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git01.mediatek.com / filogic / uboot / 8cea9b56065ebbd9af6f865553b20fb9ef3762f0 / . / include / configs / ls1046aqds.h
blob: cba22ca2b6156973299f0ef978bb8ab4b4fddd92 [file] [log] [blame]
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800[diff] [blame]1/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS1046AQDS_H__
8#define __LS1046AQDS_H__
9
10#include "ls1046a_common.h"
11
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800[diff] [blame]12#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
13#define CONFIG_SYS_TEXT_BASE 0x82000000
14#elif defined(CONFIG_QSPI_BOOT)
15#define CONFIG_SYS_TEXT_BASE 0x40010000
16#else
17#define CONFIG_SYS_TEXT_BASE 0x60100000
18#endif
19
20#ifndef __ASSEMBLY__
21unsigned long get_board_sys_clk(void);
22unsigned long get_board_ddr_clk(void);
23#endif
24
25#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
26#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
27
28#define CONFIG_SKIP_LOWLEVEL_INIT
29
30#define CONFIG_LAYERSCAPE_NS_ACCESS
31
32#define CONFIG_DIMM_SLOTS_PER_CTLR 1
33/* Physical Memory Map */
34#define CONFIG_CHIP_SELECTS_PER_CTRL 4
35#define CONFIG_NR_DRAM_BANKS 2
36
37#define CONFIG_DDR_SPD
38#define SPD_EEPROM_ADDRESS 0x51
39#define CONFIG_SYS_SPD_BUS_NUM 0
40
41#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
42
43#define CONFIG_DDR_ECC
44#ifdef CONFIG_DDR_ECC
45#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
46#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47#endif
48
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800[diff] [blame]49/* DSPI */
50#ifdef CONFIG_FSL_DSPI
51#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
52#define CONFIG_SPI_FLASH_SST /* cs1 */
53#define CONFIG_SPI_FLASH_EON /* cs2 */
54#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
55#define CONFIG_SF_DEFAULT_BUS 1
56#define CONFIG_SF_DEFAULT_CS 0
57#endif
58#endif
59
60/* QSPI */
61#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
62#ifdef CONFIG_FSL_QSPI
63#define CONFIG_SPI_FLASH_SPANSION
64#define FSL_QSPI_FLASH_SIZE (1 << 24)
65#define FSL_QSPI_FLASH_NUM 2
66#endif
67#endif
68
69#ifdef CONFIG_SYS_DPAA_FMAN
70#define CONFIG_FMAN_ENET
71#define CONFIG_PHYLIB
72#define CONFIG_PHY_VITESSE
73#define CONFIG_PHY_REALTEK
74#define CONFIG_PHYLIB_10G
75#define RGMII_PHY1_ADDR 0x1
76#define RGMII_PHY2_ADDR 0x2
77#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
78#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
79#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
80#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
81/* PHY address on QSGMII riser card on slot 2 */
82#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
83#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
84#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
85#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
86#endif
87
88#ifdef CONFIG_RAMBOOT_PBL
89#define CONFIG_SYS_FSL_PBL_PBI \
90 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
91#endif
92
93#ifdef CONFIG_NAND_BOOT
94#define CONFIG_SYS_FSL_PBL_RCW \
95 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
96#endif
97
98#ifdef CONFIG_SD_BOOT
99#ifdef CONFIG_SD_BOOT_QSPI
100#define CONFIG_SYS_FSL_PBL_RCW \
101 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
102#else
103#define CONFIG_SYS_FSL_PBL_RCW \
104 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
105#endif
106#endif
107
108/* IFC */
109#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
110#define CONFIG_FSL_IFC
111/*
112 * CONFIG_SYS_FLASH_BASE has the final address (core view)
113 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
114 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
115 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
116 */
117#define CONFIG_SYS_FLASH_BASE 0x60000000
118#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
119#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
120
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900[diff] [blame^]121#ifdef CONFIG_MTD_NOR_FLASH
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800[diff] [blame]122#define CONFIG_FLASH_CFI_DRIVER
123#define CONFIG_SYS_FLASH_CFI
124#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
125#define CONFIG_SYS_FLASH_QUIET_TEST
126#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
127#endif
128#endif
129
Shaohui Xie56007a02016-10-28 14:24:02 +0800[diff] [blame]130/* LPUART */
131#ifdef CONFIG_LPUART
132#define CONFIG_LPUART_32B_REG
133#define CFG_UART_MUX_MASK 0x6
134#define CFG_UART_MUX_SHIFT 1
135#define CFG_LPUART_EN 0x2
136#endif
137
Tang Yuantianbe1d2f32017-01-20 17:12:14 +0800[diff] [blame]138/* USB */
139#define CONFIG_HAS_FSL_XHCI_USB
140#ifdef CONFIG_HAS_FSL_XHCI_USB
141#define CONFIG_USB_XHCI_HCD
142#define CONFIG_USB_XHCI_FSL
143#define CONFIG_USB_XHCI_DWC3
144#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
145#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
146#define CONFIG_CMD_USB
147#define CONFIG_USB_STORAGE
148#endif
149
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800[diff] [blame]150/* SATA */
151#define CONFIG_LIBATA
152#define CONFIG_SCSI_AHCI
153#define CONFIG_SCSI_AHCI_PLAT
154#define CONFIG_SCSI
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800[diff] [blame]155
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800[diff] [blame]156/* EEPROM */
157#define CONFIG_ID_EEPROM
158#define CONFIG_SYS_I2C_EEPROM_NXID
159#define CONFIG_SYS_EEPROM_BUS_NUM 0
160#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
161#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
162#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
163#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
164
165#define CONFIG_SYS_SATA AHCI_BASE_ADDR
166
167#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
168#define CONFIG_SYS_SCSI_MAX_LUN 1
169#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
170 CONFIG_SYS_SCSI_MAX_LUN)
171
172/*
173 * IFC Definitions
174 */
175#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
176#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
177#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
178 CSPR_PORT_SIZE_16 | \
179 CSPR_MSEL_NOR | \
180 CSPR_V)
181#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
182#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
183 + 0x8000000) | \
184 CSPR_PORT_SIZE_16 | \
185 CSPR_MSEL_NOR | \
186 CSPR_V)
187#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
188
189#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
190 CSOR_NOR_TRHZ_80)
191#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
192 FTIM0_NOR_TEADC(0x5) | \
193 FTIM0_NOR_TEAHC(0x5))
194#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
195 FTIM1_NOR_TRAD_NOR(0x1a) | \
196 FTIM1_NOR_TSEQRAD_NOR(0x13))
197#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
198 FTIM2_NOR_TCH(0x4) | \
199 FTIM2_NOR_TWPH(0xe) | \
200 FTIM2_NOR_TWP(0x1c))
201#define CONFIG_SYS_NOR_FTIM3 0
202
203#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
204#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
205#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
206#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
207
208#define CONFIG_SYS_FLASH_EMPTY_INFO
209#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
210 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
211
212#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
213#define CONFIG_SYS_WRITE_SWAPPED_DATA
214
215/*
216 * NAND Flash Definitions
217 */
218#define CONFIG_NAND_FSL_IFC
219
220#define CONFIG_SYS_NAND_BASE 0x7e800000
221#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
222
223#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
224
225#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
226 | CSPR_PORT_SIZE_8 \
227 | CSPR_MSEL_NAND \
228 | CSPR_V)
229#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
230#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
231 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
232 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
233 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
234 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
235 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
236 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
237
238#define CONFIG_SYS_NAND_ONFI_DETECTION
239
240#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
241 FTIM0_NAND_TWP(0x18) | \
242 FTIM0_NAND_TWCHT(0x7) | \
243 FTIM0_NAND_TWH(0xa))
244#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
245 FTIM1_NAND_TWBE(0x39) | \
246 FTIM1_NAND_TRR(0xe) | \
247 FTIM1_NAND_TRP(0x18))
248#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
249 FTIM2_NAND_TREH(0xa) | \
250 FTIM2_NAND_TWHRE(0x1e))
251#define CONFIG_SYS_NAND_FTIM3 0x0
252
253#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
254#define CONFIG_SYS_MAX_NAND_DEVICE 1
255#define CONFIG_MTD_NAND_VERIFY_WRITE
256#define CONFIG_CMD_NAND
257
258#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
259#endif
260
261#ifdef CONFIG_NAND_BOOT
262#define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
263#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
264#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
265#endif
266
267#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
268#define CONFIG_QIXIS_I2C_ACCESS
269#define CONFIG_SYS_I2C_EARLY_INIT
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800[diff] [blame]270#endif
271
272/*
273 * QIXIS Definitions
274 */
275#define CONFIG_FSL_QIXIS
276
277#ifdef CONFIG_FSL_QIXIS
278#define QIXIS_BASE 0x7fb00000
279#define QIXIS_BASE_PHYS QIXIS_BASE
280#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
281#define QIXIS_LBMAP_SWITCH 6
282#define QIXIS_LBMAP_MASK 0x0f
283#define QIXIS_LBMAP_SHIFT 0
284#define QIXIS_LBMAP_DFLTBANK 0x00
285#define QIXIS_LBMAP_ALTBANK 0x04
286#define QIXIS_LBMAP_NAND 0x09
287#define QIXIS_LBMAP_SD 0x00
288#define QIXIS_LBMAP_SD_QSPI 0xff
289#define QIXIS_LBMAP_QSPI 0xff
290#define QIXIS_RCW_SRC_NAND 0x110
291#define QIXIS_RCW_SRC_SD 0x040
292#define QIXIS_RCW_SRC_QSPI 0x045
293#define QIXIS_RST_CTL_RESET 0x41
294#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
295#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
296#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
297
298#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
299#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
300 CSPR_PORT_SIZE_8 | \
301 CSPR_MSEL_GPCM | \
302 CSPR_V)
303#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
304#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
305 CSOR_NOR_NOR_MODE_AVD_NOR | \
306 CSOR_NOR_TRHZ_80)
307
308/*
309 * QIXIS Timing parameters for IFC GPCM
310 */
311#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
312 FTIM0_GPCM_TEADC(0x20) | \
313 FTIM0_GPCM_TEAHC(0x10))
314#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
315 FTIM1_GPCM_TRAD(0x1f))
316#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
317 FTIM2_GPCM_TCH(0x8) | \
318 FTIM2_GPCM_TWP(0xf0))
319#define CONFIG_SYS_FPGA_FTIM3 0x0
320#endif
321
322#ifdef CONFIG_NAND_BOOT
323#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
324#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
325#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
326#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
327#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
328#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
329#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
330#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
331#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
332#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
333#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
334#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
335#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
336#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
337#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
338#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
339#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
340#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
341#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
342#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
343#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
344#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
345#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
346#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
347#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
348#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
349#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
350#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
351#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
352#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
353#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
354#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
355#else
356#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
357#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
358#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
359#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
360#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
361#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
362#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
363#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
364#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
365#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
366#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
367#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
368#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
369#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
370#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
371#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
372#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
373#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
374#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
375#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
376#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
377#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
378#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
379#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
380#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
381#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
382#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
383#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
384#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
385#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
386#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
387#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
388#endif
389
390/*
391 * I2C bus multiplexer
392 */
393#define I2C_MUX_PCA_ADDR_PRI 0x77
394#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
395#define I2C_RETIMER_ADDR 0x18
396#define I2C_MUX_CH_DEFAULT 0x8
397#define I2C_MUX_CH_CH7301 0xC
398#define I2C_MUX_CH5 0xD
399#define I2C_MUX_CH6 0xE
400#define I2C_MUX_CH7 0xF
401
402#define I2C_MUX_CH_VOL_MONITOR 0xa
403
404/* Voltage monitor on channel 2*/
405#define I2C_VOL_MONITOR_ADDR 0x40
406#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
407#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
408#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
409
410#define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
411#ifndef CONFIG_SPL_BUILD
412#define CONFIG_VID
413#endif
414#define CONFIG_VOL_MONITOR_IR36021_SET
415#define CONFIG_VOL_MONITOR_INA220
416/* The lowest and highest voltage allowed for LS1046AQDS */
417#define VDD_MV_MIN 819
418#define VDD_MV_MAX 1212
419
420/*
421 * Miscellaneous configurable options
422 */
423#define CONFIG_MISC_INIT_R
424#define CONFIG_SYS_LONGHELP /* undef to save memory */
425#define CONFIG_AUTO_COMPLETE
426#define CONFIG_SYS_PBSIZE \
427 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
428#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
429
430#define CONFIG_SYS_MEMTEST_START 0x80000000
431#define CONFIG_SYS_MEMTEST_END 0x9fffffff
432
433#define CONFIG_SYS_HZ 1000
434
435/*
436 * Stack sizes
437 * The stack sizes are set up in start.S using the settings below
438 */
439#define CONFIG_STACKSIZE (30 * 1024)
440
441#define CONFIG_SYS_INIT_SP_OFFSET \
442 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
443
444#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
445
446/*
447 * Environment
448 */
449#define CONFIG_ENV_OVERWRITE
450
451#ifdef CONFIG_NAND_BOOT
452#define CONFIG_ENV_IS_IN_NAND
453#define CONFIG_ENV_SIZE 0x2000
454#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
455#elif defined(CONFIG_SD_BOOT)
456#define CONFIG_ENV_OFFSET (1024 * 1024)
457#define CONFIG_ENV_IS_IN_MMC
458#define CONFIG_SYS_MMC_ENV_DEV 0
459#define CONFIG_ENV_SIZE 0x2000
460#elif defined(CONFIG_QSPI_BOOT)
461#define CONFIG_ENV_IS_IN_SPI_FLASH
462#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
463#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
464#define CONFIG_ENV_SECT_SIZE 0x10000
465#else
466#define CONFIG_ENV_IS_IN_FLASH
467#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
468#define CONFIG_ENV_SECT_SIZE 0x20000
469#define CONFIG_ENV_SIZE 0x20000
470#endif
471
472#define CONFIG_CMDLINE_TAG
473
474#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
475#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
476 "e0000 f00000 && bootm $kernel_load"
477#else
478#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
479 "$kernel_size && bootm $kernel_load"
480#endif
481
482#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
483#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
484 "14m(free)"
485#else
486#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
487 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
488 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
489 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
490 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
491 "40m(nor_bank4_fit);7e800000.flash:" \
492 "4m(nand_uboot),36m(nand_kernel)," \
493 "472m(nand_free);spi0.0:2m(uboot)," \
494 "14m(free)"
495#endif
496
497#include <asm/fsl_secure_boot.h>
498
499#endif /* __LS1046AQDS_H__ */