Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 2 | /* |
Kumar Gala | ad4e9d4 | 2011-01-04 17:57:59 -0600 | [diff] [blame] | 3 | * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. |
Biwen Li | 037fa1a | 2020-05-01 20:56:37 +0800 | [diff] [blame] | 4 | * Copyright 2020 NXP |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * mpc8548cds board configuration file |
| 9 | * |
| 10 | * Please refer to doc/README.mpc85xxcds for more info. |
| 11 | * |
| 12 | */ |
| 13 | #ifndef __CONFIG_H |
| 14 | #define __CONFIG_H |
| 15 | |
Kumar Gala | ad4e9d4 | 2011-01-04 17:57:59 -0600 | [diff] [blame] | 16 | #define CONFIG_SYS_SRIO |
| 17 | #define CONFIG_SRIO1 /* SRIO port 1 */ |
| 18 | |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 19 | #define CONFIG_PCI1 /* PCI controller 1 */ |
Robert P. J. Day | a809981 | 2016-05-03 19:52:49 -0400 | [diff] [blame] | 20 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 21 | #undef CONFIG_PCI2 |
Kumar Gala | 7738d5c | 2008-10-21 11:33:58 -0500 | [diff] [blame] | 22 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 23 | |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 24 | #define CONFIG_ENV_OVERWRITE |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 25 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 26 | |
Jon Loeliger | 6bcdb40 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 27 | #define CONFIG_FSL_VIA |
Jon Loeliger | 6bcdb40 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 28 | |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 29 | #ifndef __ASSEMBLY__ |
Simon Glass | fb64e36 | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 30 | #include <linux/stringify.h> |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 31 | extern unsigned long get_clock_freq(void); |
| 32 | #endif |
| 33 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ |
| 34 | |
| 35 | /* |
| 36 | * These can be toggled for performance analysis, otherwise use default. |
| 37 | */ |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 38 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 39 | #define CONFIG_BTB /* toggle branch predition */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 40 | |
| 41 | /* |
| 42 | * Only possible on E500 Version 2 or newer cores. |
| 43 | */ |
| 44 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 45 | |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 46 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
| 47 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 48 | |
Jon Loeliger | c378bae | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 49 | /* DDR Setup */ |
Jon Loeliger | c378bae | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 50 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
| 51 | #define CONFIG_DDR_SPD |
Jon Loeliger | c378bae | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 52 | |
chenhui zhao | 3560dbd | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 53 | #define CONFIG_DDR_ECC |
Dave Liu | d3ca124 | 2008-10-28 17:53:38 +0800 | [diff] [blame] | 54 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
Jon Loeliger | c378bae | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 55 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 56 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 57 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 58 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 59 | |
Jon Loeliger | c378bae | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 60 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 61 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 62 | |
Jon Loeliger | c378bae | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 63 | /* I2C addresses of SPD EEPROMs */ |
| 64 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
| 65 | |
| 66 | /* Make sure required options are set */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 67 | #ifndef CONFIG_SPD_EEPROM |
| 68 | #error ("CONFIG_SPD_EEPROM is required") |
| 69 | #endif |
| 70 | |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 71 | /* |
| 72 | * Physical Address Map |
| 73 | * |
| 74 | * 32bit: |
| 75 | * 0x0000_0000 0x7fff_ffff DDR 2G cacheable |
| 76 | * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable |
| 77 | * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable |
| 78 | * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable |
| 79 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable |
| 80 | * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable |
| 81 | * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable |
| 82 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable |
| 83 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable |
| 84 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable |
| 85 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable |
| 86 | * |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 87 | * 36bit: |
| 88 | * 0x00000_0000 0x07fff_ffff DDR 2G cacheable |
| 89 | * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable |
| 90 | * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable |
| 91 | * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable |
| 92 | * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable |
| 93 | * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable |
| 94 | * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable |
| 95 | * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable |
| 96 | * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable |
| 97 | * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable |
| 98 | * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable |
| 99 | * |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 100 | */ |
| 101 | |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 102 | /* |
| 103 | * Local Bus Definitions |
| 104 | */ |
| 105 | |
| 106 | /* |
| 107 | * FLASH on the Local Bus |
| 108 | * Two banks, 8M each, using the CFI driver. |
| 109 | * Boot from BR0/OR0 bank at 0xff00_0000 |
| 110 | * Alternate BR1/OR1 bank at 0xff80_0000 |
| 111 | * |
| 112 | * BR0, BR1: |
| 113 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 |
| 114 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 |
| 115 | * Port Size = 16 bits = BRx[19:20] = 10 |
| 116 | * Use GPCM = BRx[24:26] = 000 |
| 117 | * Valid = BRx[31] = 1 |
| 118 | * |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 119 | * 0 4 8 12 16 20 24 28 |
| 120 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 |
| 121 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 122 | * |
| 123 | * OR0, OR1: |
| 124 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 |
| 125 | * Reserved ORx[17:18] = 11, confusion here? |
| 126 | * CSNT = ORx[20] = 1 |
| 127 | * ACS = half cycle delay = ORx[21:22] = 11 |
| 128 | * SCY = 6 = ORx[24:27] = 0110 |
| 129 | * TRLX = use relaxed timing = ORx[29] = 1 |
| 130 | * EAD = use external address latch delay = OR[31] = 1 |
| 131 | * |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 132 | * 0 4 8 12 16 20 24 28 |
| 133 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 134 | */ |
| 135 | |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 136 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 137 | #ifdef CONFIG_PHYS_64BIT |
| 138 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull |
| 139 | #else |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 140 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 141 | #endif |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 142 | |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 143 | #define CONFIG_SYS_BR0_PRELIM \ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 144 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 145 | #define CONFIG_SYS_BR1_PRELIM \ |
| 146 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 147 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 148 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
| 149 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 150 | |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 151 | #define CONFIG_SYS_FLASH_BANKS_LIST \ |
| 152 | {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 153 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 154 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
| 155 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 156 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 157 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 158 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 159 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 160 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 161 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 162 | |
chenhui zhao | 3560dbd | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 163 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 164 | |
| 165 | /* |
| 166 | * SDRAM on the Local Bus |
| 167 | */ |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 168 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 169 | #ifdef CONFIG_PHYS_64BIT |
| 170 | #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull |
| 171 | #else |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 172 | #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 173 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 174 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 175 | |
| 176 | /* |
| 177 | * Base Register 2 and Option Register 2 configure SDRAM. |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 179 | * |
| 180 | * For BR2, need: |
| 181 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
| 182 | * port-size = 32-bits = BR2[19:20] = 11 |
| 183 | * no parity checking = BR2[21:22] = 00 |
| 184 | * SDRAM for MSEL = BR2[24:26] = 011 |
| 185 | * Valid = BR[31] = 1 |
| 186 | * |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 187 | * 0 4 8 12 16 20 24 28 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 188 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
| 189 | * |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 191 | * FIXME: the top 17 bits of BR2. |
| 192 | */ |
| 193 | |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 194 | #define CONFIG_SYS_BR2_PRELIM \ |
| 195 | (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ |
| 196 | | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 197 | |
| 198 | /* |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 199 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 200 | * |
| 201 | * For OR2, need: |
| 202 | * 64MB mask for AM, OR2[0:7] = 1111 1100 |
| 203 | * XAM, OR2[17:18] = 11 |
| 204 | * 9 columns OR2[19-21] = 010 |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 205 | * 13 rows OR2[23-25] = 100 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 206 | * EAD set for extra time OR[31] = 1 |
| 207 | * |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 208 | * 0 4 8 12 16 20 24 28 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 209 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
| 210 | */ |
| 211 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 212 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 213 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 214 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
| 215 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ |
| 216 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
| 217 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 218 | |
| 219 | /* |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 220 | * Common settings for all Local Bus SDRAM commands. |
| 221 | * At run time, either BSMA1516 (for CPU 1.1) |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 222 | * or BSMA1617 (for CPU 1.0) (old) |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 223 | * is OR'ed in too. |
| 224 | */ |
Kumar Gala | 727c6a6 | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 225 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
| 226 | | LSDMR_PRETOACT7 \ |
| 227 | | LSDMR_ACTTORW7 \ |
| 228 | | LSDMR_BL8 \ |
| 229 | | LSDMR_WRC4 \ |
| 230 | | LSDMR_CL3 \ |
| 231 | | LSDMR_RFEN \ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 232 | ) |
| 233 | |
| 234 | /* |
| 235 | * The CADMUS registers are connected to CS3 on CDS. |
| 236 | * The new memory map places CADMUS at 0xf8000000. |
| 237 | * |
| 238 | * For BR3, need: |
| 239 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 |
| 240 | * port-size = 8-bits = BR[19:20] = 01 |
| 241 | * no parity checking = BR[21:22] = 00 |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 242 | * GPMC for MSEL = BR[24:26] = 000 |
| 243 | * Valid = BR[31] = 1 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 244 | * |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 245 | * 0 4 8 12 16 20 24 28 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 246 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
| 247 | * |
| 248 | * For OR3, need: |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 249 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 250 | * disable buffer ctrl OR[19] = 0 |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 251 | * CSNT OR[20] = 1 |
| 252 | * ACS OR[21:22] = 11 |
| 253 | * XACS OR[23] = 1 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 254 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 255 | * SETA OR[28] = 0 |
| 256 | * TRLX OR[29] = 1 |
| 257 | * EHTR OR[30] = 1 |
| 258 | * EAD extra time OR[31] = 1 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 259 | * |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 260 | * 0 4 8 12 16 20 24 28 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 261 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
| 262 | */ |
| 263 | |
Jon Loeliger | 6bcdb40 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 264 | #define CONFIG_FSL_CADMUS |
| 265 | |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 266 | #define CADMUS_BASE_ADDR 0xf8000000 |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 267 | #ifdef CONFIG_PHYS_64BIT |
| 268 | #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull |
| 269 | #else |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 270 | #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 271 | #endif |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 272 | #define CONFIG_SYS_BR3_PRELIM \ |
| 273 | (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 274 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 275 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 276 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 277 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 278 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 279 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 280 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 281 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 282 | |
Hou Zhiqiang | 8547bb2 | 2019-08-20 09:35:35 +0000 | [diff] [blame] | 283 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
chenhui zhao | 3560dbd | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 284 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 285 | |
| 286 | /* Serial Port */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 287 | #define CONFIG_SYS_NS16550_SERIAL |
| 288 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 289 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 290 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 291 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 292 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 293 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 294 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 295 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 296 | |
Jon Loeliger | 43d818f | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 297 | /* |
| 298 | * I2C |
| 299 | */ |
Biwen Li | 037fa1a | 2020-05-01 20:56:37 +0800 | [diff] [blame] | 300 | #ifndef CONFIG_DM_I2C |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 301 | #define CONFIG_SYS_I2C |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 302 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 303 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 304 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 305 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } |
Biwen Li | 037fa1a | 2020-05-01 20:56:37 +0800 | [diff] [blame] | 306 | #else |
| 307 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 308 | #define CONFIG_I2C_SET_DEFAULT_BUS_NUM |
| 309 | #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 |
| 310 | #endif |
| 311 | #define CONFIG_SYS_I2C_FSL |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 312 | |
Timur Tabi | 0b87d3f | 2008-07-18 16:52:23 +0200 | [diff] [blame] | 313 | /* EEPROM */ |
| 314 | #define CONFIG_ID_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 315 | #define CONFIG_SYS_I2C_EEPROM_CCID |
| 316 | #define CONFIG_SYS_ID_EEPROM |
| 317 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 318 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
Timur Tabi | 0b87d3f | 2008-07-18 16:52:23 +0200 | [diff] [blame] | 319 | |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 320 | /* |
| 321 | * General PCI |
Sergei Shtylyov | 6ffad93 | 2006-12-27 22:07:15 +0300 | [diff] [blame] | 322 | * Memory space is mapped 1-1, but I/O space must start from 0. |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 323 | */ |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 324 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 325 | #ifdef CONFIG_PHYS_64BIT |
| 326 | #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 |
| 327 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull |
| 328 | #else |
Kumar Gala | 3fe8087 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 329 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 330 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 331 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 332 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 333 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
Kumar Gala | 64bb6d1 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 334 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 335 | #ifdef CONFIG_PHYS_64BIT |
| 336 | #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull |
| 337 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 338 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 339 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 340 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 341 | |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 342 | #ifdef CONFIG_PCIE1 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 343 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 344 | #ifdef CONFIG_PHYS_64BIT |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 345 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull |
| 346 | #else |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 347 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 348 | #endif |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 349 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 350 | #ifdef CONFIG_PHYS_64BIT |
| 351 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull |
| 352 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 353 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 354 | #endif |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 355 | #endif |
Zang Roy-r61911 | a5f77dc | 2006-12-14 14:14:55 +0800 | [diff] [blame] | 356 | |
| 357 | /* |
| 358 | * RapidIO MMU |
| 359 | */ |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 360 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 361 | #ifdef CONFIG_PHYS_64BIT |
| 362 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull |
| 363 | #else |
chenhui zhao | e97171e | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 364 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 |
chenhui zhao | a9dd52d | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 365 | #endif |
Kumar Gala | ad4e9d4 | 2011-01-04 17:57:59 -0600 | [diff] [blame] | 366 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 367 | |
Randy Vinson | 1dfd6d9 | 2007-02-27 19:42:22 -0700 | [diff] [blame] | 368 | #ifdef CONFIG_LEGACY |
| 369 | #define BRIDGE_ID 17 |
| 370 | #define VIA_ID 2 |
| 371 | #else |
| 372 | #define BRIDGE_ID 28 |
| 373 | #define VIA_ID 4 |
| 374 | #endif |
| 375 | |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 376 | #if defined(CONFIG_PCI) |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 377 | #undef CONFIG_TULIP |
| 378 | |
Hou Zhiqiang | f2e520c | 2019-08-27 11:05:26 +0000 | [diff] [blame] | 379 | #if !defined(CONFIG_DM_PCI) |
| 380 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
| 381 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 |
| 382 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
| 383 | #ifdef CONFIG_PHYS_64BIT |
| 384 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| 385 | #else |
| 386 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
| 387 | #endif |
| 388 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| 389 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 390 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ |
| 391 | #endif |
| 392 | |
chenhui zhao | 3560dbd | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 393 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 394 | |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 395 | #endif /* CONFIG_PCI */ |
| 396 | |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 397 | #if defined(CONFIG_TSEC_ENET) |
| 398 | |
Kim Phillips | 177e58f | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 399 | #define CONFIG_TSEC1 1 |
| 400 | #define CONFIG_TSEC1_NAME "eTSEC0" |
| 401 | #define CONFIG_TSEC2 1 |
| 402 | #define CONFIG_TSEC2_NAME "eTSEC1" |
| 403 | #define CONFIG_TSEC3 1 |
| 404 | #define CONFIG_TSEC3_NAME "eTSEC2" |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 405 | #define CONFIG_TSEC4 |
Kim Phillips | 177e58f | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 406 | #define CONFIG_TSEC4_NAME "eTSEC3" |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 407 | #undef CONFIG_MPC85XX_FEC |
| 408 | |
| 409 | #define TSEC1_PHY_ADDR 0 |
| 410 | #define TSEC2_PHY_ADDR 1 |
| 411 | #define TSEC3_PHY_ADDR 2 |
| 412 | #define TSEC4_PHY_ADDR 3 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 413 | |
| 414 | #define TSEC1_PHYIDX 0 |
| 415 | #define TSEC2_PHYIDX 0 |
| 416 | #define TSEC3_PHYIDX 0 |
| 417 | #define TSEC4_PHYIDX 0 |
Andy Fleming | 09b88df | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 418 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 419 | #define TSEC2_FLAGS TSEC_GIGABIT |
| 420 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 421 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 422 | |
| 423 | /* Options are: eTSEC[0-3] */ |
| 424 | #define CONFIG_ETHPRIME "eTSEC0" |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 425 | #endif /* CONFIG_TSEC_ENET */ |
| 426 | |
| 427 | /* |
| 428 | * Environment |
| 429 | */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 430 | |
| 431 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 432 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 433 | |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 434 | /* |
Jon Loeliger | ed26c74 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 435 | * BOOTP options |
| 436 | */ |
| 437 | #define CONFIG_BOOTP_BOOTFILESIZE |
Jon Loeliger | ed26c74 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 438 | |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 439 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 440 | |
| 441 | /* |
| 442 | * Miscellaneous configurable options |
| 443 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 444 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 445 | |
| 446 | /* |
| 447 | * For booting Linux, the board info and command line data |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 448 | * have to be in the first 64 MB of memory, since this is |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 449 | * the maximum mapped by the Linux kernel during initialization. |
| 450 | */ |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 451 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 452 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 453 | |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 454 | #if defined(CONFIG_CMD_KGDB) |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 455 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 456 | #endif |
| 457 | |
| 458 | /* |
| 459 | * Environment Configuration |
| 460 | */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 461 | #if defined(CONFIG_TSEC_ENET) |
Andy Fleming | 458c389 | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 462 | #define CONFIG_HAS_ETH0 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 463 | #define CONFIG_HAS_ETH1 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 464 | #define CONFIG_HAS_ETH2 |
Andy Fleming | 239e75f | 2006-09-13 10:34:18 -0500 | [diff] [blame] | 465 | #define CONFIG_HAS_ETH3 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 466 | #endif |
| 467 | |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 468 | #define CONFIG_IPADDR 192.168.1.253 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 469 | |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 470 | #define CONFIG_HOSTNAME "unknown" |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 471 | #define CONFIG_ROOTPATH "/nfsroot" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 472 | #define CONFIG_BOOTFILE "8548cds/uImage.uboot" |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 473 | #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 474 | |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 475 | #define CONFIG_SERVERIP 192.168.1.1 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 476 | #define CONFIG_GATEWAYIP 192.168.1.1 |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 477 | #define CONFIG_NETMASK 255.255.255.0 |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 478 | |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 479 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 480 | |
chenhui zhao | 3560dbd | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 481 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 482 | "hwconfig=fsl_ddr:ecc=off\0" \ |
| 483 | "netdev=eth0\0" \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 484 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
chenhui zhao | 3560dbd | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 485 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 486 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 487 | " +$filesize; " \ |
| 488 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 489 | " +$filesize; " \ |
| 490 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 491 | " $filesize; " \ |
| 492 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 493 | " +$filesize; " \ |
| 494 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 495 | " $filesize\0" \ |
chenhui zhao | 3560dbd | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 496 | "consoledev=ttyS1\0" \ |
| 497 | "ramdiskaddr=2000000\0" \ |
| 498 | "ramdiskfile=ramdisk.uboot\0" \ |
Scott Wood | b7f4b85 | 2016-07-19 17:52:06 -0500 | [diff] [blame] | 499 | "fdtaddr=1e00000\0" \ |
chenhui zhao | 3560dbd | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 500 | "fdtfile=mpc8548cds.dtb\0" |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 501 | |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 502 | #define CONFIG_NFSBOOTCOMMAND \ |
| 503 | "setenv bootargs root=/dev/nfs rw " \ |
| 504 | "nfsroot=$serverip:$rootpath " \ |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 505 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 506 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 507 | "tftp $loadaddr $bootfile;" \ |
Ed Swarthout | f66cbc8 | 2007-08-21 09:38:59 -0500 | [diff] [blame] | 508 | "tftp $fdtaddr $fdtfile;" \ |
| 509 | "bootm $loadaddr - $fdtaddr" |
Andy Fleming | 7243f97 | 2006-09-13 10:33:35 -0500 | [diff] [blame] | 510 | |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 511 | #define CONFIG_RAMBOOTCOMMAND \ |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 512 | "setenv bootargs root=/dev/ram rw " \ |
| 513 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 514 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 515 | "tftp $loadaddr $bootfile;" \ |
Ed Swarthout | f66cbc8 | 2007-08-21 09:38:59 -0500 | [diff] [blame] | 516 | "tftp $fdtaddr $fdtfile;" \ |
| 517 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 518 | |
Ed Swarthout | 95ae0a0 | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 519 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 520 | |
| 521 | #endif /* __CONFIG_H */ |