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git01.mediatek.com / filogic / uboot / 98185eb2f6aa4874617ec72470ab769ddaa2db83 / . / drivers / usb / host / Kconfig
blob: 6e10b629a3c2142306a3d23b22a0b978bff3c03d [file] [log] [blame]
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]1#
2# USB Host Controller Drivers
3#
4comment "USB Host Controller Drivers"
5
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]6config USB_HOST
7 bool
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]8 select DM_USB
Marek Vasut1d5c59c2023-05-06 16:42:37 +0200[diff] [blame]9 help
10 Enable access to USB (Universal Serial Bus) host devices so that
11 SPL can load U-Boot from a connected USB peripheral, such as a USB
12 flash stick. While USB takes a little longer to start up than most
13 buses, it is very flexible since many different types of storage
14 device can be attached.
15
16config SPL_USB_HOST
17 bool "Support USB host drivers"
18 depends on SPL
19 help
20 For detailed help see USB_HOST Kconfig symbol. This option enables
21 the drivers in drivers/usb/host as part of an SPL build.
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]22
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]23config USB_XHCI_HCD
24 bool "xHCI HCD (USB 3.0) support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]25 depends on DM && OF_CONTROL
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]26 select USB_HOST
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]27 ---help---
28 The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
29 "SuperSpeed" host controller hardware.
30
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]31if USB_XHCI_HCD
32
Masahiro Yamadad3b72ca2016-06-04 07:35:04 +0900[diff] [blame]33config USB_XHCI_DWC3
34 bool "DesignWare USB3 DRD Core Support"
35 help
36 Say Y or if your system has a Dual Role SuperSpeed
37 USB controller based on the DesignWare USB3 IP Core.
38
Neil Armstrong069421e2018-04-11 17:08:00 +0200[diff] [blame]39config USB_XHCI_DWC3_OF_SIMPLE
40 bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
Jean-Jacques Hiblot74d9a9d2018-04-12 10:41:10 +0200[diff] [blame]41 depends on DM_USB
Jean-Jacques Hiblot6c705f42018-04-12 10:41:11 +0200[diff] [blame]42 default y if DRA7XX
Neil Armstrong069421e2018-04-11 17:08:00 +0200[diff] [blame]43 help
44 Support USB2/3 functionality in simple SoC integrations with
45 USB controller based on the DesignWare USB3 IP Core.
46
Tom Rini6d772e52022-06-10 23:03:00 -0400[diff] [blame]47config USB_XHCI_EXYNOS
48 bool "Support for Samsung Exynos5 family on-chip xHCI USB controller"
49 depends on ARCH_EXYNOS5
50 default y
51 help
52 Enables support for he on-chip xHCI controller on Samsung Exynos5
53 SoCs.
54
developer507fc9b2020-05-02 11:35:18 +0200[diff] [blame]55config USB_XHCI_MTK
56 bool "Support for MediaTek on-chip xHCI USB controller"
developer4adcdca2022-05-20 11:22:56 +0800[diff] [blame]57 depends on ARCH_MEDIATEK || SOC_MT7621
developer507fc9b2020-05-02 11:35:18 +0200[diff] [blame]58 help
59 Enables support for the on-chip xHCI controller on MediaTek SoCs.
60
Stefan Roese07faf112016-07-14 11:39:20 +0200[diff] [blame]61config USB_XHCI_MVEBU
62 bool "MVEBU USB 3.0 support"
63 default y
64 depends on ARCH_MVEBU
Konstantin Porotchkin1b5ed4d2017-02-12 11:10:30 +0200[diff] [blame]65 select DM_REGULATOR
Stefan Roese07faf112016-07-14 11:39:20 +0200[diff] [blame]66 help
67 Choose this option to add support for USB 3.0 driver on mvebu
68 SoCs, which includes Armada8K, Armada3700 and other Armada
69 family SoCs.
70
Stefan Roesedf33b572020-08-24 13:04:38 +0200[diff] [blame]71config USB_XHCI_OCTEON
72 bool "Support for Marvell Octeon family on-chip xHCI USB controller"
73 depends on ARCH_OCTEON
74 default y
75 help
76 Enables support for the on-chip xHCI controller on Marvell Octeon
77 family SoCs. This is a driver for the dwc3 to provide the glue logic
78 to configure the controller.
79
Tom Riniebc1c842021-09-12 20:32:22 -0400[diff] [blame]80config USB_XHCI_OMAP
81 bool "Support for TI OMAP family xHCI USB controller"
82 depends on ARCH_OMAP2PLUS
83 help
84 Enables support for the on-chip xHCI controller found on some TI SoC
85 families. Note that some families have multiple contollers while
86 others only have something such as DesignWare-based controllers.
87 Consult the SoC documentation to determine if this option applies
88 to your hardware.
89
Bin Mengd34d6fc2017-07-19 21:50:08 +0800[diff] [blame]90config USB_XHCI_PCI
91 bool "Support for PCI-based xHCI USB controller"
Heinrich Schuchardt9c83bad2023-11-20 15:56:36 +0100[diff] [blame]92 depends on DM_USB && PCI
Bin Mengd34d6fc2017-07-19 21:50:08 +0800[diff] [blame]93 default y if X86
94 help
95 Enables support for the PCI-based xHCI controller.
96
Marek Vasut24257272017-10-15 15:01:29 +0200[diff] [blame]97config USB_XHCI_RCAR
98 bool "Renesas RCar USB 3.0 support"
99 default y
Marek Vasut6468c4c2024-02-27 17:05:55 +0100[diff] [blame]100 depends on ARCH_RENESAS
Marek Vasut24257272017-10-15 15:01:29 +0200[diff] [blame]101 help
102 Choose this option to add support for USB 3.0 driver on Renesas
103 RCar Gen3 SoCs.
104
Patrice Chotardf2505b12017-09-05 11:04:24 +0200[diff] [blame]105config USB_XHCI_STI
106 bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller"
107 depends on ARCH_STI
108 default y
109 help
110 Enables support for the on-chip xHCI controller on STMicroelectronics
111 STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic
112 to configure the controller.
113
Uri Mashiachf6ff74e2017-02-23 15:39:36 +0200[diff] [blame]114config USB_XHCI_DRA7XX_INDEX
115 int "DRA7XX xHCI USB index"
116 range 0 1
117 default 0
118 depends on DRA7XX
119 help
120 Select the DRA7XX xHCI USB index.
121 Current supported values: 0, 1.
122
Ran Wanga5a97352017-10-23 10:09:22 +0800[diff] [blame]123config USB_XHCI_FSL
124 bool "Support for NXP Layerscape on-chip xHCI USB controller"
125 default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2
126 depends on !SPL_NO_USB
127 help
128 Enables support for the on-chip xHCI controller on NXP Layerscape SoCs.
Rayagonda Kokatanurf59d24e2020-04-09 09:23:15 +0530[diff] [blame]129
130config USB_XHCI_BRCM
131 bool "Broadcom USB3 Host XHCI controller"
132 depends on DM_USB
133 help
134 USB controller based on the Broadcom USB3 IP Core.
135 Supports USB2/3 functionality.
136
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]137endif # USB_XHCI_HCD
Alexey Brodkin83fd3122015-12-14 17:18:50 +0300[diff] [blame]138
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]139config EHCI_DESC_BIG_ENDIAN
140 bool
141
142config EHCI_MMIO_BIG_ENDIAN
143 bool
144
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]145config USB_EHCI_HCD
146 bool "EHCI HCD (USB 2.0) support"
Tom Rini7716cd62017-05-12 22:33:28 -0400[diff] [blame]147 default y if ARCH_MX5 || ARCH_MX6
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]148 depends on DM && OF_CONTROL
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]149 select USB_HOST
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]150 select EHCI_DESC_BIG_ENDIAN if SYS_BIG_ENDIAN
151 select EHCI_MMIO_BIG_ENDIAN if SYS_BIG_ENDIAN
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]152 ---help---
153 The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
154 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware.
155 If your USB host controller supports USB 2.0, you will likely want to
156 configure this Host Controller Driver.
157
158 EHCI controllers are packaged with "companion" host controllers (OHCI
159 or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports
160 will connect to EHCI if the device is high speed, otherwise they
161 connect to a companion controller. If you configure EHCI, you should
162 probably configure the OHCI (for NEC and some other vendors) USB Host
163 Controller Driver or UHCI (for Via motherboards) Host Controller
164 Driver too.
165
166 You may want to read <file:Documentation/usb/ehci.txt>.
167
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]168if USB_EHCI_HCD
169
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]170config USB_EHCI_IS_TDI
171 bool
172
Wenyou Yang11e26652016-08-05 08:57:35 +0800[diff] [blame]173config USB_EHCI_ATMEL
174 bool "Support for Atmel on-chip EHCI USB controller"
175 depends on ARCH_AT91
176 default y
177 ---help---
178 Enables support for the on-chip EHCI controller on Atmel chips.
179
Tom Rini6d772e52022-06-10 23:03:00 -0400[diff] [blame]180config USB_EHCI_EXYNOS
181 bool "Support for Samsung Exynos EHCI USB controller"
182 depends on ARCH_EXYNOS
183 default y
184 ---help---
185 Enables support for the on-chip EHCI controller on Samsung Exynos
186 SoCs.
187
Stefan Roese03901022015-09-01 11:39:44 +0200[diff] [blame]188config USB_EHCI_MARVELL
Tom Rini496a4172017-05-12 22:33:29 -0400[diff] [blame]189 bool "Support for Marvell on-chip EHCI USB controller"
Trevor Woernerbb7ab072020-05-06 08:02:40 -0400[diff] [blame]190 depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X
Stefan Roese03901022015-09-01 11:39:44 +0200[diff] [blame]191 default y
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]192 select USB_EHCI_IS_TDI if !ARM64
Chris Packham927671e2022-11-05 17:23:57 +1300[diff] [blame]193 select USB_EHCI_IS_TDI if ALLEYCAT_5
Stefan Roese03901022015-09-01 11:39:44 +0200[diff] [blame]194 ---help---
195 Enables support for the on-chip EHCI controller on MVEBU SoCs.
196
Lukasz Majewski6fccaf22019-04-04 12:26:55 +0200[diff] [blame]197config USB_EHCI_MX5
198 bool "Support for i.MX5 on-chip EHCI USB controller"
199 depends on ARCH_MX5
Lukasz Majewski6fccaf22019-04-04 12:26:55 +0200[diff] [blame]200 help
201 Enables support for the on-chip EHCI controller on i.MX5 SoCs.
202
Nikita Kiryanov99241032015-07-23 17:19:35 +0300[diff] [blame]203config USB_EHCI_MX6
Ye Li9da57ea2019-10-24 10:29:32 -0300[diff] [blame]204 bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller"
Giulio Benetti13ded2c2021-05-20 16:10:15 +0200[diff] [blame]205 depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]206 select EHCI_HCD_INIT_AFTER_RESET
Nikita Kiryanov99241032015-07-23 17:19:35 +0300[diff] [blame]207 default y
208 ---help---
209 Enables support for the on-chip EHCI controller on i.MX6 SoCs.
210
Stefan Agner100fe072016-07-13 00:25:36 -0700[diff] [blame]211config USB_EHCI_MX7
212 bool "Support for i.MX7 on-chip EHCI USB controller"
Mathieu Othacehe887eef82024-02-19 18:05:31 +0100[diff] [blame]213 depends on ARCH_MX7 || IMX8M || IMX93
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]214 select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7
Mathieu Othacehe887eef82024-02-19 18:05:31 +0100[diff] [blame]215 select PHY if IMX8M || IMX93
216 select NOP_PHY if IMX8M || IMX93
Stefan Agner100fe072016-07-13 00:25:36 -0700[diff] [blame]217 default y
218 ---help---
219 Enables support for the on-chip EHCI controller on i.MX7 SoCs.
220
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]221config USB_EHCI_MXS
Lukasz Majewski7a4aba62021-12-22 10:55:06 +0100[diff] [blame]222 bool "Support for i.MX23/i.MX28 EHCI USB controller"
223 depends on ARCH_MX23 || ARCH_MX28
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]224 default y
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]225 select USB_EHCI_IS_TDI
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]226 help
Lukasz Majewski7a4aba62021-12-22 10:55:06 +0100[diff] [blame]227 Enables support for the on-chip EHCI controller on i.MX23 and
228 i.MX28 SoCs.
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]229
Jim Liu1fd3b3d2022-06-21 17:09:02 +0800[diff] [blame]230config USB_EHCI_NPCM
231 bool "Support for Nuvoton NPCM on-chip EHCI USB controller"
232 depends on ARCH_NPCM
Jim Liu1fd3b3d2022-06-21 17:09:02 +0800[diff] [blame]233 ---help---
234 Enables support for the on-chip EHCI controller on
235 Nuvoton NPCM chips.
236
Tom Rini639a8402017-05-12 22:33:30 -0400[diff] [blame]237config USB_EHCI_OMAP
238 bool "Support for OMAP3+ on-chip EHCI USB controller"
239 depends on ARCH_OMAP2PLUS
Adam Fordcb9a3562022-02-19 17:08:44 -0600[diff] [blame]240 select PHY
241 imply NOP_PHY
Tom Rini639a8402017-05-12 22:33:30 -0400[diff] [blame]242 default y
243 ---help---
244 Enables support for the on-chip EHCI controller on OMAP3 and later
245 SoCs.
246
Marcel Ziswiler31f44952019-03-25 17:24:54 +0100[diff] [blame]247config USB_EHCI_VF
248 bool "Support for Vybrid on-chip EHCI USB controller"
249 depends on ARCH_VF610
250 default y
251 help
252 Enables support for the on-chip EHCI controller on Vybrid SoCs.
253
Ye Li9da57ea2019-10-24 10:29:32 -0300[diff] [blame]254if USB_EHCI_MX6 || USB_EHCI_MX7
Stefan Agner8652ce92016-07-13 00:25:38 -0700[diff] [blame]255
256config MXC_USB_OTG_HACTIVE
257 bool "USB Power pin high active"
258 ---help---
259 Set the USB Power pin polarity to be high active (PWR_POL)
260
261endif
262
Mateusz Kulikowskidc381172016-03-31 23:12:26 +0200[diff] [blame]263config USB_EHCI_MSM
264 bool "Support for Qualcomm on-chip EHCI USB controller"
265 depends on DM_USB
266 select USB_ULPI_VIEWPORT
Ramon Fried7e365962018-09-21 13:35:50 +0300[diff] [blame]267 select MSM8916_USB_PHY
Mateusz Kulikowskidc381172016-03-31 23:12:26 +0200[diff] [blame]268 ---help---
269 Enables support for the on-chip EHCI controller on Qualcomm
270 Snapdragon SoCs.
Mateusz Kulikowskidc381172016-03-31 23:12:26 +0200[diff] [blame]271
Bin Mengec4b5732017-08-09 00:21:54 -0700[diff] [blame]272config USB_EHCI_PCI
273 bool "Support for PCI-based EHCI USB controller"
274 default y if X86
275 help
276 Enables support for the PCI-based EHCI controller.
277
Peter Robinson43ecef42019-02-20 12:17:27 +0000[diff] [blame]278config USB_EHCI_TEGRA
279 bool "Support for NVIDIA Tegra on-chip EHCI USB controller"
Trevor Woerner513f6402020-05-06 08:02:41 -0400[diff] [blame]280 depends on ARCH_TEGRA
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]281 select USB_EHCI_IS_TDI
Peter Robinson43ecef42019-02-20 12:17:27 +0000[diff] [blame]282 ---help---
283 Enable support for Tegra on-chip EHCI USB controller
284
Siva Durga Prasad Paladugu42fcc182016-07-22 14:51:51 +0530[diff] [blame]285config USB_EHCI_ZYNQ
286 bool "Support for Xilinx Zynq on-chip EHCI USB controller"
Michal Simek3239d712020-08-24 14:41:51 +0200[diff] [blame]287 default y if ARCH_ZYNQ
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]288 select USB_EHCI_IS_TDI
Siva Durga Prasad Paladugu42fcc182016-07-22 14:51:51 +0530[diff] [blame]289 ---help---
290 Enable support for Zynq on-chip EHCI USB controller
291
Alexey Brodkina6aff432015-12-02 12:32:02 +0300[diff] [blame]292config USB_EHCI_GENERIC
293 bool "Support for generic EHCI USB controller"
Alexey Brodkina6aff432015-12-02 12:32:02 +0300[diff] [blame]294 depends on DM_USB
Jagan Teki1ba41e12018-12-22 18:18:10 +0530[diff] [blame]295 default ARCH_SUNXI
Alexey Brodkina6aff432015-12-02 12:32:02 +0300[diff] [blame]296 ---help---
297 Enables support for generic EHCI controller.
298
Tom Rini30fd3d92022-06-08 08:24:27 -0400[diff] [blame]299config EHCI_HCD_INIT_AFTER_RESET
300 bool
301
Ran Wang9798b662017-12-20 10:34:20 +0800[diff] [blame]302config USB_EHCI_FSL
303 bool "Support for FSL on-chip EHCI USB controller"
Tom Rini30fd3d92022-06-08 08:24:27 -0400[diff] [blame]304 select EHCI_HCD_INIT_AFTER_RESET
Tom Rini8d7aa572022-07-31 21:08:29 -0400[diff] [blame]305 select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \
306 !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020)
Ran Wang9798b662017-12-20 10:34:20 +0800[diff] [blame]307 ---help---
308 Enables support for the on-chip EHCI controller on FSL chips.
Tom Rinic85a7922022-06-08 08:24:31 -0400[diff] [blame]309
Tom Rini8d7aa572022-07-31 21:08:29 -0400[diff] [blame]310config SYS_FSL_USB_INTERNAL_UTMI_PHY
311 bool
312 depends on USB_EHCI_FSL
313
Tom Rinic85a7922022-06-08 08:24:31 -0400[diff] [blame]314config USB_EHCI_TXFIFO_THRESH
315 hex
316 depends on USB_EHCI_TEGRA
317 default 0x10
318 help
319 This parameter affects a TXFILLTUNING field that controls how much
320 data is sent to the latency fifo before it is sent to the wire.
321 Without this parameter, the default (2) causes occasional Data Buffer
322 Errors in OUT packets depending on the buffer address and size.
323
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]324endif # USB_EHCI_HCD
325
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]326config USB_OHCI_NEW
327 bool
328
329config SYS_USB_OHCI_CPU_INIT
330 bool
331
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]332config USB_OHCI_HCD
333 bool "OHCI HCD (USB 1.1) support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]334 depends on DM && OF_CONTROL
335 select USB_HOST
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]336 select USB_OHCI_NEW
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]337 ---help---
338 The Open Host Controller Interface (OHCI) is a standard for accessing
339 USB 1.1 host controller hardware. It does more in hardware than Intel's
340 UHCI specification. If your USB host controller follows the OHCI spec,
341 say Y. On most non-x86 systems, and on x86 hardware that's not using a
342 USB controller from Intel or VIA, this is appropriate. If your host
343 controller doesn't use PCI, this is probably appropriate. For a PCI
344 based system where you're not sure, the "lspci -v" entry will list the
345 right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI.
346
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]347if USB_OHCI_HCD
348
Heiko Schocher124f9472019-07-16 10:49:07 +0200[diff] [blame]349config USB_OHCI_PCI
350 bool "Support for PCI-based OHCI USB controller"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]351 depends on PCI
Heiko Schocher124f9472019-07-16 10:49:07 +0200[diff] [blame]352 help
353 Enables support for the PCI-based OHCI controller.
354
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]355config USB_OHCI_GENERIC
356 bool "Support for generic OHCI USB controller"
Jagan Teki1ba41e12018-12-22 18:18:10 +0530[diff] [blame]357 default ARCH_SUNXI
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]358 ---help---
359 Enables support for generic OHCI controller.
360
Adam Ford5f364f52019-04-30 05:21:41 -0500[diff] [blame]361config USB_OHCI_DA8XX
362 bool "Support for da850 OHCI USB controller"
363 help
364 Enable support for the da850 USB controller.
365
Jim Liu1fd3b3d2022-06-21 17:09:02 +0800[diff] [blame]366config USB_OHCI_NPCM
367 bool "Support for Nuvoton NPCM on-chip OHCI USB controller"
368 depends on ARCH_NPCM
Jim Liu1fd3b3d2022-06-21 17:09:02 +0800[diff] [blame]369 ---help---
370 Enables support for the on-chip OHCI controller on
371 Nuvoton NPCM chips.
372
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]373endif # USB_OHCI_HCD
Masahiro Yamada718ba3c2016-08-01 00:16:33 +0900[diff] [blame]374
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]375config SYS_USB_OHCI_SLOT_NAME
376 string "Display name for the OHCI controller"
377 depends on USB_OHCI_NEW && !DM_USB
378
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]379config SYS_OHCI_SWAP_REG_ACCESS
380 bool "Perform byte swapping on OHCI controller register accesses"
381 depends on USB_OHCI_NEW
382
Masahiro Yamada718ba3c2016-08-01 00:16:33 +0900[diff] [blame]383config USB_UHCI_HCD
384 bool "UHCI HCD (most Intel and VIA) support"
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]385 select USB_HOST
Masahiro Yamada718ba3c2016-08-01 00:16:33 +0900[diff] [blame]386 ---help---
387 The Universal Host Controller Interface is a standard by Intel for
388 accessing the USB hardware in the PC (which is also called the USB
389 host controller). If your USB host controller conforms to this
390 standard, you may want to say Y, but see below. All recent boards
391 with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX,
392 i810, i820) conform to this standard. Also all VIA PCI chipsets
393 (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro
394 133) and LEON/GRLIB SoCs with the GRUSBHC controller.
395 If unsure, say Y.
396
397if USB_UHCI_HCD
398
399endif # USB_UHCI_HCD
Philipp Tomsich54983812017-07-03 18:30:06 +0200[diff] [blame]400
401config USB_DWC2
402 bool "DesignWare USB2 Core support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]403 depends on DM && OF_CONTROL
Philipp Tomsich54983812017-07-03 18:30:06 +0200[diff] [blame]404 select USB_HOST
405 ---help---
406 The DesignWare USB 2.0 controller is compliant with the
407 USB-Implementers Forum (USB-IF) USB 2.0 specifications.
408 Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps)
409 operation is compliant to the controller Supplement. If you want to
410 enable this controller in host mode, say Y.
Alexey Brodkinf19414b2018-02-28 16:16:58 +0300[diff] [blame]411
412if USB_DWC2
413config USB_DWC2_BUFFER_SIZE
414 int "Data buffer size in kB"
415 default 64
416 ---help---
417 By default 64 kB buffer is used but if amount of RAM avaialble on
418 the target is not enough to accommodate allocation of buffer of
419 that size it is possible to shrink it. Smaller sizes should be fine
420 because larger transactions could be split in smaller ones.
421
422endif # USB_DWC2
Marek Vasut88016032019-08-11 13:23:43 +0200[diff] [blame]423
424config USB_R8A66597_HCD
425 bool "Renesas R8A66597 USB Core support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]426 depends on DM && OF_CONTROL
Marek Vasut88016032019-08-11 13:23:43 +0200[diff] [blame]427 select USB_HOST
428 ---help---
429 This enables support for the on-chip Renesas R8A66597 USB 2.0
430 controller, present in various RZ and SH SoCs.
Tom Rinibde21702022-06-12 20:02:04 -0400[diff] [blame]431
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]432config USB_ATMEL
433 bool "AT91 OHCI USB support"
434 depends on ARCH_AT91
435 select SYS_USB_OHCI_CPU_INIT
436 select USB_OHCI_NEW
437
438choice
439 prompt "Clock for OHCI"
440 depends on USB_ATMEL
441
442config USB_ATMEL_CLK_SEL_PLLB
443 bool "PLLB"
444
445config USB_ATMEL_CLK_SEL_UPLL
446 bool "UPLL"
447
448endchoice
449
450config USB_OHCI_LPC32XX
451 bool "LPC32xx USB OHCI support"
452 depends on ARCH_LPC32XX
453 select SYS_USB_OHCI_CPU_INIT
454 select USB_OHCI_NEW
455
Tom Rinibde21702022-06-12 20:02:04 -0400[diff] [blame]456config USB_MAX_CONTROLLER_COUNT
457 int "Maximum number of USB host controllers"
458 depends on USB_EHCI_FSL || USB_XHCI_FSL || \
459 (SPL_USB_HOST && !DM_SPL_USB) || (USB_HOST && !DM_USB)
460 default 1