blob: 840f907acb8e19f57f279df2f5d553ff052ff14a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Eran Liberty9095d4a2005-07-28 10:08:46 -05002/*
Vivek Mahajan288f7fb2009-05-25 17:23:16 +05303 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
Eran Liberty9095d4a2005-07-28 10:08:46 -05004 */
5
6#include <common.h>
Simon Glass40d9b242020-05-10 11:40:07 -06007#include <asm-offsets.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -05008#include <mpc83xx.h>
9#include <ioports.h>
Vivek Mahajan288f7fb2009-05-25 17:23:16 +053010#include <asm/io.h>
Simon Glass156283f2017-03-28 10:27:27 -060011#include <asm/processor.h>
Heiko Schocher3b767732020-04-15 10:35:40 +020012#include <fsl_qe.h>
Kim Phillips328040a2009-09-25 18:19:44 -050013#ifdef CONFIG_USB_EHCI_FSL
Mateusz Kulikowski3add69e2016-03-31 23:12:23 +020014#include <usb/ehci-ci.h>
Vivek Mahajan288f7fb2009-05-25 17:23:16 +053015#endif
Simon Glassdbd79542020-05-10 11:40:11 -060016#include <linux/delay.h>
Heiko Schocher3b07a132020-02-03 10:23:53 +010017#ifdef CONFIG_QE
18#include <fsl_qe.h>
19#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -050020
Mario Sixb47839c2019-01-21 09:17:58 +010021#include "lblaw/lblaw.h"
Mario Six1faf95d2019-01-21 09:18:03 +010022#include "elbc/elbc.h"
Mario Six636c1082019-01-21 09:18:11 +010023#include "sysio/sysio.h"
Mario Sixaa502542019-01-21 09:18:12 +010024#include "arbiter/arbiter.h"
Mario Sixf62074e2019-01-21 09:18:13 +010025#include "initreg/initreg.h"
Mario Sixb47839c2019-01-21 09:17:58 +010026
Wolfgang Denk6405a152006-03-31 18:32:53 +020027DECLARE_GLOBAL_DATA_PTR;
28
Dave Liue732e9c2006-11-03 12:11:15 -060029#ifdef CONFIG_QE
30extern qe_iop_conf_t qe_iop_conf_tab[];
31extern void qe_config_iopin(u8 port, u8 pin, int dir,
32 int open_drain, int assign);
Dave Liue732e9c2006-11-03 12:11:15 -060033
Heiko Schocher3b07a132020-02-03 10:23:53 +010034#if !defined(CONFIG_PINCTRL)
Dave Liue732e9c2006-11-03 12:11:15 -060035static void config_qe_ioports(void)
36{
37 u8 port, pin;
38 int dir, open_drain, assign;
39 int i;
40
41 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
42 port = qe_iop_conf_tab[i].port;
43 pin = qe_iop_conf_tab[i].pin;
44 dir = qe_iop_conf_tab[i].dir;
45 open_drain = qe_iop_conf_tab[i].open_drain;
46 assign = qe_iop_conf_tab[i].assign;
47 qe_config_iopin(port, pin, dir, open_drain, assign);
48 }
49}
50#endif
Heiko Schocher3b07a132020-02-03 10:23:53 +010051#endif
Dave Liue732e9c2006-11-03 12:11:15 -060052
Eran Liberty9095d4a2005-07-28 10:08:46 -050053/*
54 * Breathe some life into the CPU...
55 *
56 * Set up the memory map,
57 * initialize a bunch of registers,
58 * initialize the UPM's
59 */
60void cpu_init_f (volatile immap_t * im)
61{
Kim Phillips328040a2009-09-25 18:19:44 -050062 __be32 sccr_mask =
63#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050064 SCCR_ENCCM |
Kim Phillips19a91de2008-01-16 12:06:16 -060065#endif
Kim Phillips328040a2009-09-25 18:19:44 -050066#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050067 SCCR_PCICM |
Kim Phillips19a91de2008-01-16 12:06:16 -060068#endif
Ilya Yanoka4f3ed32010-09-17 23:41:47 +020069#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
70 SCCR_PCIEXP1CM |
71#endif
72#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
73 SCCR_PCIEXP2CM |
74#endif
Kim Phillips328040a2009-09-25 18:19:44 -050075#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050076 SCCR_TSECCM |
Timur Tabi054838e2006-10-31 18:44:42 -060077#endif
Kim Phillips328040a2009-09-25 18:19:44 -050078#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050079 SCCR_TSEC1CM |
Timur Tabi054838e2006-10-31 18:44:42 -060080#endif
Kim Phillips328040a2009-09-25 18:19:44 -050081#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050082 SCCR_TSEC2CM |
Kumar Gala15c3f692007-02-27 23:51:42 -060083#endif
Kim Phillips328040a2009-09-25 18:19:44 -050084#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050085 SCCR_TSEC1ON |
Timur Tabi0b2deff2007-07-03 13:04:34 -050086#endif
Kim Phillips328040a2009-09-25 18:19:44 -050087#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050088 SCCR_TSEC2ON |
Timur Tabi0b2deff2007-07-03 13:04:34 -050089#endif
Kim Phillips328040a2009-09-25 18:19:44 -050090#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050091 SCCR_USBMPHCM |
Kumar Gala15c3f692007-02-27 23:51:42 -060092#endif
Kim Phillips328040a2009-09-25 18:19:44 -050093#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050094 SCCR_USBDRCM |
Kumar Gala15c3f692007-02-27 23:51:42 -060095#endif
Kim Phillips328040a2009-09-25 18:19:44 -050096#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050097 SCCR_SATACM |
Timur Tabi054838e2006-10-31 18:44:42 -060098#endif
Kim Phillips328040a2009-09-25 18:19:44 -050099 0;
100 __be32 sccr_val =
101#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
102 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
103#endif
104#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
105 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
106#endif
Ilya Yanoka4f3ed32010-09-17 23:41:47 +0200107#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
108 (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
109#endif
110#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
111 (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
112#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500113#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
114 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
115#endif
116#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
117 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
118#endif
119#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
120 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
121#endif
122#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
123 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
124#endif
125#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
126 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
127#endif
128#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
129 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
130#endif
131#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
132 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
133#endif
134#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
135 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
136#endif
137 0;
138
139 /* Pointer is writable since we allocated a register for it */
140 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
141
mario.six@gdsys.cc85df7b42017-01-17 08:33:48 +0100142 /* global data region was cleared in start.S */
Kim Phillips328040a2009-09-25 18:19:44 -0500143
144 /* system performance tweaking */
145 clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
146
147 clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
148
149 clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
Timur Tabi054838e2006-10-31 18:44:42 -0600150
Eran Liberty9095d4a2005-07-28 10:08:46 -0500151 /* RSR - Reset Status Register - clear all status (4.6.1.3) */
Simon Glass4d6eaa32012-12-13 20:48:56 +0000152 gd->arch.reset_status = __raw_readl(&im->reset.rsr);
Kim Phillips328040a2009-09-25 18:19:44 -0500153 __raw_writel(~(RSR_RES), &im->reset.rsr);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500154
Nick Spence56fd3c22008-08-28 14:09:19 -0700155 /* AER - Arbiter Event Register - store status */
Simon Glass387a1f22012-12-13 20:48:57 +0000156 gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
157 gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
Nick Spence56fd3c22008-08-28 14:09:19 -0700158
Eran Liberty9095d4a2005-07-28 10:08:46 -0500159 /*
160 * RMR - Reset Mode Register
161 * contains checkstop reset enable (4.6.1.4)
162 */
Kim Phillips328040a2009-09-25 18:19:44 -0500163 __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500164
Peter Korsgaard2a483ee2009-12-08 22:20:34 +0100165 /* LCRR - Clock Ratio Register (10.3.1.16)
166 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
167 */
Becky Bruce0d4cee12010-06-17 11:37:20 -0500168 clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
169 __raw_readl(&im->im_lbc.lcrr);
Peter Korsgaard2a483ee2009-12-08 22:20:34 +0100170 isync();
171
Kim Phillips328040a2009-09-25 18:19:44 -0500172 /* Enable Time Base & Decrementer ( so we will have udelay() )*/
173 setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500174
175 /* System General Purpose Register */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200176#ifdef CONFIG_SYS_SICRH
Mario Six0344f5e2019-01-21 09:17:27 +0100177#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
Andre Schwarzcea66482008-06-23 11:40:56 +0200178 /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
Kim Phillips328040a2009-09-25 18:19:44 -0500179 __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
180 &im->sysconf.sicrh);
Andre Schwarzcea66482008-06-23 11:40:56 +0200181#else
Kim Phillips328040a2009-09-25 18:19:44 -0500182 __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
Kumar Galae5221432006-01-11 11:12:57 -0600183#endif
Andre Schwarzcea66482008-06-23 11:40:56 +0200184#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#ifdef CONFIG_SYS_SICRL
Kim Phillips328040a2009-09-25 18:19:44 -0500186 __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
Kumar Galae5221432006-01-11 11:12:57 -0600187#endif
Gerlando Falautofe201cb2012-10-10 22:13:08 +0000188#ifdef CONFIG_SYS_GPR1
189 __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
190#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500191#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
192 __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
Dave Liue740c462006-12-07 21:13:15 +0800193#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500194#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
195 __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
Dave Liub19ecd32007-09-18 12:37:57 +0800196#endif
Dave Liue740c462006-12-07 21:13:15 +0800197
Heiko Schocher3b07a132020-02-03 10:23:53 +0100198#if !defined(CONFIG_PINCTRL)
Dave Liue732e9c2006-11-03 12:11:15 -0600199#ifdef CONFIG_QE
200 /* Config QE ioports */
201 config_qe_ioports();
202#endif
Heiko Schocher3b07a132020-02-03 10:23:53 +0100203#endif
204
Becky Bruce0d4cee12010-06-17 11:37:20 -0500205 /* Set up preliminary BR/OR regs */
206 init_early_memctl_regs();
Eran Liberty9095d4a2005-07-28 10:08:46 -0500207
Becky Bruce0d4cee12010-06-17 11:37:20 -0500208 /* Local Access window setup */
209#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210 im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
211 im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500212#else
Becky Bruce0d4cee12010-06-17 11:37:20 -0500213#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
Eran Liberty9095d4a2005-07-28 10:08:46 -0500214#endif
215
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
217 im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
218 im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500219#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200220#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
221 im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
222 im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500223#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200224#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
225 im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
226 im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500227#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
229 im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
230 im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500231#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200232#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
233 im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
234 im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500235#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
237 im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
238 im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500239#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
241 im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
242 im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500243#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200244#ifdef CONFIG_SYS_GPIO1_PRELIM
245 im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
246 im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
Kumar Galaab7ec4f2006-01-11 11:21:14 -0600247#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200248#ifdef CONFIG_SYS_GPIO2_PRELIM
249 im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
250 im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
Kumar Galaab7ec4f2006-01-11 11:21:14 -0600251#endif
Mario Six9164bdd2019-01-21 09:17:25 +0100252#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
Vivek Mahajan288f7fb2009-05-25 17:23:16 +0530253 uint32_t temp;
ramneek mehresh16b08062013-09-12 16:35:49 +0530254 struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
Vivek Mahajan288f7fb2009-05-25 17:23:16 +0530255
256 /* Configure interface. */
Vivek Mahajan2d421c12009-06-24 10:08:40 +0530257 setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
Vivek Mahajan288f7fb2009-05-25 17:23:16 +0530258
259 /* Wait for clock to stabilize */
260 do {
Kim Phillips328040a2009-09-25 18:19:44 -0500261 temp = __raw_readl(&ehci->control);
Vivek Mahajan288f7fb2009-05-25 17:23:16 +0530262 udelay(1000);
263 } while (!(temp & PHY_CLK_VALID));
264#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500265}
266
Eran Liberty9095d4a2005-07-28 10:08:46 -0500267int cpu_init_r (void)
268{
Dave Liue732e9c2006-11-03 12:11:15 -0600269#ifdef CONFIG_QE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200270 uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
Kim Phillips328040a2009-09-25 18:19:44 -0500271
Dave Liue732e9c2006-11-03 12:11:15 -0600272 qe_init(qe_base);
273 qe_reset();
274#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500275 return 0;
276}
Dave Liuebd35f82007-06-25 10:41:56 +0800277
Nick Spence56fd3c22008-08-28 14:09:19 -0700278/*
279 * Print out the bus arbiter event
280 */
281#if defined(CONFIG_DISPLAY_AER_FULL)
282static int print_83xx_arb_event(int force)
283{
284 static char* event[] = {
285 "Address Time Out",
286 "Data Time Out",
287 "Address Only Transfer Type",
288 "External Control Word Transfer Type",
289 "Reserved Transfer Type",
290 "Transfer Error",
291 "reserved",
292 "reserved"
293 };
294 static char* master[] = {
295 "e300 Core Data Transaction",
296 "reserved",
297 "e300 Core Instruction Fetch",
298 "reserved",
299 "TSEC1",
300 "TSEC2",
301 "USB MPH",
302 "USB DR",
303 "Encryption Core",
304 "I2C Boot Sequencer",
305 "JTAG",
306 "reserved",
307 "eSDHC",
308 "PCI1",
309 "PCI2",
310 "DMA",
311 "QUICC Engine 00",
312 "QUICC Engine 01",
313 "QUICC Engine 10",
314 "QUICC Engine 11",
315 "reserved",
316 "reserved",
317 "reserved",
318 "reserved",
319 "SATA1",
320 "SATA2",
321 "SATA3",
322 "SATA4",
323 "reserved",
324 "PCI Express 1",
325 "PCI Express 2",
326 "TDM-DMAC"
327 };
328 static char *transfer[] = {
329 "Address-only, Clean Block",
330 "Address-only, lwarx reservation set",
331 "Single-beat or Burst write",
332 "reserved",
333 "Address-only, Flush Block",
334 "reserved",
335 "Burst write",
336 "reserved",
337 "Address-only, sync",
338 "Address-only, tlbsync",
339 "Single-beat or Burst read",
340 "Single-beat or Burst read",
341 "Address-only, Kill Block",
342 "Address-only, icbi",
343 "Burst read",
344 "reserved",
345 "Address-only, eieio",
346 "reserved",
347 "Single-beat write",
348 "reserved",
349 "ecowx - Illegal single-beat write",
350 "reserved",
351 "reserved",
352 "reserved",
353 "Address-only, TLB Invalidate",
354 "reserved",
355 "Single-beat or Burst read",
356 "reserved",
357 "eciwx - Illegal single-beat read",
358 "reserved",
359 "Burst read",
360 "reserved"
361 };
362
Simon Glass387a1f22012-12-13 20:48:57 +0000363 int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200364 >> AEATR_EVENT_SHIFT;
Simon Glass387a1f22012-12-13 20:48:57 +0000365 int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200366 >> AEATR_MSTR_ID_SHIFT;
Simon Glass387a1f22012-12-13 20:48:57 +0000367 int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200368 >> AEATR_TBST_SHIFT;
Simon Glass387a1f22012-12-13 20:48:57 +0000369 int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200370 >> AEATR_TSIZE_SHIFT;
Simon Glass387a1f22012-12-13 20:48:57 +0000371 int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200372 >> AEATR_TTYPE_SHIFT;
Nick Spence56fd3c22008-08-28 14:09:19 -0700373
Simon Glass387a1f22012-12-13 20:48:57 +0000374 if (!force && !gd->arch.arbiter_event_address)
Nick Spence56fd3c22008-08-28 14:09:19 -0700375 return 0;
376
377 puts("Arbiter Event Status:\n");
Simon Glass387a1f22012-12-13 20:48:57 +0000378 printf(" Event Address: 0x%08lX\n",
379 gd->arch.arbiter_event_address);
Nick Spence56fd3c22008-08-28 14:09:19 -0700380 printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
381 printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
382 printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
383 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
384 printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
385
Simon Glass387a1f22012-12-13 20:48:57 +0000386 return gd->arch.arbiter_event_address;
Nick Spence56fd3c22008-08-28 14:09:19 -0700387}
388
389#elif defined(CONFIG_DISPLAY_AER_BRIEF)
390
391static int print_83xx_arb_event(int force)
392{
Simon Glass387a1f22012-12-13 20:48:57 +0000393 if (!force && !gd->arch.arbiter_event_address)
Nick Spence56fd3c22008-08-28 14:09:19 -0700394 return 0;
395
396 printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
Simon Glass387a1f22012-12-13 20:48:57 +0000397 gd->arch.arbiter_event_attributes,
398 gd->arch.arbiter_event_address);
Nick Spence56fd3c22008-08-28 14:09:19 -0700399
Simon Glass387a1f22012-12-13 20:48:57 +0000400 return gd->arch.arbiter_event_address;
Nick Spence56fd3c22008-08-28 14:09:19 -0700401}
402#endif /* CONFIG_DISPLAY_AER_xxxx */
403
Mario Six28fbefa2018-08-06 10:23:45 +0200404#ifndef CONFIG_CPU_MPC83XX
Dave Liuebd35f82007-06-25 10:41:56 +0800405/*
406 * Figure out the cause of the reset
407 */
408int prt_83xx_rsr(void)
409{
410 static struct {
411 ulong mask;
412 char *desc;
413 } bits[] = {
414 {
415 RSR_SWSR, "Software Soft"}, {
416 RSR_SWHR, "Software Hard"}, {
417 RSR_JSRS, "JTAG Soft"}, {
418 RSR_CSHR, "Check Stop"}, {
419 RSR_SWRS, "Software Watchdog"}, {
420 RSR_BMRS, "Bus Monitor"}, {
421 RSR_SRS, "External/Internal Soft"}, {
422 RSR_HRS, "External/Internal Hard"}
423 };
Robert P. J. Day0c911592016-05-23 06:49:21 -0400424 static int n = ARRAY_SIZE(bits);
Simon Glass4d6eaa32012-12-13 20:48:56 +0000425 ulong rsr = gd->arch.reset_status;
Dave Liuebd35f82007-06-25 10:41:56 +0800426 int i;
427 char *sep;
428
429 puts("Reset Status:");
430
431 sep = " ";
432 for (i = 0; i < n; i++)
433 if (rsr & bits[i].mask) {
434 printf("%s%s", sep, bits[i].desc);
435 sep = ", ";
436 }
Nick Spence56fd3c22008-08-28 14:09:19 -0700437 puts("\n");
438
439#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
440 print_83xx_arb_event(rsr & RSR_BMRS);
441#endif
442 puts("\n");
443
Dave Liuebd35f82007-06-25 10:41:56 +0800444 return 0;
445}
Mario Six28fbefa2018-08-06 10:23:45 +0200446#endif