Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2002 |
Albert ARIBAUD | 60fbc8d | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 4 | * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
wdenk | ef5fe75 | 2003-03-12 10:41:04 +0000 | [diff] [blame] | 7 | #ifndef _U_BOOT_I386_H_ |
| 8 | #define _U_BOOT_I386_H_ 1 |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 9 | |
Simon Glass | 162b09c | 2017-05-17 08:22:56 -0600 | [diff] [blame] | 10 | struct global_data; |
| 11 | |
Bin Meng | a3c9fb0 | 2015-06-07 11:33:13 +0800 | [diff] [blame] | 12 | extern char gdt_rom[]; |
| 13 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 14 | /* cpu/.../cpu.c */ |
Simon Glass | 19a8b12 | 2014-11-06 13:20:06 -0700 | [diff] [blame] | 15 | int arch_cpu_init(void); |
Simon Glass | 05e12f7 | 2019-04-25 21:58:42 -0600 | [diff] [blame] | 16 | |
| 17 | /** |
| 18 | * x86_cpu_init_f() - Set up basic features of the x86 CPU |
| 19 | * |
| 20 | * 0 on success, -ve on error |
| 21 | */ |
Graeme Russ | 121931c | 2011-02-12 15:11:35 +1100 | [diff] [blame] | 22 | int x86_cpu_init_f(void); |
Simon Glass | 05e12f7 | 2019-04-25 21:58:42 -0600 | [diff] [blame] | 23 | |
| 24 | /** |
| 25 | * x86_cpu_reinit_f() - Set up the CPU a second time |
| 26 | * |
| 27 | * Once cpu_init_f() has been called (e.g. in SPL) we should not call it |
| 28 | * again (e.g. in U-Boot proper) since it sets up the state from scratch. |
| 29 | * Call this function in later phases of U-Boot instead. It reads the CPU |
| 30 | * identify so that CPU functions can be used correctly, but does not change |
| 31 | * anything. |
| 32 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 33 | * Return: 0 (indicating success, to mimic cpu_init_f()) |
Simon Glass | 05e12f7 | 2019-04-25 21:58:42 -0600 | [diff] [blame] | 34 | */ |
| 35 | int x86_cpu_reinit_f(void); |
| 36 | |
Simon Glass | dc44467 | 2019-10-20 21:37:54 -0600 | [diff] [blame] | 37 | /** |
| 38 | * x86_cpu_init_tpl() - Do the minimum possible CPU init |
| 39 | * |
| 40 | * This just sets up the CPU features and figured out the identity |
| 41 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 42 | * Return: 0 (indicating success, to mimic cpu_init_f()) |
Simon Glass | dc44467 | 2019-10-20 21:37:54 -0600 | [diff] [blame] | 43 | */ |
| 44 | int x86_cpu_init_tpl(void); |
| 45 | |
Simon Glass | c5c4ed6 | 2020-07-02 21:12:12 -0600 | [diff] [blame] | 46 | /** |
| 47 | * cpu_reinit_fpu() - Reinit the FPU if something is wrong with it |
| 48 | * |
| 49 | * The FSP-M code can leave registers in use in the FPU. This functions reinits |
| 50 | * it so that the FPU can be used safely |
| 51 | */ |
| 52 | void cpu_reinit_fpu(void); |
| 53 | |
Graeme Russ | 078395c | 2009-11-24 20:04:21 +1100 | [diff] [blame] | 54 | int cpu_init_f(void); |
Simon Glass | 162b09c | 2017-05-17 08:22:56 -0600 | [diff] [blame] | 55 | void setup_gdt(struct global_data *id, u64 *gdt_addr); |
Bin Meng | a3c9fb0 | 2015-06-07 11:33:13 +0800 | [diff] [blame] | 56 | /* |
| 57 | * Setup FSP execution environment GDT to use the one we used in |
| 58 | * arch/x86/cpu/start16.S and reload the segment registers. |
| 59 | */ |
| 60 | void setup_fsp_gdt(void); |
Graeme Russ | 6e25600 | 2011-12-27 22:46:43 +1100 | [diff] [blame] | 61 | int init_cache(void); |
Gabe Black | 846d08e | 2012-10-20 12:33:10 +0000 | [diff] [blame] | 62 | int cleanup_before_linux(void); |
Graeme Russ | 7679d1f | 2009-02-24 21:14:45 +1100 | [diff] [blame] | 63 | |
| 64 | /* cpu/.../timer.c */ |
| 65 | void timer_isr(void *); |
| 66 | typedef void (timer_fnc_t) (void); |
| 67 | int register_timer_isr (timer_fnc_t *isr_func); |
Simon Glass | 11d7a5b | 2013-04-17 16:13:36 +0000 | [diff] [blame] | 68 | unsigned long get_tbclk_mhz(void); |
| 69 | void timer_set_base(uint64_t base); |
Bin Meng | b29a08c | 2015-10-22 19:13:30 -0700 | [diff] [blame] | 70 | int i8254_init(void); |
Graeme Russ | 7679d1f | 2009-02-24 21:14:45 +1100 | [diff] [blame] | 71 | |
Graeme Russ | 77290ee | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 72 | /* cpu/.../interrupts.c */ |
| 73 | int cpu_init_interrupts(void); |
| 74 | |
Simon Glass | 8337433 | 2014-11-06 13:20:08 -0700 | [diff] [blame] | 75 | int cleanup_before_linux(void); |
| 76 | int x86_cleanup_before_linux(void); |
| 77 | void x86_enable_caches(void); |
| 78 | void x86_disable_caches(void); |
| 79 | int x86_init_cache(void); |
Simon Glass | 8337433 | 2014-11-06 13:20:08 -0700 | [diff] [blame] | 80 | ulong board_get_usable_ram_top(ulong total_size); |
Simon Glass | 543bb14 | 2014-11-10 18:00:26 -0700 | [diff] [blame] | 81 | int default_print_cpuinfo(void); |
Simon Glass | 8337433 | 2014-11-06 13:20:08 -0700 | [diff] [blame] | 82 | |
Simon Glass | 4661c2c | 2015-01-27 22:13:42 -0700 | [diff] [blame] | 83 | /* Set up a UART which can be used with printch(), printhex8(), etc. */ |
Stefan Roese | a377b7c | 2016-01-19 14:24:12 +0100 | [diff] [blame] | 84 | int setup_internal_uart(int enable); |
Simon Glass | 4661c2c | 2015-01-27 22:13:42 -0700 | [diff] [blame] | 85 | |
wdenk | abda5ca | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 86 | void isa_unmap_rom(u32 addr); |
| 87 | u32 isa_map_rom(u32 bus_addr, int size); |
| 88 | |
Graeme Russ | cbfce1d | 2011-04-13 19:43:28 +1000 | [diff] [blame] | 89 | /* arch/x86/lib/... */ |
wdenk | abda5ca | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 90 | int video_bios_init(void); |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 91 | |
Simon Glass | 6c34fc1 | 2019-09-25 08:00:11 -0600 | [diff] [blame] | 92 | /* arch/x86/lib/fsp1,2/... */ |
Bin Meng | cf20030 | 2017-04-21 07:24:39 -0700 | [diff] [blame] | 93 | |
| 94 | /** |
| 95 | * fsp_save_s3_stack() - save stack address to CMOS for next S3 boot |
| 96 | * |
| 97 | * At the end of pre-relocation phase, save the new stack address |
| 98 | * to CMOS and use it as the stack on next S3 boot for fsp_init() |
| 99 | * continuation function. |
| 100 | * |
| 101 | * @return: 0 if OK, -ve on error |
| 102 | */ |
| 103 | int fsp_save_s3_stack(void); |
| 104 | |
Graeme Russ | d7755b4 | 2012-01-01 15:06:39 +1100 | [diff] [blame] | 105 | void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); |
| 106 | void board_init_f_r(void) __attribute__ ((noreturn)); |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 107 | |
Bin Meng | 1530536 | 2015-04-24 18:10:06 +0800 | [diff] [blame] | 108 | int arch_misc_init(void); |
| 109 | |
Vadim Bendebury | 1d82bac | 2012-10-23 18:04:32 +0000 | [diff] [blame] | 110 | /* Read the time stamp counter */ |
Simon Glass | 42081ce | 2013-06-11 11:14:52 -0700 | [diff] [blame] | 111 | static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void) |
Vadim Bendebury | 1d82bac | 2012-10-23 18:04:32 +0000 | [diff] [blame] | 112 | { |
| 113 | uint32_t high, low; |
| 114 | __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)); |
| 115 | return (((uint64_t)high) << 32) | low; |
| 116 | } |
| 117 | |
| 118 | /* board/... */ |
| 119 | void timer_set_tsc_base(uint64_t new_base); |
| 120 | uint64_t timer_get_tsc(void); |
| 121 | |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 122 | void quick_ram_check(void); |
| 123 | |
Simon Glass | 1b6b9b9 | 2014-12-29 19:32:24 -0700 | [diff] [blame] | 124 | #define PCI_VGA_RAM_IMAGE_START 0xc0000 |
| 125 | |
wdenk | ef5fe75 | 2003-03-12 10:41:04 +0000 | [diff] [blame] | 126 | #endif /* _U_BOOT_I386_H_ */ |