blob: 5d7dff534d7e9a65f473a799542201d5a171fbcb [file] [log] [blame]
wdenk591dda52002-11-18 00:14:45 +00001/*
2 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +02003 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
wdenk591dda52002-11-18 00:14:45 +00004 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk591dda52002-11-18 00:14:45 +00006 */
7
wdenkef5fe752003-03-12 10:41:04 +00008#ifndef _U_BOOT_I386_H_
9#define _U_BOOT_I386_H_ 1
wdenk591dda52002-11-18 00:14:45 +000010
wdenk591dda52002-11-18 00:14:45 +000011/* cpu/.../cpu.c */
Simon Glass19a8b122014-11-06 13:20:06 -070012int arch_cpu_init(void);
Graeme Russ121931c2011-02-12 15:11:35 +110013int x86_cpu_init_f(void);
Graeme Russ078395c2009-11-24 20:04:21 +110014int cpu_init_f(void);
Graeme Russ35368962011-12-31 22:58:15 +110015void init_gd(gd_t *id, u64 *gdt_addr);
16void setup_gdt(gd_t *id, u64 *gdt_addr);
Graeme Russ6e256002011-12-27 22:46:43 +110017int init_cache(void);
Gabe Black846d08e2012-10-20 12:33:10 +000018int cleanup_before_linux(void);
Simon Glassace6cd82013-04-17 16:13:34 +000019void panic_puts(const char *str);
Graeme Russ7679d1f2009-02-24 21:14:45 +110020
21/* cpu/.../timer.c */
22void timer_isr(void *);
23typedef void (timer_fnc_t) (void);
24int register_timer_isr (timer_fnc_t *isr_func);
Simon Glass11d7a5b2013-04-17 16:13:36 +000025unsigned long get_tbclk_mhz(void);
26void timer_set_base(uint64_t base);
Simon Glass3e8b6052013-04-17 16:13:39 +000027int pcat_timer_init(void);
Graeme Russ7679d1f2009-02-24 21:14:45 +110028
Simon Glass8aa78732014-11-06 13:20:05 -070029/* Architecture specific DRAM init */
30int dram_init(void);
wdenk591dda52002-11-18 00:14:45 +000031
Graeme Russ77290ee2009-02-24 21:13:40 +110032/* cpu/.../interrupts.c */
33int cpu_init_interrupts(void);
34
wdenk591dda52002-11-18 00:14:45 +000035/* board/.../... */
wdenkabda5ca2003-05-31 18:35:21 +000036int dram_init(void);
37
Simon Glass83374332014-11-06 13:20:08 -070038int cleanup_before_linux(void);
39int x86_cleanup_before_linux(void);
40void x86_enable_caches(void);
41void x86_disable_caches(void);
42int x86_init_cache(void);
43void reset_cpu(ulong addr);
44ulong board_get_usable_ram_top(ulong total_size);
45void dram_init_banksize(void);
Simon Glass543bb142014-11-10 18:00:26 -070046int default_print_cpuinfo(void);
Simon Glass83374332014-11-06 13:20:08 -070047
Simon Glass4661c2c2015-01-27 22:13:42 -070048/* Set up a UART which can be used with printch(), printhex8(), etc. */
49int setup_early_uart(void);
50
Graeme Russa8d06b42010-04-24 00:05:48 +100051void setup_pcat_compatibility(void);
52
wdenkabda5ca2003-05-31 18:35:21 +000053void isa_unmap_rom(u32 addr);
54u32 isa_map_rom(u32 bus_addr, int size);
55
Graeme Russcbfce1d2011-04-13 19:43:28 +100056/* arch/x86/lib/... */
wdenkabda5ca2003-05-31 18:35:21 +000057int video_bios_init(void);
wdenk591dda52002-11-18 00:14:45 +000058
Graeme Russd7755b42012-01-01 15:06:39 +110059void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
60void board_init_f_r(void) __attribute__ ((noreturn));
wdenk591dda52002-11-18 00:14:45 +000061
Vadim Bendebury1d82bac2012-10-23 18:04:32 +000062/* Read the time stamp counter */
Simon Glass42081ce2013-06-11 11:14:52 -070063static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
Vadim Bendebury1d82bac2012-10-23 18:04:32 +000064{
65 uint32_t high, low;
66 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high));
67 return (((uint64_t)high) << 32) | low;
68}
69
70/* board/... */
71void timer_set_tsc_base(uint64_t new_base);
72uint64_t timer_get_tsc(void);
73
Simon Glass268eefd2014-11-12 22:42:28 -070074void quick_ram_check(void);
75
Simon Glass1b6b9b92014-12-29 19:32:24 -070076#define PCI_VGA_RAM_IMAGE_START 0xc0000
77
wdenkef5fe752003-03-12 10:41:04 +000078#endif /* _U_BOOT_I386_H_ */