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York Sun7b08d212014-06-23 15:15:56 -07001/*
Priyanka Jain7d05b992017-04-28 10:41:35 +05302 * Copyright 2017 NXP
York Sun7b08d212014-06-23 15:15:56 -07003 * Copyright (C) 2014 Freescale Semiconductor
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __LS2_COMMON_H
9#define __LS2_COMMON_H
10
York Sun7b08d212014-06-23 15:15:56 -070011#define CONFIG_REMAKE_ELF
Mingkai Hu0e58b512015-10-26 19:47:50 +080012#define CONFIG_FSL_LAYERSCAPE
Mingkai Hu0e58b512015-10-26 19:47:50 +080013#define CONFIG_MP
York Sun7b08d212014-06-23 15:15:56 -070014#define CONFIG_GICV3
Bhupesh Sharmaa0c00ff2015-01-06 13:11:21 -080015#define CONFIG_FSL_TZPC_BP147
York Sun7b08d212014-06-23 15:15:56 -070016
Bharat Bhushan70239992017-03-22 12:06:25 +053017#include <asm/arch/stream_id_lsch3.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080018#include <asm/arch/config.h>
Minghuan Lian0e3a2b92015-03-20 19:28:16 -070019
Mingkai Hu0e58b512015-10-26 19:47:50 +080020/* Link Definitions */
21#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
22
Bhupesh Sharma25b8efe2015-03-19 09:20:43 -070023/* We need architecture specific misc initializations */
Bhupesh Sharma25b8efe2015-03-19 09:20:43 -070024
York Sun7b08d212014-06-23 15:15:56 -070025/* Link Definitions */
Yuan Yao331c87c2016-06-08 18:25:00 +080026#ifndef CONFIG_QSPI_BOOT
Priyanka Jain7d05b992017-04-28 10:41:35 +053027#else
Priyanka Jain7d05b992017-04-28 10:41:35 +053028#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
29#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
Santan Kumar58bccd22017-08-09 10:35:45 +053030#define CONFIG_ENV_SECT_SIZE 0x40000
Yuan Yao331c87c2016-06-08 18:25:00 +080031#endif
York Sun7b08d212014-06-23 15:15:56 -070032
York Sun7b08d212014-06-23 15:15:56 -070033#define CONFIG_SKIP_LOWLEVEL_INIT
York Sun7b08d212014-06-23 15:15:56 -070034
Scott Wood8e728cd2015-03-24 13:25:02 -070035#ifndef CONFIG_SPL
York Sun7b08d212014-06-23 15:15:56 -070036#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
Scott Wood8e728cd2015-03-24 13:25:02 -070037#endif
York Sun7b08d212014-06-23 15:15:56 -070038#ifndef CONFIG_SYS_FSL_DDR4
York Sun7b08d212014-06-23 15:15:56 -070039#define CONFIG_SYS_DDR_RAW_TIMING
40#endif
York Sun7b08d212014-06-23 15:15:56 -070041
42#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
43
Mingkai Hu0e58b512015-10-26 19:47:50 +080044#define CONFIG_VERY_BIG_RAM
York Sun7b08d212014-06-23 15:15:56 -070045#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
46#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
48#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
York Sunc7a0e302014-08-13 10:21:05 -070049#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
50
York Sun290a83a2014-09-08 12:20:01 -070051/*
52 * SMP Definitinos
53 */
54#define CPU_RELEASE_ADDR secondary_boot_func
55
York Sunc7a0e302014-08-13 10:21:05 -070056#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053057#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sunc7a0e302014-08-13 10:21:05 -070058#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
59/*
60 * DDR controller use 0 as the base address for binding.
61 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
62 */
63#define CONFIG_SYS_DP_DDR_BASE_PHY 0
64#define CONFIG_DP_DDR_CTRL 2
65#define CONFIG_DP_DDR_NUM_CTRLS 1
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053066#endif
York Sun7b08d212014-06-23 15:15:56 -070067
68/* Generic Timer Definitions */
York Sun77a10972015-03-20 19:28:08 -070069/*
70 * This is not an accurate number. It is used in start.S. The frequency
71 * will be udpated later when get_bus_freq(0) is available.
72 */
73#define COUNTER_FREQUENCY 25000000 /* 25MHz */
York Sun7b08d212014-06-23 15:15:56 -070074
75/* Size of malloc() pool */
Prabhakar Kushwahae0665b12015-03-19 09:20:47 -070076#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
York Sun7b08d212014-06-23 15:15:56 -070077
78/* I2C */
York Sun7b08d212014-06-23 15:15:56 -070079#define CONFIG_SYS_I2C
80#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +020081#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
82#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf1a52162015-03-20 10:20:40 -070083#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
84#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
York Sun7b08d212014-06-23 15:15:56 -070085
86/* Serial Port */
York Sun03017032015-03-20 19:28:23 -070087#define CONFIG_CONS_INDEX 1
York Sun7b08d212014-06-23 15:15:56 -070088#define CONFIG_SYS_NS16550_SERIAL
89#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang3a76dd52017-01-10 16:44:16 +080090#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
York Sun7b08d212014-06-23 15:15:56 -070091
York Sun7b08d212014-06-23 15:15:56 -070092#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
93
94/* IFC */
95#define CONFIG_FSL_IFC
Prabhakar Kushwaha23931692015-03-20 19:28:06 -070096
York Sun7b08d212014-06-23 15:15:56 -070097/*
York Sun03017032015-03-20 19:28:23 -070098 * During booting, IFC is mapped at the region of 0x30000000.
99 * But this region is limited to 256MB. To accommodate NOR, promjet
100 * and FPGA. This region is divided as below:
101 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
102 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
103 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
104 *
105 * To accommodate bigger NOR flash and other devices, we will map IFC
106 * chip selects to as below:
107 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
108 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
109 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
110 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
111 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
112 *
113 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
York Sun7b08d212014-06-23 15:15:56 -0700114 * CONFIG_SYS_FLASH_BASE has the final address (core view)
115 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
116 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
117 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
118 */
York Sun03017032015-03-20 19:28:23 -0700119
York Sun7b08d212014-06-23 15:15:56 -0700120#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
121#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
122#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
123
York Sun03017032015-03-20 19:28:23 -0700124#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
125#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
126
York Sun03017032015-03-20 19:28:23 -0700127#ifndef __ASSEMBLY__
128unsigned long long get_qixis_addr(void);
129#endif
130#define QIXIS_BASE get_qixis_addr()
131#define QIXIS_BASE_PHYS 0x20000000
132#define QIXIS_BASE_PHYS_EARLY 0xC000000
Yangbo Lud0e295d2015-03-20 19:28:31 -0700133#define QIXIS_STAT_PRES1 0xb
134#define QIXIS_SDID_MASK 0x07
135#define QIXIS_ESDHC_NO_ADAPTER 0x7
York Sun03017032015-03-20 19:28:23 -0700136
137#define CONFIG_SYS_NAND_BASE 0x530000000ULL
138#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
Prabhakar Kushwaha962b2de2014-07-16 09:21:12 +0530139
York Sun7b08d212014-06-23 15:15:56 -0700140/* MC firmware */
York Sun7b08d212014-06-23 15:15:56 -0700141/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
J. German Riveraf4fed4b2015-03-20 19:28:18 -0700142#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
143#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
144#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
145#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
York Suncbe8e1c2016-04-04 11:41:26 -0700146/* For LS2085A */
J. German Riverac3b505f2015-07-02 11:28:58 +0530147#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
148#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
York Sun7b08d212014-06-23 15:15:56 -0700149
Bogdan Purcareata08bc0142017-05-24 16:40:21 +0000150/* Define phy_reset function to boot the MC based on mcinitcmd.
151 * This happens late enough to properly fixup u-boot env MAC addresses.
152 */
153#define CONFIG_RESET_PHY_R
154
Prabhakar Kushwaha853a9012015-06-02 10:55:52 +0530155/*
156 * Carve out a DDR region which will not be used by u-boot/Linux
157 *
158 * It will be used by MC and Debug Server. The MC region must be
159 * 512MB aligned, so the min size to hide is 512MB.
160 */
York Sune45e13e2016-08-03 12:33:00 -0700161#ifdef CONFIG_FSL_MC_ENET
Pratiyush Mohan Srivastavaaf150f62015-12-22 16:49:34 +0530162#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
York Sun7b08d212014-06-23 15:15:56 -0700163#endif
164
165/* Command line configuration */
York Sun7b08d212014-06-23 15:15:56 -0700166
167/* Miscellaneous configurable options */
168#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
169
170/* Physical Memory Map */
171/* fixme: these need to be checked against the board */
172#define CONFIG_CHIP_SELECTS_PER_CTRL 4
York Sun7b08d212014-06-23 15:15:56 -0700173
York Sunc7a0e302014-08-13 10:21:05 -0700174#define CONFIG_NR_DRAM_BANKS 3
York Sun7b08d212014-06-23 15:15:56 -0700175
York Sun7b08d212014-06-23 15:15:56 -0700176#define CONFIG_HWCONFIG
177#define HWCONFIG_BUFFER_SIZE 128
178
Alison Wang36427502015-11-13 16:49:06 +0800179/* Allow to overwrite serial and ethaddr */
180#define CONFIG_ENV_OVERWRITE
181
York Sun7b08d212014-06-23 15:15:56 -0700182/* Initial environment variables */
183#define CONFIG_EXTRA_ENV_SETTINGS \
184 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
185 "loadaddr=0x80100000\0" \
186 "kernel_addr=0x100000\0" \
187 "ramdisk_addr=0x800000\0" \
188 "ramdisk_size=0x2000000\0" \
Prabhakar Kushwaha23931692015-03-20 19:28:06 -0700189 "fdt_high=0xa0000000\0" \
York Sun7b08d212014-06-23 15:15:56 -0700190 "initrd_high=0xffffffffffffffff\0" \
Santan Kumar0f0173d2017-04-28 12:47:24 +0530191 "kernel_start=0x581000000\0" \
Stuart Yoderd4792d82015-01-06 13:18:57 -0800192 "kernel_load=0xa0000000\0" \
Prabhakar Kushwaha2c0a13d2015-07-01 16:28:22 +0530193 "kernel_size=0x2800000\0" \
Prabhakar Kushwahaae193f92016-02-03 17:03:51 +0530194 "console=ttyAMA0,38400n8\0" \
Santan Kumar0f0173d2017-04-28 12:47:24 +0530195 "mcinitcmd=fsl_mc start mc 0x580a00000" \
196 " 0x580e00000 \0"
York Sun7b08d212014-06-23 15:15:56 -0700197
Santan Kumar1afa9002017-05-05 15:42:29 +0530198#ifdef CONFIG_SD_BOOT
199#define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
200 " fsl_mc apply dpl 0x80200000 &&" \
201 " mmc read $kernel_load $kernel_start" \
202 " $kernel_size && bootm $kernel_load"
203#else
Santan Kumar0f0173d2017-04-28 12:47:24 +0530204#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
Prabhakar Kushwahad78fa5e2016-02-03 17:04:07 +0530205 " cp.b $kernel_start $kernel_load" \
206 " $kernel_size && bootm $kernel_load"
Santan Kumar1afa9002017-05-05 15:42:29 +0530207#endif
York Sun7b08d212014-06-23 15:15:56 -0700208
York Sun7b08d212014-06-23 15:15:56 -0700209/* Monitor Command Prompt */
210#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
York Sun7b08d212014-06-23 15:15:56 -0700211#define CONFIG_SYS_MAXARGS 64 /* max command args */
212
Scott Wood8e728cd2015-03-24 13:25:02 -0700213#define CONFIG_SPL_BSS_START_ADDR 0x80100000
214#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
Scott Wood8e728cd2015-03-24 13:25:02 -0700215#define CONFIG_SPL_MAX_SIZE 0x16000
Scott Wood8e728cd2015-03-24 13:25:02 -0700216#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
217#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
218#define CONFIG_SPL_TEXT_BASE 0x1800a000
219
Santan Kumar99136482017-05-05 15:42:28 +0530220#ifdef CONFIG_NAND_BOOT
Scott Wood8e728cd2015-03-24 13:25:02 -0700221#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
222#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
Santan Kumar99136482017-05-05 15:42:28 +0530223#endif
Scott Wood8e728cd2015-03-24 13:25:02 -0700224#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
225#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
York Sunfb383062017-12-18 08:24:55 -0800226#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
Scott Wood8e728cd2015-03-24 13:25:02 -0700227
Bhupesh Sharma37fbf612015-05-28 14:54:02 +0530228#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
229
Simon Glass89e0a3a2017-05-17 08:23:10 -0600230#include <asm/arch/soc.h>
231
York Sun7b08d212014-06-23 15:15:56 -0700232#endif /* __LS2_COMMON_H */