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Dave Liu19b247e2008-01-11 18:48:24 +08001/*
Scott Wood3f53f1a2010-08-30 18:04:52 -05002 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
Dave Liu19b247e2008-01-11 18:48:24 +08003 *
4 * Dave Liu <daveliu@freescale.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Dave Liu19b247e2008-01-11 18:48:24 +08007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Scott Woodf60c06e2010-11-24 13:28:40 +000012#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
13#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
14#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
15#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
16#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
17
Scott Woodf60c06e2010-11-24 13:28:40 +000018#ifndef CONFIG_SYS_MONITOR_BASE
19#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
20#endif
21
Dave Liu19b247e2008-01-11 18:48:24 +080022/*
23 * High Level Configuration Options
24 */
25#define CONFIG_E300 1 /* E300 family */
Peter Tyser72f2d392009-05-22 17:23:25 -050026#define CONFIG_MPC831x 1 /* MPC831x CPU family */
Dave Liu19b247e2008-01-11 18:48:24 +080027#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
28#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
29
30/*
31 * System Clock Setup
32 */
33#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
34#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
35
36/*
37 * Hardware Reset Configuration Word
38 * if CLKIN is 66.66MHz, then
39 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
40 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041#define CONFIG_SYS_HRCW_LOW (\
Dave Liu19b247e2008-01-11 18:48:24 +080042 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
43 HRCWL_DDR_TO_SCB_CLK_2X1 |\
44 HRCWL_SVCOD_DIV_2 |\
45 HRCWL_CSB_TO_CLKIN_2X1 |\
46 HRCWL_CORE_TO_CSB_3X1)
Anton Vorontsovec821752009-11-24 20:12:12 +030047#define CONFIG_SYS_HRCW_HIGH_BASE (\
Dave Liu19b247e2008-01-11 18:48:24 +080048 HRCWH_PCI_HOST |\
49 HRCWH_PCI1_ARBITER_ENABLE |\
50 HRCWH_CORE_ENABLE |\
Dave Liu19b247e2008-01-11 18:48:24 +080051 HRCWH_BOOTSEQ_DISABLE |\
52 HRCWH_SW_WATCHDOG_DISABLE |\
Dave Liu19b247e2008-01-11 18:48:24 +080053 HRCWH_TSEC1M_IN_RGMII |\
54 HRCWH_TSEC2M_IN_RGMII |\
55 HRCWH_BIG_ENDIAN |\
56 HRCWH_LALE_NORMAL)
57
Anton Vorontsovec821752009-11-24 20:12:12 +030058#ifdef CONFIG_NAND_SPL
59#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
60 HRCWH_FROM_0XFFF00100 |\
61 HRCWH_ROM_LOC_NAND_SP_8BIT |\
62 HRCWH_RL_EXT_NAND)
63#else
64#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
65 HRCWH_FROM_0X00000100 |\
66 HRCWH_ROM_LOC_LOCAL_16BIT |\
67 HRCWH_RL_EXT_LEGACY)
68#endif
69
Dave Liu19b247e2008-01-11 18:48:24 +080070/*
71 * System IO Config
72 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#define CONFIG_SYS_SICRH 0x00000000
74#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
Dave Liu19b247e2008-01-11 18:48:24 +080075
Anton Vorontsovd398b7e2009-06-10 00:25:36 +040076#define CONFIG_HWCONFIG
Dave Liu19b247e2008-01-11 18:48:24 +080077
78/*
79 * IMMR new address
80 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu19b247e2008-01-11 18:48:24 +080082
83/*
84 * Arbiter Setup
85 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
Joe Hershberger496f7722011-10-11 23:57:11 -050087#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
88#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
Dave Liu19b247e2008-01-11 18:48:24 +080089
90/*
91 * DDR Setup
92 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
94#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
95#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
96#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Joe Hershberger496f7722011-10-11 23:57:11 -050097#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
Dave Liu19b247e2008-01-11 18:48:24 +080098 | DDRCDR_PZ_LOZ \
99 | DDRCDR_NZ_LOZ \
100 | DDRCDR_ODT \
Joe Hershberger496f7722011-10-11 23:57:11 -0500101 | DDRCDR_Q_DRN)
Dave Liu19b247e2008-01-11 18:48:24 +0800102 /* 0x7b880001 */
103/*
104 * Manually set up DDR parameters
105 * consist of two chips HY5PS12621BFP-C4 from HYNIX
106 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107#define CONFIG_SYS_DDR_SIZE 128 /* MB */
108#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
Joe Hershberger496f7722011-10-11 23:57:11 -0500109#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershbergercc03b802011-10-11 23:57:29 -0500110 | CSCONFIG_ODT_RD_NEVER \
111 | CSCONFIG_ODT_WR_ONLY_CURRENT \
Joe Hershberger496f7722011-10-11 23:57:11 -0500112 | CSCONFIG_ROW_BIT_13 \
113 | CSCONFIG_COL_BIT_10)
Dave Liu19b247e2008-01-11 18:48:24 +0800114 /* 0x80010102 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200115#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger496f7722011-10-11 23:57:11 -0500116#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
117 | (0 << TIMING_CFG0_WRT_SHIFT) \
118 | (0 << TIMING_CFG0_RRT_SHIFT) \
119 | (0 << TIMING_CFG0_WWT_SHIFT) \
120 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
121 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
122 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
123 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Dave Liu19b247e2008-01-11 18:48:24 +0800124 /* 0x00220802 */
Joe Hershberger496f7722011-10-11 23:57:11 -0500125#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
126 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
127 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
128 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
129 | (6 << TIMING_CFG1_REFREC_SHIFT) \
130 | (2 << TIMING_CFG1_WRREC_SHIFT) \
131 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
132 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Howard Gregoryf2d4bef2008-11-04 14:55:33 +0800133 /* 0x27256222 */
Joe Hershberger496f7722011-10-11 23:57:11 -0500134#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
135 | (4 << TIMING_CFG2_CPO_SHIFT) \
136 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
137 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
138 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
139 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
140 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
Howard Gregoryf2d4bef2008-11-04 14:55:33 +0800141 /* 0x121048c5 */
Joe Hershberger496f7722011-10-11 23:57:11 -0500142#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
143 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Dave Liu19b247e2008-01-11 18:48:24 +0800144 /* 0x03600100 */
Joe Hershberger496f7722011-10-11 23:57:11 -0500145#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Dave Liu19b247e2008-01-11 18:48:24 +0800146 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershbergercc03b802011-10-11 23:57:29 -0500147 | SDRAM_CFG_DBW_32)
Dave Liu19b247e2008-01-11 18:48:24 +0800148 /* 0x43080000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
Joe Hershberger496f7722011-10-11 23:57:11 -0500150#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
151 | (0x0232 << SDRAM_MODE_SD_SHIFT))
Dave Liu19b247e2008-01-11 18:48:24 +0800152 /* ODT 150ohm CL=3, AL=1 on SDRAM */
Joe Hershberger496f7722011-10-11 23:57:11 -0500153#define CONFIG_SYS_DDR_MODE2 0x00000000
Dave Liu19b247e2008-01-11 18:48:24 +0800154
155/*
156 * Memory test
157 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
159#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
160#define CONFIG_SYS_MEMTEST_END 0x00140000
Dave Liu19b247e2008-01-11 18:48:24 +0800161
162/*
163 * The reserved memory
164 */
Kevin Hao349a0152016-07-08 11:25:14 +0800165#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Joe Hershberger496f7722011-10-11 23:57:11 -0500166#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dave Liu19b247e2008-01-11 18:48:24 +0800167
168/*
169 * Initial RAM Base Address Setup
170 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200171#define CONFIG_SYS_INIT_RAM_LOCK 1
172#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200173#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger496f7722011-10-11 23:57:11 -0500174#define CONFIG_SYS_GBL_DATA_OFFSET \
175 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liu19b247e2008-01-11 18:48:24 +0800176
177/*
178 * Local Bus Configuration & Clock Setup
179 */
Kim Phillips328040a2009-09-25 18:19:44 -0500180#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
181#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_LBC_LBCR 0x00040000
Becky Brucedfe6e232010-06-17 11:37:18 -0500183#define CONFIG_FSL_ELBC 1
Dave Liu19b247e2008-01-11 18:48:24 +0800184
185/*
186 * FLASH on the Local Bus
187 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200188#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200189#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Dave Liu19b247e2008-01-11 18:48:24 +0800191
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
Joe Hershberger496f7722011-10-11 23:57:11 -0500193#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
194#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu19b247e2008-01-11 18:48:24 +0800195
Joe Hershberger496f7722011-10-11 23:57:11 -0500196 /* Window base at flash base */
197#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500198#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
Dave Liu19b247e2008-01-11 18:48:24 +0800199
Anton Vorontsovec821752009-11-24 20:12:12 +0300200#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500201 | BR_PS_16 /* 16 bit port */ \
202 | BR_MS_GPCM /* MSEL = GPCM */ \
203 | BR_V) /* valid */
204#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
205 | OR_UPM_XAM \
206 | OR_GPCM_CSNT \
207 | OR_GPCM_ACS_DIV2 \
208 | OR_GPCM_XACS \
209 | OR_GPCM_SCY_15 \
210 | OR_GPCM_TRLX_SET \
211 | OR_GPCM_EHTR_SET \
212 | OR_GPCM_EAD)
Dave Liu19b247e2008-01-11 18:48:24 +0800213
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
Joe Hershberger496f7722011-10-11 23:57:11 -0500215/* 127 64KB sectors and 8 8KB top sectors per device */
216#define CONFIG_SYS_MAX_FLASH_SECT 135
Dave Liu19b247e2008-01-11 18:48:24 +0800217
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#undef CONFIG_SYS_FLASH_CHECKSUM
219#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
220#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Dave Liu19b247e2008-01-11 18:48:24 +0800221
222/*
223 * NAND Flash on the Local Bus
224 */
Anton Vorontsovec821752009-11-24 20:12:12 +0300225
226#ifdef CONFIG_NAND_SPL
227#define CONFIG_SYS_NAND_BASE 0xFFF00000
228#else
229#define CONFIG_SYS_NAND_BASE 0xE0600000
230#endif
231
Scott Wood3f53f1a2010-08-30 18:04:52 -0500232#define CONFIG_MTD_DEVICE
233#define CONFIG_MTD_PARTITION
Scott Wood3f53f1a2010-08-30 18:04:52 -0500234
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200235#define CONFIG_SYS_MAX_NAND_DEVICE 1
Dave Liu5e6b5342008-11-04 14:55:06 +0800236#define CONFIG_NAND_FSL_ELBC 1
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500237#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
238#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
Dave Liu19b247e2008-01-11 18:48:24 +0800239
Anton Vorontsovec821752009-11-24 20:12:12 +0300240#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
241#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
242#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
243#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
244#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
245
246#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500247 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershberger496f7722011-10-11 23:57:11 -0500248 | BR_PS_8 /* 8 bit port */ \
Dave Liu19b247e2008-01-11 18:48:24 +0800249 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger496f7722011-10-11 23:57:11 -0500250 | BR_V) /* valid */
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500251#define CONFIG_SYS_NAND_OR_PRELIM \
252 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
Dave Liu19b247e2008-01-11 18:48:24 +0800253 | OR_FCM_CSCT \
254 | OR_FCM_CST \
255 | OR_FCM_CHT \
256 | OR_FCM_SCY_1 \
257 | OR_FCM_TRLX \
Joe Hershberger496f7722011-10-11 23:57:11 -0500258 | OR_FCM_EHTR)
Dave Liu19b247e2008-01-11 18:48:24 +0800259 /* 0xFFFF8396 */
260
Anton Vorontsovec821752009-11-24 20:12:12 +0300261#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
262#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
263#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
264#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
Anton Vorontsovec821752009-11-24 20:12:12 +0300265
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200266#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500267#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu19b247e2008-01-11 18:48:24 +0800268
Anton Vorontsovec821752009-11-24 20:12:12 +0300269#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
270#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
271
272#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
273 !defined(CONFIG_NAND_SPL)
274#define CONFIG_SYS_RAMBOOT
275#else
276#undef CONFIG_SYS_RAMBOOT
277#endif
278
Dave Liu19b247e2008-01-11 18:48:24 +0800279/*
280 * Serial Port
281 */
282#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200283#define CONFIG_SYS_NS16550_SERIAL
284#define CONFIG_SYS_NS16550_REG_SIZE 1
Anton Vorontsovec821752009-11-24 20:12:12 +0300285#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
Dave Liu19b247e2008-01-11 18:48:24 +0800286
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200287#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger496f7722011-10-11 23:57:11 -0500288 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
Dave Liu19b247e2008-01-11 18:48:24 +0800289
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200290#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
291#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu19b247e2008-01-11 18:48:24 +0800292
Dave Liu19b247e2008-01-11 18:48:24 +0800293/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200294#define CONFIG_SYS_I2C
295#define CONFIG_SYS_I2C_FSL
296#define CONFIG_SYS_FSL_I2C_SPEED 400000
297#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
298#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
299#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Dave Liu19b247e2008-01-11 18:48:24 +0800300
301/*
302 * Board info - revision and where boot from
303 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200304#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
Dave Liu19b247e2008-01-11 18:48:24 +0800305
306/*
307 * Config on-board RTC
308 */
309#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200310#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu19b247e2008-01-11 18:48:24 +0800311
312/*
313 * General PCI
314 * Addresses are mapped 1-1.
315 */
Joe Hershberger496f7722011-10-11 23:57:11 -0500316#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
317#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
318#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200319#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
320#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
321#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
322#define CONFIG_SYS_PCI_IO_BASE 0x00000000
323#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
324#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liu19b247e2008-01-11 18:48:24 +0800325
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200326#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
327#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
328#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu19b247e2008-01-11 18:48:24 +0800329
Anton Vorontsov0db0be22009-01-08 04:26:17 +0300330#define CONFIG_SYS_PCIE1_BASE 0xA0000000
331#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
332#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
333#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
334#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
335#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
336#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
337#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
338#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
339
340#define CONFIG_SYS_PCIE2_BASE 0xC0000000
341#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
342#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
343#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
344#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
345#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
346#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
347#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
348#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
349
Gabor Juhosb4458732013-05-30 07:06:12 +0000350#define CONFIG_PCI_INDIRECT_BRIDGE
Kim Phillipsf1384292009-07-23 14:09:38 -0500351#define CONFIG_PCIE
Dave Liu19b247e2008-01-11 18:48:24 +0800352
Dave Liu19b247e2008-01-11 18:48:24 +0800353#define CONFIG_EEPRO100
354#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200355#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu19b247e2008-01-11 18:48:24 +0800356
Anton Vorontsov13c16a12008-07-08 21:00:04 +0400357#define CONFIG_HAS_FSL_DR_USB
Vivek Mahajanb8431f62009-05-25 17:23:17 +0530358#define CONFIG_SYS_SCCR_USBDRCM 3
359
Vivek Mahajanb8431f62009-05-25 17:23:17 +0530360#define CONFIG_USB_EHCI_FSL
Joe Hershberger496f7722011-10-11 23:57:11 -0500361#define CONFIG_USB_PHY_TYPE "utmi"
Vivek Mahajanb8431f62009-05-25 17:23:17 +0530362#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov13c16a12008-07-08 21:00:04 +0400363
Dave Liu19b247e2008-01-11 18:48:24 +0800364/*
365 * TSEC
366 */
367#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200368#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger496f7722011-10-11 23:57:11 -0500369#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200370#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger496f7722011-10-11 23:57:11 -0500371#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Dave Liu19b247e2008-01-11 18:48:24 +0800372
373/*
374 * TSEC ethernet configuration
375 */
376#define CONFIG_MII 1 /* MII PHY management */
377#define CONFIG_TSEC1 1
378#define CONFIG_TSEC1_NAME "eTSEC0"
379#define CONFIG_TSEC2 1
380#define CONFIG_TSEC2_NAME "eTSEC1"
381#define TSEC1_PHY_ADDR 0
382#define TSEC2_PHY_ADDR 1
383#define TSEC1_PHYIDX 0
384#define TSEC2_PHYIDX 0
385#define TSEC1_FLAGS TSEC_GIGABIT
386#define TSEC2_FLAGS TSEC_GIGABIT
387
388/* Options are: eTSEC[0-1] */
389#define CONFIG_ETHPRIME "eTSEC1"
390
391/*
Kim Phillips0daba0e2008-03-28 14:31:23 -0500392 * SATA
393 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200394#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kim Phillips0daba0e2008-03-28 14:31:23 -0500395#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200396#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger496f7722011-10-11 23:57:11 -0500397#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
398#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kim Phillips0daba0e2008-03-28 14:31:23 -0500399#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200400#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger496f7722011-10-11 23:57:11 -0500401#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
402#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kim Phillips0daba0e2008-03-28 14:31:23 -0500403
404#ifdef CONFIG_FSL_SATA
405#define CONFIG_LBA48
Kim Phillips0daba0e2008-03-28 14:31:23 -0500406#endif
407
408/*
Dave Liu19b247e2008-01-11 18:48:24 +0800409 * Environment
410 */
Masahiro Yamada5d329a82014-06-04 10:26:51 +0900411#if !defined(CONFIG_SYS_RAMBOOT)
Joe Hershberger496f7722011-10-11 23:57:11 -0500412 #define CONFIG_ENV_ADDR \
413 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200414 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
415 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19b247e2008-01-11 18:48:24 +0800416#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200417 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200418 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19b247e2008-01-11 18:48:24 +0800419#endif
420
421#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200422#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu19b247e2008-01-11 18:48:24 +0800423
424/*
425 * BOOTP options
426 */
427#define CONFIG_BOOTP_BOOTFILESIZE
Dave Liu19b247e2008-01-11 18:48:24 +0800428
429/*
430 * Command line configuration.
431 */
Dave Liu19b247e2008-01-11 18:48:24 +0800432
Dave Liu19b247e2008-01-11 18:48:24 +0800433#undef CONFIG_WATCHDOG /* watchdog disabled */
434
435/*
436 * Miscellaneous configurable options
437 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200438#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dave Liu19b247e2008-01-11 18:48:24 +0800439
Dave Liu19b247e2008-01-11 18:48:24 +0800440/*
441 * For booting Linux, the board info and command line data
Ira W. Snyderc5a22d02010-09-10 15:42:32 -0700442 * have to be in the first 256 MB of memory, since this is
Dave Liu19b247e2008-01-11 18:48:24 +0800443 * the maximum mapped by the Linux kernel during initialization.
444 */
Joe Hershberger496f7722011-10-11 23:57:11 -0500445#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Kevin Hao9c747962016-07-08 11:25:15 +0800446#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Dave Liu19b247e2008-01-11 18:48:24 +0800447
448/*
449 * Core HID Setup
450 */
Kim Phillipsf3c7cd92010-04-20 19:37:54 -0500451#define CONFIG_SYS_HID0_INIT 0x000000000
452#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
453 HID0_ENABLE_INSTRUCTION_CACHE | \
Dave Liu19b247e2008-01-11 18:48:24 +0800454 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200455#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu19b247e2008-01-11 18:48:24 +0800456
457/*
458 * MMU Setup
459 */
Becky Bruce03ea1be2008-05-08 19:02:12 -0500460#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Dave Liu19b247e2008-01-11 18:48:24 +0800461
462/* DDR: cache cacheable */
Joe Hershberger496f7722011-10-11 23:57:11 -0500463#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500464 | BATL_PP_RW \
Joe Hershberger496f7722011-10-11 23:57:11 -0500465 | BATL_MEMCOHERENCE)
466#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
467 | BATU_BL_128M \
468 | BATU_VS \
469 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200470#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
471#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu19b247e2008-01-11 18:48:24 +0800472
473/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger496f7722011-10-11 23:57:11 -0500474#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500475 | BATL_PP_RW \
Joe Hershberger496f7722011-10-11 23:57:11 -0500476 | BATL_CACHEINHIBIT \
477 | BATL_GUARDEDSTORAGE)
478#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
479 | BATU_BL_8M \
480 | BATU_VS \
481 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200482#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
483#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu19b247e2008-01-11 18:48:24 +0800484
485/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger496f7722011-10-11 23:57:11 -0500486#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500487 | BATL_PP_RW \
Joe Hershberger496f7722011-10-11 23:57:11 -0500488 | BATL_MEMCOHERENCE)
489#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
490 | BATU_BL_32M \
491 | BATU_VS \
492 | BATU_VP)
493#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500494 | BATL_PP_RW \
Joe Hershberger496f7722011-10-11 23:57:11 -0500495 | BATL_CACHEINHIBIT \
496 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200497#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu19b247e2008-01-11 18:48:24 +0800498
499/* Stack in dcache: cacheable, no memory coherence */
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500500#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger496f7722011-10-11 23:57:11 -0500501#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
502 | BATU_BL_128K \
503 | BATU_VS \
504 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200505#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
506#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu19b247e2008-01-11 18:48:24 +0800507
508/* PCI MEM space: cacheable */
Joe Hershberger496f7722011-10-11 23:57:11 -0500509#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500510 | BATL_PP_RW \
Joe Hershberger496f7722011-10-11 23:57:11 -0500511 | BATL_MEMCOHERENCE)
512#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
513 | BATU_BL_256M \
514 | BATU_VS \
515 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200516#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
517#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu19b247e2008-01-11 18:48:24 +0800518
519/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger496f7722011-10-11 23:57:11 -0500520#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500521 | BATL_PP_RW \
Joe Hershberger496f7722011-10-11 23:57:11 -0500522 | BATL_CACHEINHIBIT \
523 | BATL_GUARDEDSTORAGE)
524#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
525 | BATU_BL_256M \
526 | BATU_VS \
527 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200528#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
529#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu19b247e2008-01-11 18:48:24 +0800530
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200531#define CONFIG_SYS_IBAT6L 0
532#define CONFIG_SYS_IBAT6U 0
533#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
534#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu19b247e2008-01-11 18:48:24 +0800535
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200536#define CONFIG_SYS_IBAT7L 0
537#define CONFIG_SYS_IBAT7U 0
538#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
539#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19b247e2008-01-11 18:48:24 +0800540
Dave Liu19b247e2008-01-11 18:48:24 +0800541#if defined(CONFIG_CMD_KGDB)
542#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Dave Liu19b247e2008-01-11 18:48:24 +0800543#endif
544
545/*
546 * Environment Configuration
547 */
548
549#define CONFIG_ENV_OVERWRITE
550
551#if defined(CONFIG_TSEC_ENET)
552#define CONFIG_HAS_ETH0
Dave Liu19b247e2008-01-11 18:48:24 +0800553#define CONFIG_HAS_ETH1
Dave Liu19b247e2008-01-11 18:48:24 +0800554#endif
555
Kim Phillipsfd3a3fc2009-08-21 16:34:38 -0500556#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu19b247e2008-01-11 18:48:24 +0800557
Dave Liu19b247e2008-01-11 18:48:24 +0800558#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger496f7722011-10-11 23:57:11 -0500559 "netdev=eth0\0" \
560 "consoledev=ttyS0\0" \
561 "ramdiskaddr=1000000\0" \
562 "ramdiskfile=ramfs.83xx\0" \
563 "fdtaddr=780000\0" \
564 "fdtfile=mpc8315erdb.dtb\0" \
565 "usb_phy_type=utmi\0" \
566 ""
Dave Liu19b247e2008-01-11 18:48:24 +0800567
568#define CONFIG_NFSBOOTCOMMAND \
Joe Hershberger496f7722011-10-11 23:57:11 -0500569 "setenv bootargs root=/dev/nfs rw " \
570 "nfsroot=$serverip:$rootpath " \
571 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
572 "$netdev:off " \
573 "console=$consoledev,$baudrate $othbootargs;" \
574 "tftp $loadaddr $bootfile;" \
575 "tftp $fdtaddr $fdtfile;" \
576 "bootm $loadaddr - $fdtaddr"
Dave Liu19b247e2008-01-11 18:48:24 +0800577
578#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger496f7722011-10-11 23:57:11 -0500579 "setenv bootargs root=/dev/ram rw " \
580 "console=$consoledev,$baudrate $othbootargs;" \
581 "tftp $ramdiskaddr $ramdiskfile;" \
582 "tftp $loadaddr $bootfile;" \
583 "tftp $fdtaddr $fdtfile;" \
584 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Dave Liu19b247e2008-01-11 18:48:24 +0800585
Dave Liu19b247e2008-01-11 18:48:24 +0800586#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
587
588#endif /* __CONFIG_H */