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git01.mediatek.com / filogic / uboot / 1f493d95d5986bfff4e82df7701b96371ed415f5 / . / arch / arm / include / asm / arch-am33xx / ddr_defs.h
blob: fbe599d1ab36444cc62ab38609a26dca2149a7e4 [file] [log] [blame]
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]1/*
2 * ddr_defs.h
3 *
4 * ddr specific header
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]9 */
10
11#ifndef _DDR_DEFS_H
12#define _DDR_DEFS_H
13
14#include <asm/arch/hardware.h>
Tom Rinib668ae42012-07-24 14:55:38 -0700[diff] [blame]15#include <asm/emif.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]16
17/* AM335X EMIF Register values */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]18#define VTP_CTRL_READY (0x1 << 5)
19#define VTP_CTRL_ENABLE (0x1 << 6)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]20#define VTP_CTRL_START_EN (0x1)
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]21#ifdef CONFIG_AM43XX
22#define DDR_CKE_CTRL_NORMAL 0x3
23#else
Tom Rinide3c5702012-07-24 14:03:24 -0700[diff] [blame]24#define DDR_CKE_CTRL_NORMAL 0x1
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]25#endif
Vaibhav Hiremathc30d57b2013-03-14 21:11:16 +0000[diff] [blame]26#define PHY_EN_DYN_PWRDN (0x1 << 20)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]27
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]28/* Micron MT47H128M16RT-25E */
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]29#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
30#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
31#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
32#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
33#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
34#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]35#define MT47H128M16RT25E_RATIO 0x80
36#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
37#define MT47H128M16RT25E_RD_DQS 0x12
38#define MT47H128M16RT25E_WR_DQS 0x00
39#define MT47H128M16RT25E_PHY_WRLVL 0x00
40#define MT47H128M16RT25E_PHY_GATELVL 0x00
41#define MT47H128M16RT25E_PHY_WR_DATA 0x40
42#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]43#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]44
Tom Rini323315a2012-07-30 14:49:50 -0700[diff] [blame]45/* Micron MT41J128M16JT-125 */
Satyanarayana, Sandhyac698a1a2013-12-19 10:00:29 +0530[diff] [blame]46#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]47#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
48#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
49#define MT41J128MJT125_EMIF_TIM3 0x501F830F
50#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
51#define MT41J128MJT125_EMIF_SDREF 0x0000093B
52#define MT41J128MJT125_ZQ_CFG 0x50074BE4
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]53#define MT41J128MJT125_RATIO 0x40
54#define MT41J128MJT125_INVERT_CLKOUT 0x1
55#define MT41J128MJT125_RD_DQS 0x3B
56#define MT41J128MJT125_WR_DQS 0x85
57#define MT41J128MJT125_PHY_WR_DATA 0xC1
58#define MT41J128MJT125_PHY_FIFO_WE 0x100
59#define MT41J128MJT125_IOCTRL_VALUE 0x18B
Tom Rini323315a2012-07-30 14:49:50 -0700[diff] [blame]60
Ilya Ledvich791ca182013-11-07 07:57:33 +0200[diff] [blame]61/* Micron MT41J64M16JT-125 */
62#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
63
64/* Micron MT41J256M16JT-125 */
65#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
66
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]67/* Micron MT41J256M8HX-15E */
Satyanarayana, Sandhyac698a1a2013-12-19 10:00:29 +0530[diff] [blame]68#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]69#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
70#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
71#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
72#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
73#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
74#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]75#define MT41J256M8HX15E_RATIO 0x40
76#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
77#define MT41J256M8HX15E_RD_DQS 0x3B
78#define MT41J256M8HX15E_WR_DQS 0x85
79#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
80#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
81#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
82
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]83/* Micron MT41K256M16HA-125E */
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]84#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
85#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
Tom Rini05acd822013-04-12 12:38:16 -0400[diff] [blame]86#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
87#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
88#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]89#define MT41K256M16HA125E_EMIF_SDREF 0xC30
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]90#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]91#define MT41K256M16HA125E_RATIO 0x80
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]92#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
Tom Rini05acd822013-04-12 12:38:16 -0400[diff] [blame]93#define MT41K256M16HA125E_RD_DQS 0x38
94#define MT41K256M16HA125E_WR_DQS 0x44
95#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
96#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]97#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
98
Jeff Lance7c03a222013-01-14 05:32:20 +0000[diff] [blame]99/* Micron MT41J512M8RH-125 on EVM v1.5 */
Satyanarayana, Sandhyac698a1a2013-12-19 10:00:29 +0530[diff] [blame]100#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
Jeff Lance7c03a222013-01-14 05:32:20 +0000[diff] [blame]101#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
102#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
103#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
104#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
105#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
106#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
Jeff Lance7c03a222013-01-14 05:32:20 +0000[diff] [blame]107#define MT41J512M8RH125_RATIO 0x80
108#define MT41J512M8RH125_INVERT_CLKOUT 0x0
109#define MT41J512M8RH125_RD_DQS 0x3B
110#define MT41J512M8RH125_WR_DQS 0x3C
111#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
112#define MT41J512M8RH125_PHY_WR_DATA 0x74
113#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]114
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]115/* Samsung K4B2G1646E-BIH9 */
Satyanarayana, Sandhyac698a1a2013-12-19 10:00:29 +0530[diff] [blame]116#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007
Enric Balletbo i Serra177db362013-09-10 11:12:26 +0200[diff] [blame]117#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
118#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
119#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
120#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
121#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]122#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
Enric Balletbo i Serra177db362013-09-10 11:12:26 +0200[diff] [blame]123#define K4B2G1646EBIH9_RATIO 0x80
124#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
125#define K4B2G1646EBIH9_RD_DQS 0x35
126#define K4B2G1646EBIH9_WR_DQS 0x3A
127#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
128#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]129#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
130
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]131#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
132#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
133#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
134#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294
135#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294
136#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
137#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
138
Lokesh Vutladd0037a2013-12-10 15:02:23 +0530[diff] [blame]139#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
140#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
141#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
142#define DDR3_DATA0_IOCTRL_VALUE 0x84
143#define DDR3_DATA1_IOCTRL_VALUE 0x84
144#define DDR3_DATA2_IOCTRL_VALUE 0x84
145#define DDR3_DATA3_IOCTRL_VALUE 0x84
146
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]147/**
Matt Porter40355102013-03-15 10:07:07 +0000[diff] [blame]148 * Configure DMM
149 */
150void config_dmm(const struct dmm_lisa_map_regs *regs);
151
152/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]153 * Configure SDRAM
154 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]155void config_sdram(const struct emif_regs *regs, int nr);
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]156void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]157
158/**
159 * Set SDRAM timings
160 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]161void set_sdram_timings(const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]162
163/**
164 * Configure DDR PHY
165 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]166void config_ddr_phy(const struct emif_regs *regs, int nr);
167
168struct ddr_cmd_regs {
169 unsigned int resv0[7];
170 unsigned int cm0csratio; /* offset 0x01C */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]171 unsigned int resv1[3];
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]172 unsigned int cm0iclkout; /* offset 0x02C */
173 unsigned int resv2[8];
174 unsigned int cm1csratio; /* offset 0x050 */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]175 unsigned int resv3[3];
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]176 unsigned int cm1iclkout; /* offset 0x060 */
177 unsigned int resv4[8];
178 unsigned int cm2csratio; /* offset 0x084 */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]179 unsigned int resv5[3];
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]180 unsigned int cm2iclkout; /* offset 0x094 */
181 unsigned int resv6[3];
182};
183
184struct ddr_data_regs {
185 unsigned int dt0rdsratio0; /* offset 0x0C8 */
186 unsigned int resv1[4];
187 unsigned int dt0wdsratio0; /* offset 0x0DC */
188 unsigned int resv2[4];
189 unsigned int dt0wiratio0; /* offset 0x0F0 */
190 unsigned int resv3;
191 unsigned int dt0wimode0; /* offset 0x0F8 */
192 unsigned int dt0giratio0; /* offset 0x0FC */
193 unsigned int resv4;
194 unsigned int dt0gimode0; /* offset 0x104 */
195 unsigned int dt0fwsratio0; /* offset 0x108 */
196 unsigned int resv5[4];
197 unsigned int dt0dqoffset; /* offset 0x11C */
198 unsigned int dt0wrsratio0; /* offset 0x120 */
199 unsigned int resv6[4];
200 unsigned int dt0rdelays0; /* offset 0x134 */
201 unsigned int dt0dldiff0; /* offset 0x138 */
202 unsigned int resv7[12];
203};
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]204
205/**
206 * This structure represents the DDR registers on AM33XX devices.
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]207 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
208 * correspond to DATA1 registers defined here.
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]209 */
210struct ddr_regs {
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]211 unsigned int resv0[3];
212 unsigned int cm0config; /* offset 0x00C */
213 unsigned int cm0configclk; /* offset 0x010 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]214 unsigned int resv1[2];
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]215 unsigned int cm0csratio; /* offset 0x01C */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]216 unsigned int resv2[3];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]217 unsigned int cm0iclkout; /* offset 0x02C */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]218 unsigned int resv3[4];
219 unsigned int cm1config; /* offset 0x040 */
220 unsigned int cm1configclk; /* offset 0x044 */
221 unsigned int resv4[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]222 unsigned int cm1csratio; /* offset 0x050 */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]223 unsigned int resv5[3];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]224 unsigned int cm1iclkout; /* offset 0x060 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]225 unsigned int resv6[4];
226 unsigned int cm2config; /* offset 0x074 */
227 unsigned int cm2configclk; /* offset 0x078 */
228 unsigned int resv7[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]229 unsigned int cm2csratio; /* offset 0x084 */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]230 unsigned int resv8[3];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]231 unsigned int cm2iclkout; /* offset 0x094 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]232 unsigned int resv9[12];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]233 unsigned int dt0rdsratio0; /* offset 0x0C8 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]234 unsigned int resv10[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]235 unsigned int dt0wdsratio0; /* offset 0x0DC */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]236 unsigned int resv11[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]237 unsigned int dt0wiratio0; /* offset 0x0F0 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]238 unsigned int resv12;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]239 unsigned int dt0wimode0; /* offset 0x0F8 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]240 unsigned int dt0giratio0; /* offset 0x0FC */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]241 unsigned int resv13;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]242 unsigned int dt0gimode0; /* offset 0x104 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]243 unsigned int dt0fwsratio0; /* offset 0x108 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]244 unsigned int resv14[4];
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]245 unsigned int dt0dqoffset; /* offset 0x11C */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]246 unsigned int dt0wrsratio0; /* offset 0x120 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]247 unsigned int resv15[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]248 unsigned int dt0rdelays0; /* offset 0x134 */
249 unsigned int dt0dldiff0; /* offset 0x138 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]250};
251
252/**
253 * Encapsulates DDR CMD control registers.
254 */
255struct cmd_control {
256 unsigned long cmd0csratio;
257 unsigned long cmd0csforce;
258 unsigned long cmd0csdelay;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]259 unsigned long cmd0iclkout;
260 unsigned long cmd1csratio;
261 unsigned long cmd1csforce;
262 unsigned long cmd1csdelay;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]263 unsigned long cmd1iclkout;
264 unsigned long cmd2csratio;
265 unsigned long cmd2csforce;
266 unsigned long cmd2csdelay;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]267 unsigned long cmd2iclkout;
268};
269
270/**
271 * Encapsulates DDR DATA registers.
272 */
273struct ddr_data {
274 unsigned long datardsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]275 unsigned long datawdsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]276 unsigned long datawiratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]277 unsigned long datagiratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]278 unsigned long datafwsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]279 unsigned long datawrsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]280};
281
282/**
283 * Configure DDR CMD control registers
284 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]285void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]286
287/**
288 * Configure DDR DATA registers
289 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]290void config_ddr_data(const struct ddr_data *data, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]291
292/**
293 * This structure represents the DDR io control on AM33XX devices.
294 */
295struct ddr_cmdtctrl {
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]296 unsigned int cm0ioctl;
297 unsigned int cm1ioctl;
298 unsigned int cm2ioctl;
299 unsigned int resv2[12];
300 unsigned int dt0ioctl;
301 unsigned int dt1ioctl;
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]302 unsigned int dt2ioctrl;
303 unsigned int dt3ioctrl;
304 unsigned int resv3[4];
305 unsigned int emif_sdram_config_ext;
306};
307
308struct ctrl_ioregs {
309 unsigned int cm0ioctl;
310 unsigned int cm1ioctl;
311 unsigned int cm2ioctl;
312 unsigned int dt0ioctl;
313 unsigned int dt1ioctl;
314 unsigned int dt2ioctrl;
315 unsigned int dt3ioctrl;
316 unsigned int emif_sdram_config_ext;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]317};
318
319/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]320 * Configure DDR io control registers
321 */
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]322void config_io_ctrl(const struct ctrl_ioregs *ioregs);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]323
324struct ddr_ctrl {
325 unsigned int ddrioctrl;
326 unsigned int resv1[325];
327 unsigned int ddrckectrl;
328};
329
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]330void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]331 const struct ddr_data *data, const struct cmd_control *ctrl,
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]332 const struct emif_regs *regs, int nr);
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]333void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]334
335#endif /* _DDR_DEFS_H */