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Sricharan9310ff72011-11-15 09:49:55 -05001/*
2 * (C) Copyright 2010
3 * Texas Instruments, <www.ti.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Sricharan9310ff72011-11-15 09:49:55 -05006 */
7
8#ifndef _SYS_PROTO_H_
9#define _SYS_PROTO_H_
10
11#include <asm/arch/omap.h>
12#include <asm/io.h>
Lokesh Vutla61c517f2013-05-30 02:54:32 +000013#include <asm/arch/clock.h>
Sricharan9310ff72011-11-15 09:49:55 -050014#include <asm/omap_common.h>
pekon gupta5bbb0992013-11-22 16:53:29 +053015#include <linux/mtd/omap_gpmc.h>
Lokesh Vutla61c517f2013-05-30 02:54:32 +000016#include <asm/arch/clock.h>
Tom Rini72f36002014-05-16 13:02:24 -040017#include <asm/ti-common/sys_proto.h>
Sricharan9310ff72011-11-15 09:49:55 -050018
SRICHARAN R3f30b0a2013-04-24 00:41:24 +000019DECLARE_GLOBAL_DATA_PTR;
20
Lokesh Vutlaf0ee64a2015-06-04 16:42:37 +053021/*
22 * Structure for Iodelay configuration registers.
23 * Theoretical max for g_delay is 21560 ps.
24 * Theoretical max for a_delay is 1/3rd of g_delay max.
25 * So using u16 for both a/g_delay.
26 */
27struct iodelay_cfg_entry {
28 u16 offset;
29 u16 a_delay;
30 u16 g_delay;
31};
32
Lokesh Vutla40700ad2013-02-12 21:29:08 +000033struct pad_conf_entry {
34 u32 offset;
35 u32 val;
36};
37
Kishon Vijay Abraham I8c2efe92018-01-30 16:01:41 +010038struct mmc_platform_fixups {
39 const char *hw_rev;
40 u32 unsupported_caps;
41 u32 max_freq;
42};
43
Sricharan9310ff72011-11-15 09:49:55 -050044struct omap_sysinfo {
45 char *board_string;
46};
47extern const struct omap_sysinfo sysinfo;
48
Sricharan9310ff72011-11-15 09:49:55 -050049void gpmc_init(void);
50void watchdog_init(void);
51u32 get_device_type(void);
52void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
Lokesh Vutla5dedc172015-06-04 16:42:33 +053053void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size);
Paul Kocialkowskia00b1e52016-02-27 19:18:56 +010054void set_muxconf_regs(void);
Sricharan9310ff72011-11-15 09:49:55 -050055u32 wait_on_value(u32, u32, void *, u32);
56void sdelay(unsigned long);
Kipisz, Stevenebe86dc2016-02-24 12:30:52 -060057void setup_early_clocks(void);
Sricharan9310ff72011-11-15 09:49:55 -050058void prcm_init(void);
Kipisz, Steven4466dfb2016-02-24 12:30:57 -060059void do_board_detect(void);
Keerthy35740ec2016-05-24 11:45:05 +053060void vcores_init(void);
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +000061void bypass_dpll(u32 const base);
Sricharan9310ff72011-11-15 09:49:55 -050062void freq_update_core(void);
63u32 get_sys_clk_freq(void);
64u32 omap5_ddr_clk(void);
65void cancel_out(u32 *num, u32 *den, u32 den_limit);
66void sdram_init(void);
67u32 omap_sdram_size(void);
68u32 cortex_rev(void);
Tom Rini51df26c2013-05-31 12:31:59 -040069void save_omap_boot_params(void);
Sricharan9310ff72011-11-15 09:49:55 -050070void init_omap_revision(void);
Lokesh Vutla69483e62017-12-29 11:47:51 +053071void init_package_revision(void);
Sricharan9310ff72011-11-15 09:49:55 -050072void do_io_settings(void);
Lokesh Vutlaae49f6d2013-05-30 02:54:33 +000073void sri2c_init(void);
Nishanth Menon41d7ab12012-03-01 14:17:37 +000074int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
Lokesh Vutlae89f1542012-05-29 19:26:41 +000075u32 warm_reset(void);
Lokesh Vutlaba873772012-05-29 19:26:43 +000076void force_emif_self_refresh(void);
Lokesh Vutlad8ac0502013-02-04 04:22:05 +000077void get_ioregs(const struct ctrl_ioregs **regs);
Lokesh Vutla28049632013-02-12 01:33:45 +000078void srcomp_enable(void);
Lokesh Vutla100c2d82013-04-17 20:49:40 +000079void setup_warmreset_time(void);
Kishon Vijay Abraham I8c2efe92018-01-30 16:01:41 +010080const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr);
Sricharan9310ff72011-11-15 09:49:55 -050081
Lokesh Vutla100c2d82013-04-17 20:49:40 +000082static inline u32 div_round_up(u32 num, u32 den)
83{
84 return (num + den - 1)/den;
85}
86
87static inline u32 usec_to_32k(u32 usec)
88{
89 return div_round_up(32768 * usec, 1000000);
90}
Praveen Rao3206b8a2015-03-09 17:12:06 -050091
92#define OMAP5_SERVICE_L2ACTLR_SET 0x104
Nishanth Menon2740b832015-07-27 16:26:06 -050093#define OMAP5_SERVICE_ACR_SET 0x107
Praveen Rao3206b8a2015-03-09 17:12:06 -050094
Sricharan9310ff72011-11-15 09:49:55 -050095#endif