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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Heiko Schocherfe954e32011-09-14 19:59:38 +00002/*
Christian Riesch0e5e0c52011-11-08 08:55:07 -05003 * SoC-specific lowlevel code for DA850
Heiko Schocherfe954e32011-09-14 19:59:38 +00004 *
5 * Copyright (C) 2011
6 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
Heiko Schocherfe954e32011-09-14 19:59:38 +00007 */
8#include <common.h>
9#include <nand.h>
10#include <ns16550.h>
11#include <post.h>
Christian Riesch0e5e0c52011-11-08 08:55:07 -050012#include <asm/arch/da850_lowlevel.h>
Heiko Schocherfe954e32011-09-14 19:59:38 +000013#include <asm/arch/hardware.h>
Christian Riesch2eb60502011-11-28 23:46:20 +000014#include <asm/arch/davinci_misc.h>
Heiko Schocherfe954e32011-09-14 19:59:38 +000015#include <asm/arch/ddr2_defs.h>
Khoronzhuk, Ivan753a00a2014-06-07 04:22:52 +030016#include <asm/ti-common/davinci_nand.h>
Heiko Schocher34061e82011-11-15 10:00:02 -050017#include <asm/arch/pll_defs.h>
Heiko Schocherfe954e32011-09-14 19:59:38 +000018
Eric Benard3c3dc792013-04-22 05:54:59 +000019void davinci_enable_uart0(void)
20{
21 lpsc_on(DAVINCI_LPSC_UART0);
22
23 /* Bringup UART0 out of reset */
24 REG(UART0_PWREMU_MGMT) = 0x00006001;
25}
26
Sughosh Ganua2616972012-02-02 00:44:41 +000027#if defined(CONFIG_SYS_DA850_PLL_INIT)
Manish Badarkhed47dffe2014-04-11 08:02:04 +053028static void da850_waitloop(unsigned long loopcnt)
Heiko Schocherfe954e32011-09-14 19:59:38 +000029{
30 unsigned long i;
31
32 for (i = 0; i < loopcnt; i++)
33 asm(" NOP");
34}
35
Manish Badarkhed47dffe2014-04-11 08:02:04 +053036static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
Heiko Schocherfe954e32011-09-14 19:59:38 +000037{
38 if (reg == davinci_pllc0_regs)
39 /* Unlock PLL registers. */
Heiko Schocher34061e82011-11-15 10:00:02 -050040 clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
Heiko Schocherfe954e32011-09-14 19:59:38 +000041
42 /*
43 * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
44 * through MMR
45 */
Heiko Schocher34061e82011-11-15 10:00:02 -050046 clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
Heiko Schocherfe954e32011-09-14 19:59:38 +000047 /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
Heiko Schocher34061e82011-11-15 10:00:02 -050048 clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
Heiko Schocherfe954e32011-09-14 19:59:38 +000049
50 /* Set PLLEN=0 => PLL BYPASS MODE */
Heiko Schocher34061e82011-11-15 10:00:02 -050051 clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
Heiko Schocherfe954e32011-09-14 19:59:38 +000052
Christian Riesch0e5e0c52011-11-08 08:55:07 -050053 da850_waitloop(150);
Heiko Schocherfe954e32011-09-14 19:59:38 +000054
55 if (reg == davinci_pllc0_regs) {
56 /*
57 * Select the Clock Mode bit 8 as External Clock or On Chip
58 * Oscilator
59 */
Heiko Schocher34061e82011-11-15 10:00:02 -050060 dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
61 setbits_le32(&reg->pllctl,
62 (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
Heiko Schocherfe954e32011-09-14 19:59:38 +000063 }
64
65 /* Clear PLLRST bit to reset the PLL */
Heiko Schocher34061e82011-11-15 10:00:02 -050066 clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
Heiko Schocherfe954e32011-09-14 19:59:38 +000067
68 /* Disable the PLL output */
Heiko Schocher34061e82011-11-15 10:00:02 -050069 setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
Heiko Schocherfe954e32011-09-14 19:59:38 +000070
71 /* PLL initialization sequence */
72 /*
73 * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
74 * power down bit
75 */
Heiko Schocher34061e82011-11-15 10:00:02 -050076 clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
Heiko Schocherfe954e32011-09-14 19:59:38 +000077
78 /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
Heiko Schocher34061e82011-11-15 10:00:02 -050079 clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
Heiko Schocherfe954e32011-09-14 19:59:38 +000080
Ben Gardinerb2a47522012-01-16 07:43:15 +000081#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
82 /* program the prediv */
83 if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
84 writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
85 &reg->prediv);
86#endif
87
Heiko Schocherfe954e32011-09-14 19:59:38 +000088 /* Program the required multiplier value in PLLM */
89 writel(pllmult, &reg->pllm);
90
91 /* program the postdiv */
92 if (reg == davinci_pllc0_regs)
Heiko Schocher34061e82011-11-15 10:00:02 -050093 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
Heiko Schocherfe954e32011-09-14 19:59:38 +000094 &reg->postdiv);
95 else
Heiko Schocher34061e82011-11-15 10:00:02 -050096 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
Heiko Schocherfe954e32011-09-14 19:59:38 +000097 &reg->postdiv);
98
99 /*
100 * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
101 * no GO operation is currently in progress
102 */
Heiko Schocher34061e82011-11-15 10:00:02 -0500103 while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
Heiko Schocherfe954e32011-09-14 19:59:38 +0000104 ;
105
106 if (reg == davinci_pllc0_regs) {
Christian Riesch0e5e0c52011-11-08 08:55:07 -0500107 writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
108 writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
109 writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
110 writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
111 writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
112 writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
113 writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000114 } else {
Christian Riesch0e5e0c52011-11-08 08:55:07 -0500115 writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
116 writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
117 writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000118 }
119
120 /*
121 * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
122 * transition.
123 */
Heiko Schocher34061e82011-11-15 10:00:02 -0500124 setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000125
126 /*
127 * Wait for the GOSTAT bit in PLLSTAT to clear to 0
128 * (completion of phase alignment).
129 */
Heiko Schocher34061e82011-11-15 10:00:02 -0500130 while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
Heiko Schocherfe954e32011-09-14 19:59:38 +0000131 ;
132
133 /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
Christian Riesch0e5e0c52011-11-08 08:55:07 -0500134 da850_waitloop(200);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000135
136 /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
Heiko Schocher34061e82011-11-15 10:00:02 -0500137 setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000138
139 /* Wait for PLL to lock. See PLL spec for PLL lock time */
Christian Riesch0e5e0c52011-11-08 08:55:07 -0500140 da850_waitloop(2400);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000141
142 /*
143 * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
144 * mode
145 */
Heiko Schocher34061e82011-11-15 10:00:02 -0500146 setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000147
148
149 /*
150 * clear EMIFA and EMIFB clock source settings, let them
151 * run off SYSCLK
152 */
153 if (reg == davinci_pllc0_regs)
Heiko Schocher34061e82011-11-15 10:00:02 -0500154 dv_maskbits(&davinci_syscfg_regs->cfgchip3,
155 ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
Heiko Schocherfe954e32011-09-14 19:59:38 +0000156
157 return 0;
158}
Sughosh Ganua2616972012-02-02 00:44:41 +0000159#endif /* CONFIG_SYS_DA850_PLL_INIT */
Heiko Schocherfe954e32011-09-14 19:59:38 +0000160
Sughosh Ganua2616972012-02-02 00:44:41 +0000161#if defined(CONFIG_SYS_DA850_DDR_INIT)
Manish Badarkhed47dffe2014-04-11 08:02:04 +0530162static int da850_ddr_setup(void)
Heiko Schocherfe954e32011-09-14 19:59:38 +0000163{
164 unsigned long tmp;
165
166 /* Enable the Clock to DDR2/mDDR */
Christian Riesch99271c82011-11-08 08:55:10 -0500167 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000168
169 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
170 if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
171 /* Begin VTP Calibration */
172 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
173 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
174 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
175 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
176 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
177
178 /* Polling READY bit to see when VTP calibration is done */
179 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
180 while ((tmp & VTP_READY) != VTP_READY)
181 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
182
183 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
184 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000185 }
Mikhail Kshevetskiy4a6d36e2012-07-09 08:52:41 +0000186 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
Christian Riesch0e5e0c52011-11-08 08:55:07 -0500187 writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
Mikhail Kshevetskiy4a6d36e2012-07-09 08:52:41 +0000188
189 if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
190 /* DDR2 */
191 clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
192 (1 << DDR_SLEW_DDR_PDENA_BIT) |
193 (1 << DDR_SLEW_CMOSEN_BIT));
194 } else {
195 /* MOBILE DDR */
196 setbits_le32(&davinci_syscfg1_regs->ddr_slew,
197 (1 << DDR_SLEW_DDR_PDENA_BIT) |
198 (1 << DDR_SLEW_CMOSEN_BIT));
199 }
Heiko Schocherfe954e32011-09-14 19:59:38 +0000200
Christian Riesch81ad48e2011-11-08 08:55:13 -0500201 /*
202 * SDRAM Configuration Register (SDCR):
203 * First set the BOOTUNLOCK bit to make configuration bits
204 * writeable.
205 */
Heiko Schocherfe954e32011-09-14 19:59:38 +0000206 setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
207
Christian Riesch81ad48e2011-11-08 08:55:13 -0500208 /*
209 * Write the new value of these bits and clear BOOTUNLOCK.
210 * At the same time, set the TIMUNLOCK bit to allow changing
211 * the timing registers
212 */
213 tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
Heiko Schocher34061e82011-11-15 10:00:02 -0500214 tmp &= ~DV_DDR_BOOTUNLOCK;
215 tmp |= DV_DDR_TIMUNLOCK;
Christian Riesch81ad48e2011-11-08 08:55:13 -0500216 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000217
Christian Riesch81ad48e2011-11-08 08:55:13 -0500218 /* write memory configuration and timing */
Mikhail Kshevetskiy4a6d36e2012-07-09 08:52:41 +0000219 if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
220 /* MOBILE DDR only*/
221 writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
222 &dv_ddr2_regs_ctrl->sdbcr2);
223 }
Christian Riesch0e5e0c52011-11-08 08:55:07 -0500224 writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
225 writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000226
Christian Riesch81ad48e2011-11-08 08:55:13 -0500227 /* clear the TIMUNLOCK bit and write the value of the CL field */
Heiko Schocher34061e82011-11-15 10:00:02 -0500228 tmp &= ~DV_DDR_TIMUNLOCK;
Christian Riesch81ad48e2011-11-08 08:55:13 -0500229 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000230
231 /*
232 * LPMODEN and MCLKSTOPEN must be set!
233 * Without this bits set, PSC don;t switch states !!
234 */
Christian Riesch0e5e0c52011-11-08 08:55:07 -0500235 writel(CONFIG_SYS_DA850_DDR2_SDRCR |
Heiko Schocherfe954e32011-09-14 19:59:38 +0000236 (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
237 (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
238 &dv_ddr2_regs_ctrl->sdrcr);
239
240 /* SyncReset the Clock to EMIF3A SDRAM */
Christian Riesch99271c82011-11-08 08:55:10 -0500241 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000242 /* Enable the Clock to EMIF3A SDRAM */
Christian Riesch99271c82011-11-08 08:55:10 -0500243 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000244
245 /* disable self refresh */
Heiko Schocher34061e82011-11-15 10:00:02 -0500246 clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
Mikhail Kshevetskiy4a6d36e2012-07-09 08:52:41 +0000247 DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
Heiko Schocher34061e82011-11-15 10:00:02 -0500248 writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000249
250 return 0;
251}
Sughosh Ganua2616972012-02-02 00:44:41 +0000252#endif /* CONFIG_SYS_DA850_DDR_INIT */
Heiko Schocherfe954e32011-09-14 19:59:38 +0000253
Heiko Schocherfe954e32011-09-14 19:59:38 +0000254__attribute__((weak))
255void board_gpio_init(void)
256{
257 return;
258}
259
Heiko Schocherfe954e32011-09-14 19:59:38 +0000260int arch_cpu_init(void)
Heiko Schocherfe954e32011-09-14 19:59:38 +0000261{
Heiko Schocherfe954e32011-09-14 19:59:38 +0000262 /* Unlock kick registers */
Heiko Schocher34061e82011-11-15 10:00:02 -0500263 writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
264 writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000265
266 dv_maskbits(&davinci_syscfg_regs->suspsrc,
Heiko Schocher34061e82011-11-15 10:00:02 -0500267 CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
Heiko Schocherfe954e32011-09-14 19:59:38 +0000268
Christian Riesch2eb60502011-11-28 23:46:20 +0000269 /* configure pinmux settings */
270 if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
271 return 1;
Heiko Schocherfe954e32011-09-14 19:59:38 +0000272
Sughosh Ganua2616972012-02-02 00:44:41 +0000273#if defined(CONFIG_SYS_DA850_PLL_INIT)
Heiko Schocherfe954e32011-09-14 19:59:38 +0000274 /* PLL setup */
Christian Riesch0e5e0c52011-11-08 08:55:07 -0500275 da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
276 da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
Sughosh Ganua2616972012-02-02 00:44:41 +0000277#endif
Heiko Schocherfe954e32011-09-14 19:59:38 +0000278 /* setup CSn config */
Heiko Schocher34061e82011-11-15 10:00:02 -0500279#if defined(CONFIG_SYS_DA850_CS2CFG)
Christian Riesch0e5e0c52011-11-08 08:55:07 -0500280 writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
Heiko Schocher34061e82011-11-15 10:00:02 -0500281#endif
282#if defined(CONFIG_SYS_DA850_CS3CFG)
Christian Riesch0e5e0c52011-11-08 08:55:07 -0500283 writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
Heiko Schocher34061e82011-11-15 10:00:02 -0500284#endif
Heiko Schocherfe954e32011-09-14 19:59:38 +0000285
Sughosh Ganua2616972012-02-02 00:44:41 +0000286 da8xx_configure_lpsc_items(lpsc, lpsc_size);
287
288 /* GPIO setup */
289 board_gpio_init();
290
Adam Ford88fe03c2018-08-13 21:09:17 -0500291#if !defined(CONFIG_DM_SERIAL)
Heiko Schocherfe954e32011-09-14 19:59:38 +0000292 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
293 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
Adam Ford88fe03c2018-08-13 21:09:17 -0500294#endif
Heiko Schocherfe954e32011-09-14 19:59:38 +0000295 /*
296 * Fix Power and Emulation Management Register
297 * see sprufw3a.pdf page 37 Table 24
298 */
Heiko Schocher34061e82011-11-15 10:00:02 -0500299 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
300 DAVINCI_UART_PWREMU_MGMT_UTRST),
Heiko Schochere999dca2013-08-05 16:00:37 +0200301#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
302 &davinci_uart0_ctrl_regs->pwremu_mgmt);
303#else
Heiko Schocher34061e82011-11-15 10:00:02 -0500304 &davinci_uart2_ctrl_regs->pwremu_mgmt);
Heiko Schochere999dca2013-08-05 16:00:37 +0200305#endif
Heiko Schocherfe954e32011-09-14 19:59:38 +0000306
Sughosh Ganua2616972012-02-02 00:44:41 +0000307#if defined(CONFIG_SYS_DA850_DDR_INIT)
Heiko Schocher34061e82011-11-15 10:00:02 -0500308 da850_ddr_setup();
Sughosh Ganua2616972012-02-02 00:44:41 +0000309#endif
310
Heiko Schocherfe954e32011-09-14 19:59:38 +0000311 return 0;
Heiko Schocherfe954e32011-09-14 19:59:38 +0000312}