blob: 6d94e7af38e9af1ca002ea142e03c812134aa64d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergey Lapin77e524c2008-10-31 12:28:43 +01002/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Sergey Lapin77e524c2008-10-31 12:28:43 +01005 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8 *
Wu, Joshfd3091d2012-08-23 00:05:36 +00009 * Add Programmable Multibit ECC support for various AT91 SoC
10 * (C) Copyright 2012 ATMEL, Hong Xu
Sergey Lapin77e524c2008-10-31 12:28:43 +010011 */
12
13#include <common.h>
Simon Glass0f2af882020-05-10 11:40:05 -060014#include <log.h>
Sean Anderson11a4c702023-11-04 16:37:41 -040015#include <system-constants.h>
Andreas Bießmanna4c24d32013-11-29 12:13:45 +010016#include <asm/gpio.h>
Sergey Lapin77e524c2008-10-31 12:28:43 +010017#include <asm/arch/gpio.h>
Simon Glass9bc15642020-02-03 07:36:16 -070018#include <dm/device_compat.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070019#include <dm/devres.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060020#include <linux/bitops.h>
Simon Glassc06c1be2020-05-10 11:40:08 -060021#include <linux/bug.h>
Simon Glassdbd79542020-05-10 11:40:11 -060022#include <linux/delay.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060023#include <linux/printk.h>
Sergey Lapin77e524c2008-10-31 12:28:43 +010024
Wu, Josh4e87b3152013-07-03 11:11:48 +080025#include <malloc.h>
Sergey Lapin77e524c2008-10-31 12:28:43 +010026#include <nand.h>
Wu, Joshfd3091d2012-08-23 00:05:36 +000027#include <watchdog.h>
Heiko Schocherfd683382014-10-31 08:31:01 +010028#include <linux/mtd/nand_ecc.h>
Tom Rini3bde7e22021-09-22 14:50:35 -040029#include <linux/mtd/rawnand.h>
Sergey Lapin77e524c2008-10-31 12:28:43 +010030
Nikolay Petukhove6015ca2010-03-19 10:49:27 +050031#ifdef CONFIG_ATMEL_NAND_HWECC
32
33/* Register access macros */
34#define ecc_readl(add, reg) \
Andre Renaudcf44b942016-05-05 07:28:14 -060035 readl(add + ATMEL_ECC_##reg)
Nikolay Petukhove6015ca2010-03-19 10:49:27 +050036#define ecc_writel(add, reg, value) \
Andre Renaudcf44b942016-05-05 07:28:14 -060037 writel((value), add + ATMEL_ECC_##reg)
Nikolay Petukhove6015ca2010-03-19 10:49:27 +050038
39#include "atmel_nand_ecc.h" /* Hardware ECC registers */
40
Wu, Joshfd3091d2012-08-23 00:05:36 +000041#ifdef CONFIG_ATMEL_NAND_HW_PMECC
42
43struct atmel_nand_host {
44 struct pmecc_regs __iomem *pmecc;
45 struct pmecc_errloc_regs __iomem *pmerrloc;
46 void __iomem *pmecc_rom_base;
47
48 u8 pmecc_corr_cap;
49 u16 pmecc_sector_size;
50 u32 pmecc_index_table_offset;
Wu, Josh1f5c0892015-01-16 11:54:46 +080051 u32 pmecc_version;
Wu, Joshfd3091d2012-08-23 00:05:36 +000052
53 int pmecc_bytes_per_sector;
54 int pmecc_sector_number;
55 int pmecc_degree; /* Degree of remainders */
56 int pmecc_cw_len; /* Length of codeword */
57
58 /* lookup table for alpha_to and index_of */
59 void __iomem *pmecc_alpha_to;
60 void __iomem *pmecc_index_of;
61
62 /* data for pmecc computation */
Wu, Josh4e87b3152013-07-03 11:11:48 +080063 int16_t *pmecc_smu;
64 int16_t *pmecc_partial_syn;
65 int16_t *pmecc_si;
66 int16_t *pmecc_lmu; /* polynomal order */
67 int *pmecc_mu;
68 int *pmecc_dmu;
69 int *pmecc_delta;
Wu, Joshfd3091d2012-08-23 00:05:36 +000070};
71
72static struct atmel_nand_host pmecc_host;
73static struct nand_ecclayout atmel_pmecc_oobinfo;
74
75/*
76 * Return number of ecc bytes per sector according to sector size and
77 * correction capability
78 *
79 * Following table shows what at91 PMECC supported:
80 * Correction Capability Sector_512_bytes Sector_1024_bytes
81 * ===================== ================ =================
82 * 2-bits 4-bytes 4-bytes
83 * 4-bits 7-bytes 7-bytes
84 * 8-bits 13-bytes 14-bytes
85 * 12-bits 20-bytes 21-bytes
86 * 24-bits 39-bytes 42-bytes
Josh Wuce764952015-11-24 16:34:01 +080087 * 32-bits 52-bytes 56-bytes
Wu, Joshfd3091d2012-08-23 00:05:36 +000088 */
89static int pmecc_get_ecc_bytes(int cap, int sector_size)
90{
91 int m = 12 + sector_size / 512;
92 return (m * cap + 7) / 8;
93}
94
95static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
96 int oobsize, int ecc_len)
97{
98 int i;
99
100 layout->eccbytes = ecc_len;
101
102 /* ECC will occupy the last ecc_len bytes continuously */
103 for (i = 0; i < ecc_len; i++)
104 layout->eccpos[i] = oobsize - ecc_len + i;
105
106 layout->oobfree[0].offset = 2;
107 layout->oobfree[0].length =
108 oobsize - ecc_len - layout->oobfree[0].offset;
109}
110
111static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
112{
113 int table_size;
114
115 table_size = host->pmecc_sector_size == 512 ?
116 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
117
118 /* the ALPHA lookup table is right behind the INDEX lookup table. */
119 return host->pmecc_rom_base + host->pmecc_index_table_offset +
120 table_size * sizeof(int16_t);
121}
122
Wu, Josh4e87b3152013-07-03 11:11:48 +0800123static void pmecc_data_free(struct atmel_nand_host *host)
124{
125 free(host->pmecc_partial_syn);
126 free(host->pmecc_si);
127 free(host->pmecc_lmu);
128 free(host->pmecc_smu);
129 free(host->pmecc_mu);
130 free(host->pmecc_dmu);
131 free(host->pmecc_delta);
132}
133
134static int pmecc_data_alloc(struct atmel_nand_host *host)
135{
136 const int cap = host->pmecc_corr_cap;
137 int size;
138
139 size = (2 * cap + 1) * sizeof(int16_t);
140 host->pmecc_partial_syn = malloc(size);
141 host->pmecc_si = malloc(size);
142 host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
143 host->pmecc_smu = malloc((cap + 2) * size);
144
145 size = (cap + 1) * sizeof(int);
146 host->pmecc_mu = malloc(size);
147 host->pmecc_dmu = malloc(size);
148 host->pmecc_delta = malloc(size);
149
150 if (host->pmecc_partial_syn &&
151 host->pmecc_si &&
152 host->pmecc_lmu &&
153 host->pmecc_smu &&
154 host->pmecc_mu &&
155 host->pmecc_dmu &&
156 host->pmecc_delta)
157 return 0;
158
159 /* error happened */
160 pmecc_data_free(host);
161 return -ENOMEM;
162
163}
164
Wu, Joshfd3091d2012-08-23 00:05:36 +0000165static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
166{
Scott Wood17fed142016-05-30 13:57:56 -0500167 struct nand_chip *nand_chip = mtd_to_nand(mtd);
168 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000169 int i;
170 uint32_t value;
171
172 /* Fill odd syndromes */
173 for (i = 0; i < host->pmecc_corr_cap; i++) {
Wu, Joshb31868f2014-06-24 18:18:06 +0800174 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000175 if (i & 1)
176 value >>= 16;
177 value &= 0xffff;
178 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
179 }
180}
181
182static void pmecc_substitute(struct mtd_info *mtd)
183{
Scott Wood17fed142016-05-30 13:57:56 -0500184 struct nand_chip *nand_chip = mtd_to_nand(mtd);
185 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000186 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
187 int16_t __iomem *index_of = host->pmecc_index_of;
188 int16_t *partial_syn = host->pmecc_partial_syn;
189 const int cap = host->pmecc_corr_cap;
190 int16_t *si;
191 int i, j;
192
193 /* si[] is a table that holds the current syndrome value,
194 * an element of that table belongs to the field
195 */
196 si = host->pmecc_si;
197
198 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
199
200 /* Computation 2t syndromes based on S(x) */
201 /* Odd syndromes */
202 for (i = 1; i < 2 * cap; i += 2) {
203 for (j = 0; j < host->pmecc_degree; j++) {
204 if (partial_syn[i] & (0x1 << j))
205 si[i] = readw(alpha_to + i * j) ^ si[i];
206 }
207 }
208 /* Even syndrome = (Odd syndrome) ** 2 */
209 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
210 if (si[j] == 0) {
211 si[i] = 0;
212 } else {
213 int16_t tmp;
214
215 tmp = readw(index_of + si[j]);
216 tmp = (tmp * 2) % host->pmecc_cw_len;
217 si[i] = readw(alpha_to + tmp);
218 }
219 }
220}
221
222/*
223 * This function defines a Berlekamp iterative procedure for
224 * finding the value of the error location polynomial.
225 * The input is si[], initialize by pmecc_substitute().
226 * The output is smu[][].
227 *
228 * This function is written according to chip datasheet Chapter:
229 * Find the Error Location Polynomial Sigma(x) of Section:
230 * Programmable Multibit ECC Control (PMECC).
231 */
232static void pmecc_get_sigma(struct mtd_info *mtd)
233{
Scott Wood17fed142016-05-30 13:57:56 -0500234 struct nand_chip *nand_chip = mtd_to_nand(mtd);
235 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000236
237 int16_t *lmu = host->pmecc_lmu;
238 int16_t *si = host->pmecc_si;
239 int *mu = host->pmecc_mu;
240 int *dmu = host->pmecc_dmu; /* Discrepancy */
241 int *delta = host->pmecc_delta; /* Delta order */
242 int cw_len = host->pmecc_cw_len;
243 const int16_t cap = host->pmecc_corr_cap;
244 const int num = 2 * cap + 1;
245 int16_t __iomem *index_of = host->pmecc_index_of;
246 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
247 int i, j, k;
248 uint32_t dmu_0_count, tmp;
249 int16_t *smu = host->pmecc_smu;
250
251 /* index of largest delta */
252 int ro;
253 int largest;
254 int diff;
255
256 /* Init the Sigma(x) */
Bin Meng455ef432018-10-08 02:27:44 -0700257 memset(smu, 0, sizeof(int16_t) * num * (cap + 2));
Wu, Joshfd3091d2012-08-23 00:05:36 +0000258
259 dmu_0_count = 0;
260
261 /* First Row */
262
263 /* Mu */
264 mu[0] = -1;
265
266 smu[0] = 1;
267
268 /* discrepancy set to 1 */
269 dmu[0] = 1;
270 /* polynom order set to 0 */
271 lmu[0] = 0;
272 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
273 delta[0] = -1;
274
275 /* Second Row */
276
277 /* Mu */
278 mu[1] = 0;
279 /* Sigma(x) set to 1 */
280 smu[num] = 1;
281
282 /* discrepancy set to S1 */
283 dmu[1] = si[1];
284
285 /* polynom order set to 0 */
286 lmu[1] = 0;
287
288 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
289 delta[1] = 0;
290
291 for (i = 1; i <= cap; i++) {
292 mu[i + 1] = i << 1;
293 /* Begin Computing Sigma (Mu+1) and L(mu) */
294 /* check if discrepancy is set to 0 */
295 if (dmu[i] == 0) {
296 dmu_0_count++;
297
298 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
299 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
300 tmp += 2;
301 else
302 tmp += 1;
303
304 if (dmu_0_count == tmp) {
305 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
306 smu[(cap + 1) * num + j] =
307 smu[i * num + j];
308
309 lmu[cap + 1] = lmu[i];
310 return;
311 }
312
313 /* copy polynom */
314 for (j = 0; j <= lmu[i] >> 1; j++)
315 smu[(i + 1) * num + j] = smu[i * num + j];
316
317 /* copy previous polynom order to the next */
318 lmu[i + 1] = lmu[i];
319 } else {
320 ro = 0;
321 largest = -1;
322 /* find largest delta with dmu != 0 */
323 for (j = 0; j < i; j++) {
324 if ((dmu[j]) && (delta[j] > largest)) {
325 largest = delta[j];
326 ro = j;
327 }
328 }
329
330 /* compute difference */
331 diff = (mu[i] - mu[ro]);
332
333 /* Compute degree of the new smu polynomial */
334 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
335 lmu[i + 1] = lmu[i];
336 else
337 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
338
339 /* Init smu[i+1] with 0 */
340 for (k = 0; k < num; k++)
341 smu[(i + 1) * num + k] = 0;
342
343 /* Compute smu[i+1] */
344 for (k = 0; k <= lmu[ro] >> 1; k++) {
345 int16_t a, b, c;
346
347 if (!(smu[ro * num + k] && dmu[i]))
348 continue;
349 a = readw(index_of + dmu[i]);
350 b = readw(index_of + dmu[ro]);
351 c = readw(index_of + smu[ro * num + k]);
352 tmp = a + (cw_len - b) + c;
353 a = readw(alpha_to + tmp % cw_len);
354 smu[(i + 1) * num + (k + diff)] = a;
355 }
356
357 for (k = 0; k <= lmu[i] >> 1; k++)
358 smu[(i + 1) * num + k] ^= smu[i * num + k];
359 }
360
361 /* End Computing Sigma (Mu+1) and L(mu) */
362 /* In either case compute delta */
363 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
364
365 /* Do not compute discrepancy for the last iteration */
366 if (i >= cap)
367 continue;
368
369 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
370 tmp = 2 * (i - 1);
371 if (k == 0) {
372 dmu[i + 1] = si[tmp + 3];
373 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
374 int16_t a, b, c;
375 a = readw(index_of +
376 smu[(i + 1) * num + k]);
377 b = si[2 * (i - 1) + 3 - k];
378 c = readw(index_of + b);
379 tmp = a + c;
380 tmp %= cw_len;
381 dmu[i + 1] = readw(alpha_to + tmp) ^
382 dmu[i + 1];
383 }
384 }
385 }
386}
387
388static int pmecc_err_location(struct mtd_info *mtd)
389{
Scott Wood17fed142016-05-30 13:57:56 -0500390 struct nand_chip *nand_chip = mtd_to_nand(mtd);
391 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000392 const int cap = host->pmecc_corr_cap;
393 const int num = 2 * cap + 1;
394 int sector_size = host->pmecc_sector_size;
395 int err_nbr = 0; /* number of error */
396 int roots_nbr; /* number of roots */
397 int i;
398 uint32_t val;
399 int16_t *smu = host->pmecc_smu;
400 int timeout = PMECC_MAX_TIMEOUT_US;
401
Wu, Joshb31868f2014-06-24 18:18:06 +0800402 pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000403
404 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
Wu, Joshb31868f2014-06-24 18:18:06 +0800405 pmecc_writel(host->pmerrloc, sigma[i],
406 smu[(cap + 1) * num + i]);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000407 err_nbr++;
408 }
409
410 val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
411 if (sector_size == 1024)
412 val |= PMERRLOC_ELCFG_SECTOR_1024;
413
Wu, Joshb31868f2014-06-24 18:18:06 +0800414 pmecc_writel(host->pmerrloc, elcfg, val);
415 pmecc_writel(host->pmerrloc, elen,
416 sector_size * 8 + host->pmecc_degree * cap);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000417
418 while (--timeout) {
Wu, Joshb31868f2014-06-24 18:18:06 +0800419 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
Wu, Joshfd3091d2012-08-23 00:05:36 +0000420 break;
Stefan Roese80877fa2022-09-02 14:10:46 +0200421 schedule();
Wu, Joshfd3091d2012-08-23 00:05:36 +0000422 udelay(1);
423 }
424
425 if (!timeout) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400426 dev_err(mtd->dev,
427 "Timeout to calculate PMECC error location\n");
Wu, Joshfd3091d2012-08-23 00:05:36 +0000428 return -1;
429 }
430
Wu, Joshb31868f2014-06-24 18:18:06 +0800431 roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
Wu, Joshfd3091d2012-08-23 00:05:36 +0000432 >> 8;
433 /* Number of roots == degree of smu hence <= cap */
434 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
435 return err_nbr - 1;
436
437 /* Number of roots does not match the degree of smu
438 * unable to correct error */
439 return -1;
440}
441
442static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
443 int sector_num, int extra_bytes, int err_nbr)
444{
Scott Wood17fed142016-05-30 13:57:56 -0500445 struct nand_chip *nand_chip = mtd_to_nand(mtd);
446 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000447 int i = 0;
448 int byte_pos, bit_pos, sector_size, pos;
449 uint32_t tmp;
450 uint8_t err_byte;
451
452 sector_size = host->pmecc_sector_size;
453
454 while (err_nbr) {
Wu, Joshb31868f2014-06-24 18:18:06 +0800455 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000456 byte_pos = tmp / 8;
457 bit_pos = tmp % 8;
458
459 if (byte_pos >= (sector_size + extra_bytes))
460 BUG(); /* should never happen */
461
462 if (byte_pos < sector_size) {
463 err_byte = *(buf + byte_pos);
464 *(buf + byte_pos) ^= (1 << bit_pos);
465
466 pos = sector_num * host->pmecc_sector_size + byte_pos;
Sean Andersondfff1c12020-09-15 10:44:49 -0400467 dev_dbg(mtd->dev,
468 "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
Wu, Joshfd3091d2012-08-23 00:05:36 +0000469 pos, bit_pos, err_byte, *(buf + byte_pos));
470 } else {
471 /* Bit flip in OOB area */
472 tmp = sector_num * host->pmecc_bytes_per_sector
473 + (byte_pos - sector_size);
474 err_byte = ecc[tmp];
475 ecc[tmp] ^= (1 << bit_pos);
476
477 pos = tmp + nand_chip->ecc.layout->eccpos[0];
Sean Andersondfff1c12020-09-15 10:44:49 -0400478 dev_dbg(mtd->dev,
479 "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
Wu, Joshfd3091d2012-08-23 00:05:36 +0000480 pos, bit_pos, err_byte, ecc[tmp]);
481 }
482
483 i++;
484 err_nbr--;
485 }
486
487 return;
488}
489
490static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
491 u8 *ecc)
492{
Scott Wood17fed142016-05-30 13:57:56 -0500493 struct nand_chip *nand_chip = mtd_to_nand(mtd);
494 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Kai Stuhlemmer (ebee Engineering)bd4d5992021-05-21 11:52:06 +0300495 int i, err_nbr;
496 u8 *buf_pos, *ecc_pos;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000497
Wu, Joshfd3091d2012-08-23 00:05:36 +0000498 for (i = 0; i < host->pmecc_sector_number; i++) {
499 err_nbr = 0;
500 if (pmecc_stat & 0x1) {
501 buf_pos = buf + i * host->pmecc_sector_size;
502
503 pmecc_gen_syndrome(mtd, i);
504 pmecc_substitute(mtd);
505 pmecc_get_sigma(mtd);
506
507 err_nbr = pmecc_err_location(mtd);
Kai Stuhlemmer (ebee Engineering)bd4d5992021-05-21 11:52:06 +0300508 if (err_nbr >= 0) {
509 pmecc_correct_data(mtd, buf_pos, ecc, i,
510 host->pmecc_bytes_per_sector,
511 err_nbr);
512 } else if (host->pmecc_version < PMECC_VERSION_SAMA5D4) {
513 ecc_pos = ecc + i * host->pmecc_bytes_per_sector;
514
515 err_nbr = nand_check_erased_ecc_chunk(
516 buf_pos, host->pmecc_sector_size,
517 ecc_pos, host->pmecc_bytes_per_sector,
518 NULL, 0, host->pmecc_corr_cap);
519 }
520
521 if (err_nbr < 0) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400522 dev_err(mtd->dev, "PMECC: Too many errors\n");
Wu, Joshfd3091d2012-08-23 00:05:36 +0000523 mtd->ecc_stats.failed++;
Scott Wood52ab7ce2016-05-30 13:57:58 -0500524 return -EBADMSG;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000525 }
Kai Stuhlemmer (ebee Engineering)bd4d5992021-05-21 11:52:06 +0300526
527 mtd->ecc_stats.corrected += err_nbr;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000528 }
529 pmecc_stat >>= 1;
530 }
531
532 return 0;
533}
534
535static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
Sergey Lapin3a38a552013-01-14 03:46:50 +0000536 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
Wu, Joshfd3091d2012-08-23 00:05:36 +0000537{
Scott Wood17fed142016-05-30 13:57:56 -0500538 struct atmel_nand_host *host = nand_get_controller_data(chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000539 int eccsize = chip->ecc.size;
540 uint8_t *oob = chip->oob_poi;
541 uint32_t *eccpos = chip->ecc.layout->eccpos;
542 uint32_t stat;
543 int timeout = PMECC_MAX_TIMEOUT_US;
544
545 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
546 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
547 pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
548 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
549
550 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
551 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
552
553 chip->read_buf(mtd, buf, eccsize);
554 chip->read_buf(mtd, oob, mtd->oobsize);
555
556 while (--timeout) {
557 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
558 break;
Stefan Roese80877fa2022-09-02 14:10:46 +0200559 schedule();
Wu, Joshfd3091d2012-08-23 00:05:36 +0000560 udelay(1);
561 }
562
563 if (!timeout) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400564 dev_err(mtd->dev, "Timeout to read PMECC page\n");
Wu, Joshfd3091d2012-08-23 00:05:36 +0000565 return -1;
566 }
567
568 stat = pmecc_readl(host->pmecc, isr);
569 if (stat != 0)
570 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
Scott Wood52ab7ce2016-05-30 13:57:58 -0500571 return -EBADMSG;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000572
573 return 0;
574}
575
Sergey Lapin3a38a552013-01-14 03:46:50 +0000576static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
577 struct nand_chip *chip, const uint8_t *buf,
Scott Wood46e13102016-05-30 13:57:57 -0500578 int oob_required, int page)
Wu, Joshfd3091d2012-08-23 00:05:36 +0000579{
Scott Wood17fed142016-05-30 13:57:56 -0500580 struct atmel_nand_host *host = nand_get_controller_data(chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000581 uint32_t *eccpos = chip->ecc.layout->eccpos;
582 int i, j;
583 int timeout = PMECC_MAX_TIMEOUT_US;
584
585 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
586 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
587
588 pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
589 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
590
591 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
592 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
593
594 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
595
596 while (--timeout) {
597 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
598 break;
Stefan Roese80877fa2022-09-02 14:10:46 +0200599 schedule();
Wu, Joshfd3091d2012-08-23 00:05:36 +0000600 udelay(1);
601 }
602
603 if (!timeout) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400604 dev_err(mtd->dev,
605 "Timeout to read PMECC status, fail to write PMECC in oob\n");
Sergey Lapin3a38a552013-01-14 03:46:50 +0000606 goto out;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000607 }
608
609 for (i = 0; i < host->pmecc_sector_number; i++) {
610 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
611 int pos;
612
613 pos = i * host->pmecc_bytes_per_sector + j;
614 chip->oob_poi[eccpos[pos]] =
Wu, Joshb31868f2014-06-24 18:18:06 +0800615 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000616 }
617 }
618 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
Sergey Lapin3a38a552013-01-14 03:46:50 +0000619out:
620 return 0;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000621}
622
623static void atmel_pmecc_core_init(struct mtd_info *mtd)
624{
Scott Wood17fed142016-05-30 13:57:56 -0500625 struct nand_chip *nand_chip = mtd_to_nand(mtd);
626 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000627 uint32_t val = 0;
628 struct nand_ecclayout *ecc_layout;
629
630 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
631 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
632
633 switch (host->pmecc_corr_cap) {
634 case 2:
635 val = PMECC_CFG_BCH_ERR2;
636 break;
637 case 4:
638 val = PMECC_CFG_BCH_ERR4;
639 break;
640 case 8:
641 val = PMECC_CFG_BCH_ERR8;
642 break;
643 case 12:
644 val = PMECC_CFG_BCH_ERR12;
645 break;
646 case 24:
647 val = PMECC_CFG_BCH_ERR24;
648 break;
Josh Wuce764952015-11-24 16:34:01 +0800649 case 32:
650 val = PMECC_CFG_BCH_ERR32;
651 break;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000652 }
653
654 if (host->pmecc_sector_size == 512)
655 val |= PMECC_CFG_SECTOR512;
656 else if (host->pmecc_sector_size == 1024)
657 val |= PMECC_CFG_SECTOR1024;
658
659 switch (host->pmecc_sector_number) {
660 case 1:
661 val |= PMECC_CFG_PAGE_1SECTOR;
662 break;
663 case 2:
664 val |= PMECC_CFG_PAGE_2SECTORS;
665 break;
666 case 4:
667 val |= PMECC_CFG_PAGE_4SECTORS;
668 break;
669 case 8:
670 val |= PMECC_CFG_PAGE_8SECTORS;
671 break;
672 }
673
674 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
675 | PMECC_CFG_AUTO_DISABLE);
676 pmecc_writel(host->pmecc, cfg, val);
677
678 ecc_layout = nand_chip->ecc.layout;
679 pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
680 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
681 pmecc_writel(host->pmecc, eaddr,
682 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
683 /* See datasheet about PMECC Clock Control Register */
684 pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
685 pmecc_writel(host->pmecc, idr, 0xff);
686 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
687}
688
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800689#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
690/*
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800691 * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
692 * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
693 * ONFI ECC parameters.
694 * @host: point to an atmel_nand_host structure.
695 * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
696 * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
697 * @chip: point to an nand_chip structure.
698 * @cap: store the ONFI ECC correct bits capbility
699 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
700 *
701 * Return 0 if success. otherwise return the error code.
702 */
703static int pmecc_choose_ecc(struct atmel_nand_host *host,
704 struct nand_chip *chip,
705 int *cap, int *sector_size)
706{
707 /* Get ECC requirement from ONFI parameters */
708 *cap = *sector_size = 0;
709 if (chip->onfi_version) {
Josh Wuc90cc682016-01-25 14:06:33 +0800710 *cap = chip->ecc_strength_ds;
711 *sector_size = chip->ecc_step_ds;
Masahiro Yamadaf8a5d512017-10-18 00:10:48 +0900712 pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
Josh Wuc90cc682016-01-25 14:06:33 +0800713 *cap, *sector_size);
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800714 }
Josh Wuc90cc682016-01-25 14:06:33 +0800715
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800716 if (*cap == 0 && *sector_size == 0) {
Josh Wuc90cc682016-01-25 14:06:33 +0800717 /* Non-ONFI compliant */
Sean Andersondfff1c12020-09-15 10:44:49 -0400718 dev_info(chip->mtd.dev,
719 "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800720 *cap = 2;
721 *sector_size = 512;
722 }
723
724 /* If head file doesn't specify then use the one in ONFI parameters */
725 if (host->pmecc_corr_cap == 0) {
726 /* use the most fitable ecc bits (the near bigger one ) */
727 if (*cap <= 2)
728 host->pmecc_corr_cap = 2;
729 else if (*cap <= 4)
730 host->pmecc_corr_cap = 4;
731 else if (*cap <= 8)
732 host->pmecc_corr_cap = 8;
733 else if (*cap <= 12)
734 host->pmecc_corr_cap = 12;
735 else if (*cap <= 24)
736 host->pmecc_corr_cap = 24;
737 else
Josh Wuce764952015-11-24 16:34:01 +0800738#ifdef CONFIG_SAMA5D2
739 host->pmecc_corr_cap = 32;
740#else
741 host->pmecc_corr_cap = 24;
742#endif
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800743 }
744 if (host->pmecc_sector_size == 0) {
745 /* use the most fitable sector size (the near smaller one ) */
746 if (*sector_size >= 1024)
747 host->pmecc_sector_size = 1024;
748 else if (*sector_size >= 512)
749 host->pmecc_sector_size = 512;
750 else
751 return -EINVAL;
752 }
753 return 0;
754}
755#endif
756
Josh Wuf259ad22014-11-10 15:24:00 +0800757#if defined(NO_GALOIS_TABLE_IN_ROM)
758static uint16_t *pmecc_galois_table;
759static inline int deg(unsigned int poly)
760{
761 /* polynomial degree is the most-significant bit index */
762 return fls(poly) - 1;
763}
764
765static int build_gf_tables(int mm, unsigned int poly,
766 int16_t *index_of, int16_t *alpha_to)
767{
768 unsigned int i, x = 1;
769 const unsigned int k = 1 << deg(poly);
770 unsigned int nn = (1 << mm) - 1;
771
772 /* primitive polynomial must be of degree m */
773 if (k != (1u << mm))
774 return -EINVAL;
775
776 for (i = 0; i < nn; i++) {
777 alpha_to[i] = x;
778 index_of[x] = i;
779 if (i && (x == 1))
780 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
781 return -EINVAL;
782 x <<= 1;
783 if (x & k)
784 x ^= poly;
785 }
786
787 alpha_to[nn] = 1;
788 index_of[0] = 0;
789
790 return 0;
791}
792
793static uint16_t *create_lookup_table(int sector_size)
794{
795 int degree = (sector_size == 512) ?
796 PMECC_GF_DIMENSION_13 :
797 PMECC_GF_DIMENSION_14;
798 unsigned int poly = (sector_size == 512) ?
799 PMECC_GF_13_PRIMITIVE_POLY :
800 PMECC_GF_14_PRIMITIVE_POLY;
801 int table_size = (sector_size == 512) ?
802 PMECC_INDEX_TABLE_SIZE_512 :
803 PMECC_INDEX_TABLE_SIZE_1024;
804
805 int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
806 if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
807 return NULL;
808
809 return (uint16_t *)addr;
810}
811#endif
812
Wu, Joshfd3091d2012-08-23 00:05:36 +0000813static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
814 struct mtd_info *mtd)
815{
816 struct atmel_nand_host *host;
817 int cap, sector_size;
818
Scott Wood17fed142016-05-30 13:57:56 -0500819 host = &pmecc_host;
820 nand_set_controller_data(nand, host);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000821
822 nand->ecc.mode = NAND_ECC_HW;
823 nand->ecc.calculate = NULL;
824 nand->ecc.correct = NULL;
825 nand->ecc.hwctl = NULL;
826
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800827#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
828 host->pmecc_corr_cap = host->pmecc_sector_size = 0;
829
830#ifdef CONFIG_PMECC_CAP
831 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
832#endif
833#ifdef CONFIG_PMECC_SECTOR_SIZE
834 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
835#endif
836 /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
837 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
838 * from ONFI.
839 */
840 if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400841 dev_err(mtd->dev,
842 "Required ECC %d bits in %d bytes not supported!\n",
Josh Wudaf40882016-01-25 14:06:34 +0800843 cap, sector_size);
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800844 return -EINVAL;
845 }
846
847 if (cap > host->pmecc_corr_cap)
Sean Andersondfff1c12020-09-15 10:44:49 -0400848 dev_info(mtd->dev,
849 "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
850 host->pmecc_corr_cap, cap);
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800851 if (sector_size < host->pmecc_sector_size)
Sean Andersondfff1c12020-09-15 10:44:49 -0400852 dev_info(mtd->dev,
853 "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
854 host->pmecc_sector_size, sector_size);
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800855#else /* CONFIG_SYS_NAND_ONFI_DETECTION */
856 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
857 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
858#endif
859
860 cap = host->pmecc_corr_cap;
861 sector_size = host->pmecc_sector_size;
862
863 /* TODO: need check whether cap & sector_size is validate */
Josh Wuf259ad22014-11-10 15:24:00 +0800864#if defined(NO_GALOIS_TABLE_IN_ROM)
865 /*
866 * As pmecc_rom_base is the begin of the gallois field table, So the
867 * index offset just set as 0.
868 */
869 host->pmecc_index_table_offset = 0;
870#else
Wu, Joshb45c9492013-07-03 11:11:45 +0800871 if (host->pmecc_sector_size == 512)
872 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
873 else
874 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
Josh Wuf259ad22014-11-10 15:24:00 +0800875#endif
Wu, Joshfd3091d2012-08-23 00:05:36 +0000876
Masahiro Yamadaf8a5d512017-10-18 00:10:48 +0900877 pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
878 cap, sector_size);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000879
880 host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
881 host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
882 ATMEL_BASE_PMERRLOC;
Josh Wuf259ad22014-11-10 15:24:00 +0800883#if defined(NO_GALOIS_TABLE_IN_ROM)
884 pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
885 if (!pmecc_galois_table) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400886 dev_err(mtd->dev, "out of memory\n");
Josh Wuf259ad22014-11-10 15:24:00 +0800887 return -ENOMEM;
888 }
889
890 host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
891#else
Wu, Joshfd3091d2012-08-23 00:05:36 +0000892 host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
Josh Wuf259ad22014-11-10 15:24:00 +0800893#endif
Wu, Joshfd3091d2012-08-23 00:05:36 +0000894
895 /* ECC is calculated for the whole page (1 step) */
896 nand->ecc.size = mtd->writesize;
897
898 /* set ECC page size and oob layout */
899 switch (mtd->writesize) {
900 case 2048:
901 case 4096:
Wu, Joshf9f69b12013-10-18 17:46:31 +0800902 case 8192:
Wu, Josh89bdc8e2013-08-23 15:09:05 +0800903 host->pmecc_degree = (sector_size == 512) ?
904 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000905 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
906 host->pmecc_sector_number = mtd->writesize / sector_size;
907 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
908 cap, sector_size);
909 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
910 host->pmecc_index_of = host->pmecc_rom_base +
911 host->pmecc_index_table_offset;
912
913 nand->ecc.steps = 1;
914 nand->ecc.bytes = host->pmecc_bytes_per_sector *
915 host->pmecc_sector_number;
Wu, Joshf9f69b12013-10-18 17:46:31 +0800916
917 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400918 dev_err(mtd->dev,
919 "too large eccpos entries. max support ecc.bytes is %d\n",
920 MTD_MAX_ECCPOS_ENTRIES_LARGE);
Wu, Joshf9f69b12013-10-18 17:46:31 +0800921 return -EINVAL;
922 }
923
Josh Wu5d3256c2016-01-25 14:06:35 +0800924 if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400925 dev_err(mtd->dev, "No room for ECC bytes\n");
Wu, Joshfd3091d2012-08-23 00:05:36 +0000926 return -EINVAL;
927 }
928 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
929 mtd->oobsize,
930 nand->ecc.bytes);
931 nand->ecc.layout = &atmel_pmecc_oobinfo;
932 break;
933 case 512:
934 case 1024:
935 /* TODO */
Sean Andersondfff1c12020-09-15 10:44:49 -0400936 dev_err(mtd->dev,
937 "Unsupported page size for PMECC, use Software ECC\n");
Wu, Joshfd3091d2012-08-23 00:05:36 +0000938 default:
939 /* page size not handled by HW ECC */
940 /* switching back to soft ECC */
941 nand->ecc.mode = NAND_ECC_SOFT;
942 nand->ecc.read_page = NULL;
943 nand->ecc.postpad = 0;
944 nand->ecc.prepad = 0;
945 nand->ecc.bytes = 0;
946 return 0;
947 }
948
Wu, Josh4e87b3152013-07-03 11:11:48 +0800949 /* Allocate data for PMECC computation */
950 if (pmecc_data_alloc(host)) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400951 dev_err(mtd->dev,
952 "Cannot allocate memory for PMECC computation!\n");
Wu, Josh4e87b3152013-07-03 11:11:48 +0800953 return -ENOMEM;
954 }
955
Boris BREZILLONd7915f42014-09-02 10:23:09 +0200956 nand->options |= NAND_NO_SUBPAGE_WRITE;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000957 nand->ecc.read_page = atmel_nand_pmecc_read_page;
958 nand->ecc.write_page = atmel_nand_pmecc_write_page;
Sergey Lapin3a38a552013-01-14 03:46:50 +0000959 nand->ecc.strength = cap;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000960
Wu, Josh1f5c0892015-01-16 11:54:46 +0800961 /* Check the PMECC ip version */
962 host->pmecc_version = pmecc_readl(host->pmerrloc, version);
Sean Andersondfff1c12020-09-15 10:44:49 -0400963 dev_dbg(mtd->dev, "PMECC IP version is: %x\n", host->pmecc_version);
Wu, Josh1f5c0892015-01-16 11:54:46 +0800964
Wu, Joshfd3091d2012-08-23 00:05:36 +0000965 atmel_pmecc_core_init(mtd);
966
967 return 0;
968}
969
970#else
971
Nikolay Petukhove6015ca2010-03-19 10:49:27 +0500972/* oob layout for large page size
973 * bad block info is on bytes 0 and 1
974 * the bytes have to be consecutives to avoid
975 * several NAND_CMD_RNDOUT during read
976 */
977static struct nand_ecclayout atmel_oobinfo_large = {
978 .eccbytes = 4,
979 .eccpos = {60, 61, 62, 63},
980 .oobfree = {
981 {2, 58}
982 },
983};
984
985/* oob layout for small page size
986 * bad block info is on bytes 4 and 5
987 * the bytes have to be consecutives to avoid
988 * several NAND_CMD_RNDOUT during read
989 */
990static struct nand_ecclayout atmel_oobinfo_small = {
991 .eccbytes = 4,
992 .eccpos = {0, 1, 2, 3},
993 .oobfree = {
994 {6, 10}
995 },
996};
997
998/*
999 * Calculate HW ECC
1000 *
1001 * function called after a write
1002 *
1003 * mtd: MTD block structure
1004 * dat: raw data (unused)
1005 * ecc_code: buffer for ECC
1006 */
1007static int atmel_nand_calculate(struct mtd_info *mtd,
1008 const u_char *dat, unsigned char *ecc_code)
1009{
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001010 unsigned int ecc_value;
1011
1012 /* get the first 2 ECC bytes */
Tom Riniddaaf072022-11-12 17:36:46 -05001013 ecc_value = ecc_readl(ATMEL_BASE_ECC, PR);
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001014
1015 ecc_code[0] = ecc_value & 0xFF;
1016 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1017
1018 /* get the last 2 ECC bytes */
Tom Riniddaaf072022-11-12 17:36:46 -05001019 ecc_value = ecc_readl(ATMEL_BASE_ECC, NPR) & ATMEL_ECC_NPARITY;
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001020
1021 ecc_code[2] = ecc_value & 0xFF;
1022 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1023
1024 return 0;
1025}
1026
1027/*
1028 * HW ECC read page function
1029 *
1030 * mtd: mtd info structure
1031 * chip: nand chip info structure
1032 * buf: buffer to store read data
Sergey Lapin3a38a552013-01-14 03:46:50 +00001033 * oob_required: caller expects OOB data read to chip->oob_poi
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001034 */
Sergey Lapin3a38a552013-01-14 03:46:50 +00001035static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1036 uint8_t *buf, int oob_required, int page)
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001037{
1038 int eccsize = chip->ecc.size;
1039 int eccbytes = chip->ecc.bytes;
1040 uint32_t *eccpos = chip->ecc.layout->eccpos;
1041 uint8_t *p = buf;
1042 uint8_t *oob = chip->oob_poi;
1043 uint8_t *ecc_pos;
1044 int stat;
1045
1046 /* read the page */
1047 chip->read_buf(mtd, p, eccsize);
1048
1049 /* move to ECC position if needed */
1050 if (eccpos[0] != 0) {
1051 /* This only works on large pages
1052 * because the ECC controller waits for
1053 * NAND_CMD_RNDOUTSTART after the
1054 * NAND_CMD_RNDOUT.
1055 * anyway, for small pages, the eccpos[0] == 0
1056 */
1057 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1058 mtd->writesize + eccpos[0], -1);
1059 }
1060
1061 /* the ECC controller needs to read the ECC just after the data */
1062 ecc_pos = oob + eccpos[0];
1063 chip->read_buf(mtd, ecc_pos, eccbytes);
1064
1065 /* check if there's an error */
1066 stat = chip->ecc.correct(mtd, p, oob, NULL);
1067
1068 if (stat < 0)
1069 mtd->ecc_stats.failed++;
1070 else
1071 mtd->ecc_stats.corrected += stat;
1072
1073 /* get back to oob start (end of page) */
1074 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1075
1076 /* read the oob */
1077 chip->read_buf(mtd, oob, mtd->oobsize);
1078
1079 return 0;
1080}
1081
1082/*
1083 * HW ECC Correction
1084 *
1085 * function called after a read
1086 *
1087 * mtd: MTD block structure
1088 * dat: raw data read from the chip
1089 * read_ecc: ECC from the chip (unused)
1090 * isnull: unused
1091 *
1092 * Detect and correct a 1 bit error for a page
1093 */
1094static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1095 u_char *read_ecc, u_char *isnull)
1096{
Scott Wood17fed142016-05-30 13:57:56 -05001097 struct nand_chip *nand_chip = mtd_to_nand(mtd);
Wu, Josh1586d1b2012-08-23 00:05:35 +00001098 unsigned int ecc_status;
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001099 unsigned int ecc_word, ecc_bit;
1100
1101 /* get the status from the Status Register */
Tom Riniddaaf072022-11-12 17:36:46 -05001102 ecc_status = ecc_readl(ATMEL_BASE_ECC, SR);
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001103
1104 /* if there's no error */
1105 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1106 return 0;
1107
1108 /* get error bit offset (4 bits) */
Tom Riniddaaf072022-11-12 17:36:46 -05001109 ecc_bit = ecc_readl(ATMEL_BASE_ECC, PR) & ATMEL_ECC_BITADDR;
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001110 /* get word address (12 bits) */
Tom Riniddaaf072022-11-12 17:36:46 -05001111 ecc_word = ecc_readl(ATMEL_BASE_ECC, PR) & ATMEL_ECC_WORDADDR;
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001112 ecc_word >>= 4;
1113
1114 /* if there are multiple errors */
1115 if (ecc_status & ATMEL_ECC_MULERR) {
1116 /* check if it is a freshly erased block
1117 * (filled with 0xff) */
1118 if ((ecc_bit == ATMEL_ECC_BITADDR)
1119 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1120 /* the block has just been erased, return OK */
1121 return 0;
1122 }
1123 /* it doesn't seems to be a freshly
1124 * erased block.
1125 * We can't correct so many errors */
Sean Andersondfff1c12020-09-15 10:44:49 -04001126 dev_warn(mtd->dev,
1127 "multiple errors detected. Unable to correct.\n");
Scott Wood52ab7ce2016-05-30 13:57:58 -05001128 return -EBADMSG;
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001129 }
1130
1131 /* if there's a single bit error : we can correct it */
1132 if (ecc_status & ATMEL_ECC_ECCERR) {
1133 /* there's nothing much to do here.
1134 * the bit error is on the ECC itself.
1135 */
Sean Andersondfff1c12020-09-15 10:44:49 -04001136 dev_warn(mtd->dev,
1137 "one bit error on ECC code. Nothing to correct\n");
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001138 return 0;
1139 }
1140
Sean Andersondfff1c12020-09-15 10:44:49 -04001141 dev_warn(mtd->dev,
1142 "one bit error on data. (word offset in the page : 0x%x bit offset : 0x%x)\n",
1143 ecc_word, ecc_bit);
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001144 /* correct the error */
1145 if (nand_chip->options & NAND_BUSWIDTH_16) {
1146 /* 16 bits words */
1147 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1148 } else {
1149 /* 8 bits words */
1150 dat[ecc_word] ^= (1 << ecc_bit);
1151 }
Sean Andersondfff1c12020-09-15 10:44:49 -04001152 dev_warn(mtd->dev, "error corrected\n");
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001153 return 1;
1154}
1155
1156/*
1157 * Enable HW ECC : unused on most chips
1158 */
1159static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1160{
1161}
Wu, Josh6cded6d2012-08-23 00:05:34 +00001162
1163int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1164{
1165 nand->ecc.mode = NAND_ECC_HW;
1166 nand->ecc.calculate = atmel_nand_calculate;
1167 nand->ecc.correct = atmel_nand_correct;
1168 nand->ecc.hwctl = atmel_nand_hwctl;
1169 nand->ecc.read_page = atmel_nand_read_page;
1170 nand->ecc.bytes = 4;
Andre Renaudeaf23212016-05-05 07:28:15 -06001171 nand->ecc.strength = 4;
Wu, Josh6cded6d2012-08-23 00:05:34 +00001172
1173 if (nand->ecc.mode == NAND_ECC_HW) {
1174 /* ECC is calculated for the whole page (1 step) */
1175 nand->ecc.size = mtd->writesize;
1176
1177 /* set ECC page size and oob layout */
1178 switch (mtd->writesize) {
1179 case 512:
1180 nand->ecc.layout = &atmel_oobinfo_small;
Tom Riniddaaf072022-11-12 17:36:46 -05001181 ecc_writel(ATMEL_BASE_ECC, MR,
Wu, Josh6cded6d2012-08-23 00:05:34 +00001182 ATMEL_ECC_PAGESIZE_528);
1183 break;
1184 case 1024:
1185 nand->ecc.layout = &atmel_oobinfo_large;
Tom Riniddaaf072022-11-12 17:36:46 -05001186 ecc_writel(ATMEL_BASE_ECC, MR,
Wu, Josh6cded6d2012-08-23 00:05:34 +00001187 ATMEL_ECC_PAGESIZE_1056);
1188 break;
1189 case 2048:
1190 nand->ecc.layout = &atmel_oobinfo_large;
Tom Riniddaaf072022-11-12 17:36:46 -05001191 ecc_writel(ATMEL_BASE_ECC, MR,
Wu, Josh6cded6d2012-08-23 00:05:34 +00001192 ATMEL_ECC_PAGESIZE_2112);
1193 break;
1194 case 4096:
1195 nand->ecc.layout = &atmel_oobinfo_large;
Tom Riniddaaf072022-11-12 17:36:46 -05001196 ecc_writel(ATMEL_BASE_ECC, MR,
Wu, Josh6cded6d2012-08-23 00:05:34 +00001197 ATMEL_ECC_PAGESIZE_4224);
1198 break;
1199 default:
1200 /* page size not handled by HW ECC */
1201 /* switching back to soft ECC */
1202 nand->ecc.mode = NAND_ECC_SOFT;
1203 nand->ecc.calculate = NULL;
1204 nand->ecc.correct = NULL;
1205 nand->ecc.hwctl = NULL;
1206 nand->ecc.read_page = NULL;
1207 nand->ecc.postpad = 0;
1208 nand->ecc.prepad = 0;
1209 nand->ecc.bytes = 0;
1210 break;
1211 }
1212 }
1213
1214 return 0;
1215}
1216
Wu, Joshfd3091d2012-08-23 00:05:36 +00001217#endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1218
1219#endif /* CONFIG_ATMEL_NAND_HWECC */
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001220
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +01001221static void at91_nand_hwcontrol(struct mtd_info *mtd,
Sergey Lapin77e524c2008-10-31 12:28:43 +01001222 int cmd, unsigned int ctrl)
1223{
Scott Wood17fed142016-05-30 13:57:56 -05001224 struct nand_chip *this = mtd_to_nand(mtd);
Sergey Lapin77e524c2008-10-31 12:28:43 +01001225
1226 if (ctrl & NAND_CTRL_CHANGE) {
1227 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
Tom Rinib4213492022-11-12 17:36:51 -05001228 IO_ADDR_W &= ~(CFG_SYS_NAND_MASK_ALE
1229 | CFG_SYS_NAND_MASK_CLE);
Sergey Lapin77e524c2008-10-31 12:28:43 +01001230
1231 if (ctrl & NAND_CLE)
Tom Rinib4213492022-11-12 17:36:51 -05001232 IO_ADDR_W |= CFG_SYS_NAND_MASK_CLE;
Sergey Lapin77e524c2008-10-31 12:28:43 +01001233 if (ctrl & NAND_ALE)
Tom Rinib4213492022-11-12 17:36:51 -05001234 IO_ADDR_W |= CFG_SYS_NAND_MASK_ALE;
Sergey Lapin77e524c2008-10-31 12:28:43 +01001235
Tom Rinib4213492022-11-12 17:36:51 -05001236#ifdef CFG_SYS_NAND_ENABLE_PIN
1237 at91_set_gpio_value(CFG_SYS_NAND_ENABLE_PIN,
Wenyou Yangd4aab6b2017-03-23 12:55:21 +08001238 !(ctrl & NAND_NCE));
michael4b5cef72011-03-14 21:16:38 +00001239#endif
Sergey Lapin77e524c2008-10-31 12:28:43 +01001240 this->IO_ADDR_W = (void *) IO_ADDR_W;
1241 }
1242
1243 if (cmd != NAND_CMD_NONE)
1244 writeb(cmd, this->IO_ADDR_W);
1245}
1246
Tom Rinib4213492022-11-12 17:36:51 -05001247#ifdef CFG_SYS_NAND_READY_PIN
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +01001248static int at91_nand_ready(struct mtd_info *mtd)
Sergey Lapin77e524c2008-10-31 12:28:43 +01001249{
Tom Rinib4213492022-11-12 17:36:51 -05001250 return at91_get_gpio_value(CFG_SYS_NAND_READY_PIN);
Sergey Lapin77e524c2008-10-31 12:28:43 +01001251}
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +01001252#endif
Sergey Lapin77e524c2008-10-31 12:28:43 +01001253
Bo Shen9415b872014-03-03 14:47:16 +08001254#ifdef CONFIG_SPL_BUILD
1255/* The following code is for SPL */
Scott Wood2c1b7e12016-05-30 13:57:55 -05001256static struct mtd_info *mtd;
Bo Shen9415b872014-03-03 14:47:16 +08001257static struct nand_chip nand_chip;
1258
1259static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1260{
Scott Wood17fed142016-05-30 13:57:56 -05001261 struct nand_chip *this = mtd_to_nand(mtd);
Sean Anderson11a4c702023-11-04 16:37:41 -04001262 int page_addr = page + block * SYS_NAND_BLOCK_PAGES;
Bo Shen9415b872014-03-03 14:47:16 +08001263 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1264 unsigned int ctrl) = this->cmd_ctrl;
1265
Scott Wood2c1b7e12016-05-30 13:57:55 -05001266 while (!this->dev_ready(mtd))
Bo Shen9415b872014-03-03 14:47:16 +08001267 ;
1268
1269 if (cmd == NAND_CMD_READOOB) {
1270 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1271 cmd = NAND_CMD_READ0;
1272 }
1273
Scott Wood2c1b7e12016-05-30 13:57:55 -05001274 hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
Bo Shen9415b872014-03-03 14:47:16 +08001275
Brian Norris67675222014-05-06 00:46:17 +05301276 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
Bo Shen9415b872014-03-03 14:47:16 +08001277 offs >>= 1;
1278
Scott Wood2c1b7e12016-05-30 13:57:55 -05001279 hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1280 hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1281 hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1282 hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
Bo Shen9415b872014-03-03 14:47:16 +08001283#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
Scott Wood2c1b7e12016-05-30 13:57:55 -05001284 hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
Bo Shen9415b872014-03-03 14:47:16 +08001285#endif
Scott Wood2c1b7e12016-05-30 13:57:55 -05001286 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
Bo Shen9415b872014-03-03 14:47:16 +08001287
Scott Wood2c1b7e12016-05-30 13:57:55 -05001288 hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1289 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
Bo Shen9415b872014-03-03 14:47:16 +08001290
Scott Wood2c1b7e12016-05-30 13:57:55 -05001291 while (!this->dev_ready(mtd))
Bo Shen9415b872014-03-03 14:47:16 +08001292 ;
1293
1294 return 0;
1295}
1296
1297static int nand_is_bad_block(int block)
1298{
Scott Wood17fed142016-05-30 13:57:56 -05001299 struct nand_chip *this = mtd_to_nand(mtd);
Bo Shen9415b872014-03-03 14:47:16 +08001300
1301 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1302
1303 if (this->options & NAND_BUSWIDTH_16) {
1304 if (readw(this->IO_ADDR_R) != 0xffff)
1305 return 1;
1306 } else {
1307 if (readb(this->IO_ADDR_R) != 0xff)
1308 return 1;
1309 }
1310
1311 return 0;
1312}
1313
1314#ifdef CONFIG_SPL_NAND_ECC
Tom Rinib4213492022-11-12 17:36:51 -05001315static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
Bo Shen9415b872014-03-03 14:47:16 +08001316#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
Tom Rinib4213492022-11-12 17:36:51 -05001317 CFG_SYS_NAND_ECCSIZE)
1318#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
Bo Shen9415b872014-03-03 14:47:16 +08001319
1320static int nand_read_page(int block, int page, void *dst)
1321{
Scott Wood17fed142016-05-30 13:57:56 -05001322 struct nand_chip *this = mtd_to_nand(mtd);
Bo Shen9415b872014-03-03 14:47:16 +08001323 u_char ecc_calc[ECCTOTAL];
1324 u_char ecc_code[ECCTOTAL];
1325 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
Tom Rinib4213492022-11-12 17:36:51 -05001326 int eccsize = CFG_SYS_NAND_ECCSIZE;
1327 int eccbytes = CFG_SYS_NAND_ECCBYTES;
Bo Shen9415b872014-03-03 14:47:16 +08001328 int eccsteps = ECCSTEPS;
1329 int i;
1330 uint8_t *p = dst;
1331 nand_command(block, page, 0, NAND_CMD_READ0);
1332
1333 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1334 if (this->ecc.mode != NAND_ECC_SOFT)
Scott Wood2c1b7e12016-05-30 13:57:55 -05001335 this->ecc.hwctl(mtd, NAND_ECC_READ);
1336 this->read_buf(mtd, p, eccsize);
1337 this->ecc.calculate(mtd, p, &ecc_calc[i]);
Bo Shen9415b872014-03-03 14:47:16 +08001338 }
Scott Wood2c1b7e12016-05-30 13:57:55 -05001339 this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
Bo Shen9415b872014-03-03 14:47:16 +08001340
1341 for (i = 0; i < ECCTOTAL; i++)
1342 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1343
1344 eccsteps = ECCSTEPS;
1345 p = dst;
1346
1347 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
Scott Wood2c1b7e12016-05-30 13:57:55 -05001348 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
Bo Shen9415b872014-03-03 14:47:16 +08001349
1350 return 0;
1351}
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001352
1353int spl_nand_erase_one(int block, int page)
1354{
Scott Wood17fed142016-05-30 13:57:56 -05001355 struct nand_chip *this = mtd_to_nand(mtd);
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001356 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1357 unsigned int ctrl) = this->cmd_ctrl;
1358 int page_addr;
1359
1360 if (nand_chip.select_chip)
Scott Wood2c1b7e12016-05-30 13:57:55 -05001361 nand_chip.select_chip(mtd, 0);
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001362
Sean Anderson11a4c702023-11-04 16:37:41 -04001363 page_addr = page + block * SYS_NAND_BLOCK_PAGES;
Scott Wood2c1b7e12016-05-30 13:57:55 -05001364 hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001365 /* Row address */
Scott Wood2c1b7e12016-05-30 13:57:55 -05001366 hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1367 hwctrl(mtd, ((page_addr >> 8) & 0xff),
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001368 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1369#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1370 /* One more address cycle for devices > 128MiB */
Scott Wood2c1b7e12016-05-30 13:57:55 -05001371 hwctrl(mtd, (page_addr >> 16) & 0x0f,
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001372 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1373#endif
Scott Wood2c1b7e12016-05-30 13:57:55 -05001374 hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001375
Scott Wood2c1b7e12016-05-30 13:57:55 -05001376 while (!this->dev_ready(mtd))
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001377 ;
1378
1379 nand_deselect();
1380
1381 return 0;
1382}
Bo Shen9415b872014-03-03 14:47:16 +08001383#else
1384static int nand_read_page(int block, int page, void *dst)
1385{
Scott Wood17fed142016-05-30 13:57:56 -05001386 struct nand_chip *this = mtd_to_nand(mtd);
Bo Shen9415b872014-03-03 14:47:16 +08001387
1388 nand_command(block, page, 0, NAND_CMD_READ0);
Scott Wood2c1b7e12016-05-30 13:57:55 -05001389 atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
Bo Shen9415b872014-03-03 14:47:16 +08001390
1391 return 0;
1392}
1393#endif /* CONFIG_SPL_NAND_ECC */
1394
Bo Shen9415b872014-03-03 14:47:16 +08001395int at91_nand_wait_ready(struct mtd_info *mtd)
1396{
Scott Wood17fed142016-05-30 13:57:56 -05001397 struct nand_chip *this = mtd_to_nand(mtd);
Bo Shen9415b872014-03-03 14:47:16 +08001398
1399 udelay(this->chip_delay);
1400
Heiko Schocherae2af0a2014-10-31 08:31:03 +01001401 return 1;
Bo Shen9415b872014-03-03 14:47:16 +08001402}
1403
1404int board_nand_init(struct nand_chip *nand)
1405{
1406 int ret = 0;
1407
1408 nand->ecc.mode = NAND_ECC_SOFT;
1409#ifdef CONFIG_SYS_NAND_DBW_16
1410 nand->options = NAND_BUSWIDTH_16;
1411 nand->read_buf = nand_read_buf16;
1412#else
1413 nand->read_buf = nand_read_buf;
1414#endif
1415 nand->cmd_ctrl = at91_nand_hwcontrol;
Tom Rinib4213492022-11-12 17:36:51 -05001416#ifdef CFG_SYS_NAND_READY_PIN
Bo Shen9415b872014-03-03 14:47:16 +08001417 nand->dev_ready = at91_nand_ready;
1418#else
1419 nand->dev_ready = at91_nand_wait_ready;
1420#endif
1421 nand->chip_delay = 20;
David Dueckab7ec112015-03-20 10:52:49 +01001422#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1423 nand->bbt_options |= NAND_BBT_USE_FLASH;
1424#endif
Bo Shen9415b872014-03-03 14:47:16 +08001425
1426#ifdef CONFIG_ATMEL_NAND_HWECC
1427#ifdef CONFIG_ATMEL_NAND_HW_PMECC
Scott Wood2c1b7e12016-05-30 13:57:55 -05001428 ret = atmel_pmecc_nand_init_params(nand, mtd);
Bo Shen9415b872014-03-03 14:47:16 +08001429#endif
1430#endif
1431
1432 return ret;
1433}
1434
1435void nand_init(void)
1436{
Boris Brezillon3b5f8842016-06-15 20:56:10 +02001437 mtd = nand_to_mtd(&nand_chip);
Scott Wood2c1b7e12016-05-30 13:57:55 -05001438 mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1439 mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
Tom Rinib4213492022-11-12 17:36:51 -05001440 nand_chip.IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
1441 nand_chip.IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
Bo Shen9415b872014-03-03 14:47:16 +08001442 board_nand_init(&nand_chip);
1443
1444#ifdef CONFIG_SPL_NAND_ECC
1445 if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1446 nand_chip.ecc.calculate = nand_calculate_ecc;
1447 nand_chip.ecc.correct = nand_correct_data;
1448 }
1449#endif
1450
1451 if (nand_chip.select_chip)
Scott Wood2c1b7e12016-05-30 13:57:55 -05001452 nand_chip.select_chip(mtd, 0);
Bo Shen9415b872014-03-03 14:47:16 +08001453}
1454
Sean Anderson8805f9d2023-11-04 16:37:44 -04001455unsigned int nand_page_size(void)
1456{
1457 return nand_to_mtd(&nand_chip)->writesize;
1458}
1459
Bo Shen9415b872014-03-03 14:47:16 +08001460void nand_deselect(void)
1461{
1462 if (nand_chip.select_chip)
Scott Wood2c1b7e12016-05-30 13:57:55 -05001463 nand_chip.select_chip(mtd, -1);
Bo Shen9415b872014-03-03 14:47:16 +08001464}
1465
Ladislav Michlc6a42002017-04-16 15:31:59 +02001466#include "nand_spl_loaders.c"
1467
Bo Shen9415b872014-03-03 14:47:16 +08001468#else
1469
Tom Rinib4213492022-11-12 17:36:51 -05001470#ifndef CFG_SYS_NAND_BASE_LIST
1471#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001472#endif
Wu, Josh6cded6d2012-08-23 00:05:34 +00001473static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
Tom Rinib4213492022-11-12 17:36:51 -05001474static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
Wu, Josh6cded6d2012-08-23 00:05:34 +00001475
1476int atmel_nand_chip_init(int devnum, ulong base_addr)
1477{
1478 int ret;
Wu, Josh6cded6d2012-08-23 00:05:34 +00001479 struct nand_chip *nand = &nand_chip[devnum];
Scott Wood17fed142016-05-30 13:57:56 -05001480 struct mtd_info *mtd = nand_to_mtd(nand);
Wu, Josh6cded6d2012-08-23 00:05:34 +00001481
Wu, Josh6cded6d2012-08-23 00:05:34 +00001482 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001483
Bo Shenbb5a12f2013-08-28 14:54:26 +00001484#ifdef CONFIG_NAND_ECC_BCH
1485 nand->ecc.mode = NAND_ECC_SOFT_BCH;
1486#else
Sergey Lapin77e524c2008-10-31 12:28:43 +01001487 nand->ecc.mode = NAND_ECC_SOFT;
Bo Shenbb5a12f2013-08-28 14:54:26 +00001488#endif
Sergey Lapin77e524c2008-10-31 12:28:43 +01001489#ifdef CONFIG_SYS_NAND_DBW_16
1490 nand->options = NAND_BUSWIDTH_16;
1491#endif
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +01001492 nand->cmd_ctrl = at91_nand_hwcontrol;
Tom Rinib4213492022-11-12 17:36:51 -05001493#ifdef CFG_SYS_NAND_READY_PIN
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +01001494 nand->dev_ready = at91_nand_ready;
1495#endif
Wu, Joshf9f69b12013-10-18 17:46:31 +08001496 nand->chip_delay = 75;
David Dueckab7ec112015-03-20 10:52:49 +01001497#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1498 nand->bbt_options |= NAND_BBT_USE_FLASH;
1499#endif
Sergey Lapin77e524c2008-10-31 12:28:43 +01001500
Wu, Josh6cded6d2012-08-23 00:05:34 +00001501 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1502 if (ret)
1503 return ret;
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001504
1505#ifdef CONFIG_ATMEL_NAND_HWECC
Wu, Joshfd3091d2012-08-23 00:05:36 +00001506#ifdef CONFIG_ATMEL_NAND_HW_PMECC
1507 ret = atmel_pmecc_nand_init_params(nand, mtd);
1508#else
Wu, Josh6cded6d2012-08-23 00:05:34 +00001509 ret = atmel_hwecc_nand_init_param(nand, mtd);
Wu, Joshfd3091d2012-08-23 00:05:36 +00001510#endif
Wu, Josh6cded6d2012-08-23 00:05:34 +00001511 if (ret)
1512 return ret;
1513#endif
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001514
Wu, Josh6cded6d2012-08-23 00:05:34 +00001515 ret = nand_scan_tail(mtd);
1516 if (!ret)
Scott Wood2c1b7e12016-05-30 13:57:55 -05001517 nand_register(devnum, mtd);
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001518
Wu, Josh6cded6d2012-08-23 00:05:34 +00001519 return ret;
1520}
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001521
Wu, Josh6cded6d2012-08-23 00:05:34 +00001522void board_nand_init(void)
1523{
1524 int i;
1525 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1526 if (atmel_nand_chip_init(i, base_addr[i]))
Sean Andersondfff1c12020-09-15 10:44:49 -04001527 log_err("atmel_nand: Fail to initialize #%d chip", i);
Sergey Lapin77e524c2008-10-31 12:28:43 +01001528}
Bo Shen9415b872014-03-03 14:47:16 +08001529#endif /* CONFIG_SPL_BUILD */