blob: 06bf5ac18ffcdfb5321e1f8737ea3de194701f3f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergey Lapin77e524c2008-10-31 12:28:43 +01002/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Sergey Lapin77e524c2008-10-31 12:28:43 +01005 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8 *
Wu, Joshfd3091d2012-08-23 00:05:36 +00009 * Add Programmable Multibit ECC support for various AT91 SoC
10 * (C) Copyright 2012 ATMEL, Hong Xu
Sergey Lapin77e524c2008-10-31 12:28:43 +010011 */
12
13#include <common.h>
Simon Glass0f2af882020-05-10 11:40:05 -060014#include <log.h>
Andreas Bießmanna4c24d32013-11-29 12:13:45 +010015#include <asm/gpio.h>
Sergey Lapin77e524c2008-10-31 12:28:43 +010016#include <asm/arch/gpio.h>
Simon Glass9bc15642020-02-03 07:36:16 -070017#include <dm/device_compat.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070018#include <dm/devres.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060019#include <linux/bitops.h>
Simon Glassc06c1be2020-05-10 11:40:08 -060020#include <linux/bug.h>
Simon Glassdbd79542020-05-10 11:40:11 -060021#include <linux/delay.h>
Sergey Lapin77e524c2008-10-31 12:28:43 +010022
Wu, Josh4e87b3152013-07-03 11:11:48 +080023#include <malloc.h>
Sergey Lapin77e524c2008-10-31 12:28:43 +010024#include <nand.h>
Wu, Joshfd3091d2012-08-23 00:05:36 +000025#include <watchdog.h>
Heiko Schocherfd683382014-10-31 08:31:01 +010026#include <linux/mtd/nand_ecc.h>
Tom Rini3bde7e22021-09-22 14:50:35 -040027#include <linux/mtd/rawnand.h>
Sergey Lapin77e524c2008-10-31 12:28:43 +010028
Nikolay Petukhove6015ca2010-03-19 10:49:27 +050029#ifdef CONFIG_ATMEL_NAND_HWECC
30
31/* Register access macros */
32#define ecc_readl(add, reg) \
Andre Renaudcf44b942016-05-05 07:28:14 -060033 readl(add + ATMEL_ECC_##reg)
Nikolay Petukhove6015ca2010-03-19 10:49:27 +050034#define ecc_writel(add, reg, value) \
Andre Renaudcf44b942016-05-05 07:28:14 -060035 writel((value), add + ATMEL_ECC_##reg)
Nikolay Petukhove6015ca2010-03-19 10:49:27 +050036
37#include "atmel_nand_ecc.h" /* Hardware ECC registers */
38
Wu, Joshfd3091d2012-08-23 00:05:36 +000039#ifdef CONFIG_ATMEL_NAND_HW_PMECC
40
Bo Shen9415b872014-03-03 14:47:16 +080041#ifdef CONFIG_SPL_BUILD
42#undef CONFIG_SYS_NAND_ONFI_DETECTION
43#endif
44
Wu, Joshfd3091d2012-08-23 00:05:36 +000045struct atmel_nand_host {
46 struct pmecc_regs __iomem *pmecc;
47 struct pmecc_errloc_regs __iomem *pmerrloc;
48 void __iomem *pmecc_rom_base;
49
50 u8 pmecc_corr_cap;
51 u16 pmecc_sector_size;
52 u32 pmecc_index_table_offset;
Wu, Josh1f5c0892015-01-16 11:54:46 +080053 u32 pmecc_version;
Wu, Joshfd3091d2012-08-23 00:05:36 +000054
55 int pmecc_bytes_per_sector;
56 int pmecc_sector_number;
57 int pmecc_degree; /* Degree of remainders */
58 int pmecc_cw_len; /* Length of codeword */
59
60 /* lookup table for alpha_to and index_of */
61 void __iomem *pmecc_alpha_to;
62 void __iomem *pmecc_index_of;
63
64 /* data for pmecc computation */
Wu, Josh4e87b3152013-07-03 11:11:48 +080065 int16_t *pmecc_smu;
66 int16_t *pmecc_partial_syn;
67 int16_t *pmecc_si;
68 int16_t *pmecc_lmu; /* polynomal order */
69 int *pmecc_mu;
70 int *pmecc_dmu;
71 int *pmecc_delta;
Wu, Joshfd3091d2012-08-23 00:05:36 +000072};
73
74static struct atmel_nand_host pmecc_host;
75static struct nand_ecclayout atmel_pmecc_oobinfo;
76
77/*
78 * Return number of ecc bytes per sector according to sector size and
79 * correction capability
80 *
81 * Following table shows what at91 PMECC supported:
82 * Correction Capability Sector_512_bytes Sector_1024_bytes
83 * ===================== ================ =================
84 * 2-bits 4-bytes 4-bytes
85 * 4-bits 7-bytes 7-bytes
86 * 8-bits 13-bytes 14-bytes
87 * 12-bits 20-bytes 21-bytes
88 * 24-bits 39-bytes 42-bytes
Josh Wuce764952015-11-24 16:34:01 +080089 * 32-bits 52-bytes 56-bytes
Wu, Joshfd3091d2012-08-23 00:05:36 +000090 */
91static int pmecc_get_ecc_bytes(int cap, int sector_size)
92{
93 int m = 12 + sector_size / 512;
94 return (m * cap + 7) / 8;
95}
96
97static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
98 int oobsize, int ecc_len)
99{
100 int i;
101
102 layout->eccbytes = ecc_len;
103
104 /* ECC will occupy the last ecc_len bytes continuously */
105 for (i = 0; i < ecc_len; i++)
106 layout->eccpos[i] = oobsize - ecc_len + i;
107
108 layout->oobfree[0].offset = 2;
109 layout->oobfree[0].length =
110 oobsize - ecc_len - layout->oobfree[0].offset;
111}
112
113static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
114{
115 int table_size;
116
117 table_size = host->pmecc_sector_size == 512 ?
118 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
119
120 /* the ALPHA lookup table is right behind the INDEX lookup table. */
121 return host->pmecc_rom_base + host->pmecc_index_table_offset +
122 table_size * sizeof(int16_t);
123}
124
Wu, Josh4e87b3152013-07-03 11:11:48 +0800125static void pmecc_data_free(struct atmel_nand_host *host)
126{
127 free(host->pmecc_partial_syn);
128 free(host->pmecc_si);
129 free(host->pmecc_lmu);
130 free(host->pmecc_smu);
131 free(host->pmecc_mu);
132 free(host->pmecc_dmu);
133 free(host->pmecc_delta);
134}
135
136static int pmecc_data_alloc(struct atmel_nand_host *host)
137{
138 const int cap = host->pmecc_corr_cap;
139 int size;
140
141 size = (2 * cap + 1) * sizeof(int16_t);
142 host->pmecc_partial_syn = malloc(size);
143 host->pmecc_si = malloc(size);
144 host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
145 host->pmecc_smu = malloc((cap + 2) * size);
146
147 size = (cap + 1) * sizeof(int);
148 host->pmecc_mu = malloc(size);
149 host->pmecc_dmu = malloc(size);
150 host->pmecc_delta = malloc(size);
151
152 if (host->pmecc_partial_syn &&
153 host->pmecc_si &&
154 host->pmecc_lmu &&
155 host->pmecc_smu &&
156 host->pmecc_mu &&
157 host->pmecc_dmu &&
158 host->pmecc_delta)
159 return 0;
160
161 /* error happened */
162 pmecc_data_free(host);
163 return -ENOMEM;
164
165}
166
Wu, Joshfd3091d2012-08-23 00:05:36 +0000167static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
168{
Scott Wood17fed142016-05-30 13:57:56 -0500169 struct nand_chip *nand_chip = mtd_to_nand(mtd);
170 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000171 int i;
172 uint32_t value;
173
174 /* Fill odd syndromes */
175 for (i = 0; i < host->pmecc_corr_cap; i++) {
Wu, Joshb31868f2014-06-24 18:18:06 +0800176 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000177 if (i & 1)
178 value >>= 16;
179 value &= 0xffff;
180 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
181 }
182}
183
184static void pmecc_substitute(struct mtd_info *mtd)
185{
Scott Wood17fed142016-05-30 13:57:56 -0500186 struct nand_chip *nand_chip = mtd_to_nand(mtd);
187 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000188 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
189 int16_t __iomem *index_of = host->pmecc_index_of;
190 int16_t *partial_syn = host->pmecc_partial_syn;
191 const int cap = host->pmecc_corr_cap;
192 int16_t *si;
193 int i, j;
194
195 /* si[] is a table that holds the current syndrome value,
196 * an element of that table belongs to the field
197 */
198 si = host->pmecc_si;
199
200 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
201
202 /* Computation 2t syndromes based on S(x) */
203 /* Odd syndromes */
204 for (i = 1; i < 2 * cap; i += 2) {
205 for (j = 0; j < host->pmecc_degree; j++) {
206 if (partial_syn[i] & (0x1 << j))
207 si[i] = readw(alpha_to + i * j) ^ si[i];
208 }
209 }
210 /* Even syndrome = (Odd syndrome) ** 2 */
211 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
212 if (si[j] == 0) {
213 si[i] = 0;
214 } else {
215 int16_t tmp;
216
217 tmp = readw(index_of + si[j]);
218 tmp = (tmp * 2) % host->pmecc_cw_len;
219 si[i] = readw(alpha_to + tmp);
220 }
221 }
222}
223
224/*
225 * This function defines a Berlekamp iterative procedure for
226 * finding the value of the error location polynomial.
227 * The input is si[], initialize by pmecc_substitute().
228 * The output is smu[][].
229 *
230 * This function is written according to chip datasheet Chapter:
231 * Find the Error Location Polynomial Sigma(x) of Section:
232 * Programmable Multibit ECC Control (PMECC).
233 */
234static void pmecc_get_sigma(struct mtd_info *mtd)
235{
Scott Wood17fed142016-05-30 13:57:56 -0500236 struct nand_chip *nand_chip = mtd_to_nand(mtd);
237 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000238
239 int16_t *lmu = host->pmecc_lmu;
240 int16_t *si = host->pmecc_si;
241 int *mu = host->pmecc_mu;
242 int *dmu = host->pmecc_dmu; /* Discrepancy */
243 int *delta = host->pmecc_delta; /* Delta order */
244 int cw_len = host->pmecc_cw_len;
245 const int16_t cap = host->pmecc_corr_cap;
246 const int num = 2 * cap + 1;
247 int16_t __iomem *index_of = host->pmecc_index_of;
248 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
249 int i, j, k;
250 uint32_t dmu_0_count, tmp;
251 int16_t *smu = host->pmecc_smu;
252
253 /* index of largest delta */
254 int ro;
255 int largest;
256 int diff;
257
258 /* Init the Sigma(x) */
Bin Meng455ef432018-10-08 02:27:44 -0700259 memset(smu, 0, sizeof(int16_t) * num * (cap + 2));
Wu, Joshfd3091d2012-08-23 00:05:36 +0000260
261 dmu_0_count = 0;
262
263 /* First Row */
264
265 /* Mu */
266 mu[0] = -1;
267
268 smu[0] = 1;
269
270 /* discrepancy set to 1 */
271 dmu[0] = 1;
272 /* polynom order set to 0 */
273 lmu[0] = 0;
274 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
275 delta[0] = -1;
276
277 /* Second Row */
278
279 /* Mu */
280 mu[1] = 0;
281 /* Sigma(x) set to 1 */
282 smu[num] = 1;
283
284 /* discrepancy set to S1 */
285 dmu[1] = si[1];
286
287 /* polynom order set to 0 */
288 lmu[1] = 0;
289
290 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
291 delta[1] = 0;
292
293 for (i = 1; i <= cap; i++) {
294 mu[i + 1] = i << 1;
295 /* Begin Computing Sigma (Mu+1) and L(mu) */
296 /* check if discrepancy is set to 0 */
297 if (dmu[i] == 0) {
298 dmu_0_count++;
299
300 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
301 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
302 tmp += 2;
303 else
304 tmp += 1;
305
306 if (dmu_0_count == tmp) {
307 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
308 smu[(cap + 1) * num + j] =
309 smu[i * num + j];
310
311 lmu[cap + 1] = lmu[i];
312 return;
313 }
314
315 /* copy polynom */
316 for (j = 0; j <= lmu[i] >> 1; j++)
317 smu[(i + 1) * num + j] = smu[i * num + j];
318
319 /* copy previous polynom order to the next */
320 lmu[i + 1] = lmu[i];
321 } else {
322 ro = 0;
323 largest = -1;
324 /* find largest delta with dmu != 0 */
325 for (j = 0; j < i; j++) {
326 if ((dmu[j]) && (delta[j] > largest)) {
327 largest = delta[j];
328 ro = j;
329 }
330 }
331
332 /* compute difference */
333 diff = (mu[i] - mu[ro]);
334
335 /* Compute degree of the new smu polynomial */
336 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
337 lmu[i + 1] = lmu[i];
338 else
339 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
340
341 /* Init smu[i+1] with 0 */
342 for (k = 0; k < num; k++)
343 smu[(i + 1) * num + k] = 0;
344
345 /* Compute smu[i+1] */
346 for (k = 0; k <= lmu[ro] >> 1; k++) {
347 int16_t a, b, c;
348
349 if (!(smu[ro * num + k] && dmu[i]))
350 continue;
351 a = readw(index_of + dmu[i]);
352 b = readw(index_of + dmu[ro]);
353 c = readw(index_of + smu[ro * num + k]);
354 tmp = a + (cw_len - b) + c;
355 a = readw(alpha_to + tmp % cw_len);
356 smu[(i + 1) * num + (k + diff)] = a;
357 }
358
359 for (k = 0; k <= lmu[i] >> 1; k++)
360 smu[(i + 1) * num + k] ^= smu[i * num + k];
361 }
362
363 /* End Computing Sigma (Mu+1) and L(mu) */
364 /* In either case compute delta */
365 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
366
367 /* Do not compute discrepancy for the last iteration */
368 if (i >= cap)
369 continue;
370
371 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
372 tmp = 2 * (i - 1);
373 if (k == 0) {
374 dmu[i + 1] = si[tmp + 3];
375 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
376 int16_t a, b, c;
377 a = readw(index_of +
378 smu[(i + 1) * num + k]);
379 b = si[2 * (i - 1) + 3 - k];
380 c = readw(index_of + b);
381 tmp = a + c;
382 tmp %= cw_len;
383 dmu[i + 1] = readw(alpha_to + tmp) ^
384 dmu[i + 1];
385 }
386 }
387 }
388}
389
390static int pmecc_err_location(struct mtd_info *mtd)
391{
Scott Wood17fed142016-05-30 13:57:56 -0500392 struct nand_chip *nand_chip = mtd_to_nand(mtd);
393 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000394 const int cap = host->pmecc_corr_cap;
395 const int num = 2 * cap + 1;
396 int sector_size = host->pmecc_sector_size;
397 int err_nbr = 0; /* number of error */
398 int roots_nbr; /* number of roots */
399 int i;
400 uint32_t val;
401 int16_t *smu = host->pmecc_smu;
402 int timeout = PMECC_MAX_TIMEOUT_US;
403
Wu, Joshb31868f2014-06-24 18:18:06 +0800404 pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000405
406 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
Wu, Joshb31868f2014-06-24 18:18:06 +0800407 pmecc_writel(host->pmerrloc, sigma[i],
408 smu[(cap + 1) * num + i]);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000409 err_nbr++;
410 }
411
412 val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
413 if (sector_size == 1024)
414 val |= PMERRLOC_ELCFG_SECTOR_1024;
415
Wu, Joshb31868f2014-06-24 18:18:06 +0800416 pmecc_writel(host->pmerrloc, elcfg, val);
417 pmecc_writel(host->pmerrloc, elen,
418 sector_size * 8 + host->pmecc_degree * cap);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000419
420 while (--timeout) {
Wu, Joshb31868f2014-06-24 18:18:06 +0800421 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
Wu, Joshfd3091d2012-08-23 00:05:36 +0000422 break;
423 WATCHDOG_RESET();
424 udelay(1);
425 }
426
427 if (!timeout) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400428 dev_err(mtd->dev,
429 "Timeout to calculate PMECC error location\n");
Wu, Joshfd3091d2012-08-23 00:05:36 +0000430 return -1;
431 }
432
Wu, Joshb31868f2014-06-24 18:18:06 +0800433 roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
Wu, Joshfd3091d2012-08-23 00:05:36 +0000434 >> 8;
435 /* Number of roots == degree of smu hence <= cap */
436 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
437 return err_nbr - 1;
438
439 /* Number of roots does not match the degree of smu
440 * unable to correct error */
441 return -1;
442}
443
444static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
445 int sector_num, int extra_bytes, int err_nbr)
446{
Scott Wood17fed142016-05-30 13:57:56 -0500447 struct nand_chip *nand_chip = mtd_to_nand(mtd);
448 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000449 int i = 0;
450 int byte_pos, bit_pos, sector_size, pos;
451 uint32_t tmp;
452 uint8_t err_byte;
453
454 sector_size = host->pmecc_sector_size;
455
456 while (err_nbr) {
Wu, Joshb31868f2014-06-24 18:18:06 +0800457 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000458 byte_pos = tmp / 8;
459 bit_pos = tmp % 8;
460
461 if (byte_pos >= (sector_size + extra_bytes))
462 BUG(); /* should never happen */
463
464 if (byte_pos < sector_size) {
465 err_byte = *(buf + byte_pos);
466 *(buf + byte_pos) ^= (1 << bit_pos);
467
468 pos = sector_num * host->pmecc_sector_size + byte_pos;
Sean Andersondfff1c12020-09-15 10:44:49 -0400469 dev_dbg(mtd->dev,
470 "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
Wu, Joshfd3091d2012-08-23 00:05:36 +0000471 pos, bit_pos, err_byte, *(buf + byte_pos));
472 } else {
473 /* Bit flip in OOB area */
474 tmp = sector_num * host->pmecc_bytes_per_sector
475 + (byte_pos - sector_size);
476 err_byte = ecc[tmp];
477 ecc[tmp] ^= (1 << bit_pos);
478
479 pos = tmp + nand_chip->ecc.layout->eccpos[0];
Sean Andersondfff1c12020-09-15 10:44:49 -0400480 dev_dbg(mtd->dev,
481 "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
Wu, Joshfd3091d2012-08-23 00:05:36 +0000482 pos, bit_pos, err_byte, ecc[tmp]);
483 }
484
485 i++;
486 err_nbr--;
487 }
488
489 return;
490}
491
492static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
493 u8 *ecc)
494{
Scott Wood17fed142016-05-30 13:57:56 -0500495 struct nand_chip *nand_chip = mtd_to_nand(mtd);
496 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Kai Stuhlemmer (ebee Engineering)bd4d5992021-05-21 11:52:06 +0300497 int i, err_nbr;
498 u8 *buf_pos, *ecc_pos;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000499
Wu, Joshfd3091d2012-08-23 00:05:36 +0000500 for (i = 0; i < host->pmecc_sector_number; i++) {
501 err_nbr = 0;
502 if (pmecc_stat & 0x1) {
503 buf_pos = buf + i * host->pmecc_sector_size;
504
505 pmecc_gen_syndrome(mtd, i);
506 pmecc_substitute(mtd);
507 pmecc_get_sigma(mtd);
508
509 err_nbr = pmecc_err_location(mtd);
Kai Stuhlemmer (ebee Engineering)bd4d5992021-05-21 11:52:06 +0300510 if (err_nbr >= 0) {
511 pmecc_correct_data(mtd, buf_pos, ecc, i,
512 host->pmecc_bytes_per_sector,
513 err_nbr);
514 } else if (host->pmecc_version < PMECC_VERSION_SAMA5D4) {
515 ecc_pos = ecc + i * host->pmecc_bytes_per_sector;
516
517 err_nbr = nand_check_erased_ecc_chunk(
518 buf_pos, host->pmecc_sector_size,
519 ecc_pos, host->pmecc_bytes_per_sector,
520 NULL, 0, host->pmecc_corr_cap);
521 }
522
523 if (err_nbr < 0) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400524 dev_err(mtd->dev, "PMECC: Too many errors\n");
Wu, Joshfd3091d2012-08-23 00:05:36 +0000525 mtd->ecc_stats.failed++;
Scott Wood52ab7ce2016-05-30 13:57:58 -0500526 return -EBADMSG;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000527 }
Kai Stuhlemmer (ebee Engineering)bd4d5992021-05-21 11:52:06 +0300528
529 mtd->ecc_stats.corrected += err_nbr;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000530 }
531 pmecc_stat >>= 1;
532 }
533
534 return 0;
535}
536
537static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
Sergey Lapin3a38a552013-01-14 03:46:50 +0000538 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
Wu, Joshfd3091d2012-08-23 00:05:36 +0000539{
Scott Wood17fed142016-05-30 13:57:56 -0500540 struct atmel_nand_host *host = nand_get_controller_data(chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000541 int eccsize = chip->ecc.size;
542 uint8_t *oob = chip->oob_poi;
543 uint32_t *eccpos = chip->ecc.layout->eccpos;
544 uint32_t stat;
545 int timeout = PMECC_MAX_TIMEOUT_US;
546
547 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
548 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
549 pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
550 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
551
552 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
553 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
554
555 chip->read_buf(mtd, buf, eccsize);
556 chip->read_buf(mtd, oob, mtd->oobsize);
557
558 while (--timeout) {
559 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
560 break;
561 WATCHDOG_RESET();
562 udelay(1);
563 }
564
565 if (!timeout) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400566 dev_err(mtd->dev, "Timeout to read PMECC page\n");
Wu, Joshfd3091d2012-08-23 00:05:36 +0000567 return -1;
568 }
569
570 stat = pmecc_readl(host->pmecc, isr);
571 if (stat != 0)
572 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
Scott Wood52ab7ce2016-05-30 13:57:58 -0500573 return -EBADMSG;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000574
575 return 0;
576}
577
Sergey Lapin3a38a552013-01-14 03:46:50 +0000578static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
579 struct nand_chip *chip, const uint8_t *buf,
Scott Wood46e13102016-05-30 13:57:57 -0500580 int oob_required, int page)
Wu, Joshfd3091d2012-08-23 00:05:36 +0000581{
Scott Wood17fed142016-05-30 13:57:56 -0500582 struct atmel_nand_host *host = nand_get_controller_data(chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000583 uint32_t *eccpos = chip->ecc.layout->eccpos;
584 int i, j;
585 int timeout = PMECC_MAX_TIMEOUT_US;
586
587 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
588 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
589
590 pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
591 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
592
593 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
594 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
595
596 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
597
598 while (--timeout) {
599 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
600 break;
601 WATCHDOG_RESET();
602 udelay(1);
603 }
604
605 if (!timeout) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400606 dev_err(mtd->dev,
607 "Timeout to read PMECC status, fail to write PMECC in oob\n");
Sergey Lapin3a38a552013-01-14 03:46:50 +0000608 goto out;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000609 }
610
611 for (i = 0; i < host->pmecc_sector_number; i++) {
612 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
613 int pos;
614
615 pos = i * host->pmecc_bytes_per_sector + j;
616 chip->oob_poi[eccpos[pos]] =
Wu, Joshb31868f2014-06-24 18:18:06 +0800617 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000618 }
619 }
620 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
Sergey Lapin3a38a552013-01-14 03:46:50 +0000621out:
622 return 0;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000623}
624
625static void atmel_pmecc_core_init(struct mtd_info *mtd)
626{
Scott Wood17fed142016-05-30 13:57:56 -0500627 struct nand_chip *nand_chip = mtd_to_nand(mtd);
628 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000629 uint32_t val = 0;
630 struct nand_ecclayout *ecc_layout;
631
632 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
633 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
634
635 switch (host->pmecc_corr_cap) {
636 case 2:
637 val = PMECC_CFG_BCH_ERR2;
638 break;
639 case 4:
640 val = PMECC_CFG_BCH_ERR4;
641 break;
642 case 8:
643 val = PMECC_CFG_BCH_ERR8;
644 break;
645 case 12:
646 val = PMECC_CFG_BCH_ERR12;
647 break;
648 case 24:
649 val = PMECC_CFG_BCH_ERR24;
650 break;
Josh Wuce764952015-11-24 16:34:01 +0800651 case 32:
652 val = PMECC_CFG_BCH_ERR32;
653 break;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000654 }
655
656 if (host->pmecc_sector_size == 512)
657 val |= PMECC_CFG_SECTOR512;
658 else if (host->pmecc_sector_size == 1024)
659 val |= PMECC_CFG_SECTOR1024;
660
661 switch (host->pmecc_sector_number) {
662 case 1:
663 val |= PMECC_CFG_PAGE_1SECTOR;
664 break;
665 case 2:
666 val |= PMECC_CFG_PAGE_2SECTORS;
667 break;
668 case 4:
669 val |= PMECC_CFG_PAGE_4SECTORS;
670 break;
671 case 8:
672 val |= PMECC_CFG_PAGE_8SECTORS;
673 break;
674 }
675
676 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
677 | PMECC_CFG_AUTO_DISABLE);
678 pmecc_writel(host->pmecc, cfg, val);
679
680 ecc_layout = nand_chip->ecc.layout;
681 pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
682 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
683 pmecc_writel(host->pmecc, eaddr,
684 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
685 /* See datasheet about PMECC Clock Control Register */
686 pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
687 pmecc_writel(host->pmecc, idr, 0xff);
688 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
689}
690
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800691#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
692/*
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800693 * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
694 * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
695 * ONFI ECC parameters.
696 * @host: point to an atmel_nand_host structure.
697 * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
698 * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
699 * @chip: point to an nand_chip structure.
700 * @cap: store the ONFI ECC correct bits capbility
701 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
702 *
703 * Return 0 if success. otherwise return the error code.
704 */
705static int pmecc_choose_ecc(struct atmel_nand_host *host,
706 struct nand_chip *chip,
707 int *cap, int *sector_size)
708{
709 /* Get ECC requirement from ONFI parameters */
710 *cap = *sector_size = 0;
711 if (chip->onfi_version) {
Josh Wuc90cc682016-01-25 14:06:33 +0800712 *cap = chip->ecc_strength_ds;
713 *sector_size = chip->ecc_step_ds;
Masahiro Yamadaf8a5d512017-10-18 00:10:48 +0900714 pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
Josh Wuc90cc682016-01-25 14:06:33 +0800715 *cap, *sector_size);
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800716 }
Josh Wuc90cc682016-01-25 14:06:33 +0800717
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800718 if (*cap == 0 && *sector_size == 0) {
Josh Wuc90cc682016-01-25 14:06:33 +0800719 /* Non-ONFI compliant */
Sean Andersondfff1c12020-09-15 10:44:49 -0400720 dev_info(chip->mtd.dev,
721 "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800722 *cap = 2;
723 *sector_size = 512;
724 }
725
726 /* If head file doesn't specify then use the one in ONFI parameters */
727 if (host->pmecc_corr_cap == 0) {
728 /* use the most fitable ecc bits (the near bigger one ) */
729 if (*cap <= 2)
730 host->pmecc_corr_cap = 2;
731 else if (*cap <= 4)
732 host->pmecc_corr_cap = 4;
733 else if (*cap <= 8)
734 host->pmecc_corr_cap = 8;
735 else if (*cap <= 12)
736 host->pmecc_corr_cap = 12;
737 else if (*cap <= 24)
738 host->pmecc_corr_cap = 24;
739 else
Josh Wuce764952015-11-24 16:34:01 +0800740#ifdef CONFIG_SAMA5D2
741 host->pmecc_corr_cap = 32;
742#else
743 host->pmecc_corr_cap = 24;
744#endif
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800745 }
746 if (host->pmecc_sector_size == 0) {
747 /* use the most fitable sector size (the near smaller one ) */
748 if (*sector_size >= 1024)
749 host->pmecc_sector_size = 1024;
750 else if (*sector_size >= 512)
751 host->pmecc_sector_size = 512;
752 else
753 return -EINVAL;
754 }
755 return 0;
756}
757#endif
758
Josh Wuf259ad22014-11-10 15:24:00 +0800759#if defined(NO_GALOIS_TABLE_IN_ROM)
760static uint16_t *pmecc_galois_table;
761static inline int deg(unsigned int poly)
762{
763 /* polynomial degree is the most-significant bit index */
764 return fls(poly) - 1;
765}
766
767static int build_gf_tables(int mm, unsigned int poly,
768 int16_t *index_of, int16_t *alpha_to)
769{
770 unsigned int i, x = 1;
771 const unsigned int k = 1 << deg(poly);
772 unsigned int nn = (1 << mm) - 1;
773
774 /* primitive polynomial must be of degree m */
775 if (k != (1u << mm))
776 return -EINVAL;
777
778 for (i = 0; i < nn; i++) {
779 alpha_to[i] = x;
780 index_of[x] = i;
781 if (i && (x == 1))
782 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
783 return -EINVAL;
784 x <<= 1;
785 if (x & k)
786 x ^= poly;
787 }
788
789 alpha_to[nn] = 1;
790 index_of[0] = 0;
791
792 return 0;
793}
794
795static uint16_t *create_lookup_table(int sector_size)
796{
797 int degree = (sector_size == 512) ?
798 PMECC_GF_DIMENSION_13 :
799 PMECC_GF_DIMENSION_14;
800 unsigned int poly = (sector_size == 512) ?
801 PMECC_GF_13_PRIMITIVE_POLY :
802 PMECC_GF_14_PRIMITIVE_POLY;
803 int table_size = (sector_size == 512) ?
804 PMECC_INDEX_TABLE_SIZE_512 :
805 PMECC_INDEX_TABLE_SIZE_1024;
806
807 int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
808 if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
809 return NULL;
810
811 return (uint16_t *)addr;
812}
813#endif
814
Wu, Joshfd3091d2012-08-23 00:05:36 +0000815static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
816 struct mtd_info *mtd)
817{
818 struct atmel_nand_host *host;
819 int cap, sector_size;
820
Scott Wood17fed142016-05-30 13:57:56 -0500821 host = &pmecc_host;
822 nand_set_controller_data(nand, host);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000823
824 nand->ecc.mode = NAND_ECC_HW;
825 nand->ecc.calculate = NULL;
826 nand->ecc.correct = NULL;
827 nand->ecc.hwctl = NULL;
828
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800829#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
830 host->pmecc_corr_cap = host->pmecc_sector_size = 0;
831
832#ifdef CONFIG_PMECC_CAP
833 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
834#endif
835#ifdef CONFIG_PMECC_SECTOR_SIZE
836 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
837#endif
838 /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
839 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
840 * from ONFI.
841 */
842 if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400843 dev_err(mtd->dev,
844 "Required ECC %d bits in %d bytes not supported!\n",
Josh Wudaf40882016-01-25 14:06:34 +0800845 cap, sector_size);
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800846 return -EINVAL;
847 }
848
849 if (cap > host->pmecc_corr_cap)
Sean Andersondfff1c12020-09-15 10:44:49 -0400850 dev_info(mtd->dev,
851 "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
852 host->pmecc_corr_cap, cap);
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800853 if (sector_size < host->pmecc_sector_size)
Sean Andersondfff1c12020-09-15 10:44:49 -0400854 dev_info(mtd->dev,
855 "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
856 host->pmecc_sector_size, sector_size);
Wu, Josh3b4c7f62013-07-04 15:36:23 +0800857#else /* CONFIG_SYS_NAND_ONFI_DETECTION */
858 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
859 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
860#endif
861
862 cap = host->pmecc_corr_cap;
863 sector_size = host->pmecc_sector_size;
864
865 /* TODO: need check whether cap & sector_size is validate */
Josh Wuf259ad22014-11-10 15:24:00 +0800866#if defined(NO_GALOIS_TABLE_IN_ROM)
867 /*
868 * As pmecc_rom_base is the begin of the gallois field table, So the
869 * index offset just set as 0.
870 */
871 host->pmecc_index_table_offset = 0;
872#else
Wu, Joshb45c9492013-07-03 11:11:45 +0800873 if (host->pmecc_sector_size == 512)
874 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
875 else
876 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
Josh Wuf259ad22014-11-10 15:24:00 +0800877#endif
Wu, Joshfd3091d2012-08-23 00:05:36 +0000878
Masahiro Yamadaf8a5d512017-10-18 00:10:48 +0900879 pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
880 cap, sector_size);
Wu, Joshfd3091d2012-08-23 00:05:36 +0000881
882 host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
883 host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
884 ATMEL_BASE_PMERRLOC;
Josh Wuf259ad22014-11-10 15:24:00 +0800885#if defined(NO_GALOIS_TABLE_IN_ROM)
886 pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
887 if (!pmecc_galois_table) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400888 dev_err(mtd->dev, "out of memory\n");
Josh Wuf259ad22014-11-10 15:24:00 +0800889 return -ENOMEM;
890 }
891
892 host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
893#else
Wu, Joshfd3091d2012-08-23 00:05:36 +0000894 host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
Josh Wuf259ad22014-11-10 15:24:00 +0800895#endif
Wu, Joshfd3091d2012-08-23 00:05:36 +0000896
897 /* ECC is calculated for the whole page (1 step) */
898 nand->ecc.size = mtd->writesize;
899
900 /* set ECC page size and oob layout */
901 switch (mtd->writesize) {
902 case 2048:
903 case 4096:
Wu, Joshf9f69b12013-10-18 17:46:31 +0800904 case 8192:
Wu, Josh89bdc8e2013-08-23 15:09:05 +0800905 host->pmecc_degree = (sector_size == 512) ?
906 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000907 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
908 host->pmecc_sector_number = mtd->writesize / sector_size;
909 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
910 cap, sector_size);
911 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
912 host->pmecc_index_of = host->pmecc_rom_base +
913 host->pmecc_index_table_offset;
914
915 nand->ecc.steps = 1;
916 nand->ecc.bytes = host->pmecc_bytes_per_sector *
917 host->pmecc_sector_number;
Wu, Joshf9f69b12013-10-18 17:46:31 +0800918
919 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400920 dev_err(mtd->dev,
921 "too large eccpos entries. max support ecc.bytes is %d\n",
922 MTD_MAX_ECCPOS_ENTRIES_LARGE);
Wu, Joshf9f69b12013-10-18 17:46:31 +0800923 return -EINVAL;
924 }
925
Josh Wu5d3256c2016-01-25 14:06:35 +0800926 if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400927 dev_err(mtd->dev, "No room for ECC bytes\n");
Wu, Joshfd3091d2012-08-23 00:05:36 +0000928 return -EINVAL;
929 }
930 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
931 mtd->oobsize,
932 nand->ecc.bytes);
933 nand->ecc.layout = &atmel_pmecc_oobinfo;
934 break;
935 case 512:
936 case 1024:
937 /* TODO */
Sean Andersondfff1c12020-09-15 10:44:49 -0400938 dev_err(mtd->dev,
939 "Unsupported page size for PMECC, use Software ECC\n");
Wu, Joshfd3091d2012-08-23 00:05:36 +0000940 default:
941 /* page size not handled by HW ECC */
942 /* switching back to soft ECC */
943 nand->ecc.mode = NAND_ECC_SOFT;
944 nand->ecc.read_page = NULL;
945 nand->ecc.postpad = 0;
946 nand->ecc.prepad = 0;
947 nand->ecc.bytes = 0;
948 return 0;
949 }
950
Wu, Josh4e87b3152013-07-03 11:11:48 +0800951 /* Allocate data for PMECC computation */
952 if (pmecc_data_alloc(host)) {
Sean Andersondfff1c12020-09-15 10:44:49 -0400953 dev_err(mtd->dev,
954 "Cannot allocate memory for PMECC computation!\n");
Wu, Josh4e87b3152013-07-03 11:11:48 +0800955 return -ENOMEM;
956 }
957
Boris BREZILLONd7915f42014-09-02 10:23:09 +0200958 nand->options |= NAND_NO_SUBPAGE_WRITE;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000959 nand->ecc.read_page = atmel_nand_pmecc_read_page;
960 nand->ecc.write_page = atmel_nand_pmecc_write_page;
Sergey Lapin3a38a552013-01-14 03:46:50 +0000961 nand->ecc.strength = cap;
Wu, Joshfd3091d2012-08-23 00:05:36 +0000962
Wu, Josh1f5c0892015-01-16 11:54:46 +0800963 /* Check the PMECC ip version */
964 host->pmecc_version = pmecc_readl(host->pmerrloc, version);
Sean Andersondfff1c12020-09-15 10:44:49 -0400965 dev_dbg(mtd->dev, "PMECC IP version is: %x\n", host->pmecc_version);
Wu, Josh1f5c0892015-01-16 11:54:46 +0800966
Wu, Joshfd3091d2012-08-23 00:05:36 +0000967 atmel_pmecc_core_init(mtd);
968
969 return 0;
970}
971
972#else
973
Nikolay Petukhove6015ca2010-03-19 10:49:27 +0500974/* oob layout for large page size
975 * bad block info is on bytes 0 and 1
976 * the bytes have to be consecutives to avoid
977 * several NAND_CMD_RNDOUT during read
978 */
979static struct nand_ecclayout atmel_oobinfo_large = {
980 .eccbytes = 4,
981 .eccpos = {60, 61, 62, 63},
982 .oobfree = {
983 {2, 58}
984 },
985};
986
987/* oob layout for small page size
988 * bad block info is on bytes 4 and 5
989 * the bytes have to be consecutives to avoid
990 * several NAND_CMD_RNDOUT during read
991 */
992static struct nand_ecclayout atmel_oobinfo_small = {
993 .eccbytes = 4,
994 .eccpos = {0, 1, 2, 3},
995 .oobfree = {
996 {6, 10}
997 },
998};
999
1000/*
1001 * Calculate HW ECC
1002 *
1003 * function called after a write
1004 *
1005 * mtd: MTD block structure
1006 * dat: raw data (unused)
1007 * ecc_code: buffer for ECC
1008 */
1009static int atmel_nand_calculate(struct mtd_info *mtd,
1010 const u_char *dat, unsigned char *ecc_code)
1011{
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001012 unsigned int ecc_value;
1013
1014 /* get the first 2 ECC bytes */
1015 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1016
1017 ecc_code[0] = ecc_value & 0xFF;
1018 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1019
1020 /* get the last 2 ECC bytes */
1021 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1022
1023 ecc_code[2] = ecc_value & 0xFF;
1024 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1025
1026 return 0;
1027}
1028
1029/*
1030 * HW ECC read page function
1031 *
1032 * mtd: mtd info structure
1033 * chip: nand chip info structure
1034 * buf: buffer to store read data
Sergey Lapin3a38a552013-01-14 03:46:50 +00001035 * oob_required: caller expects OOB data read to chip->oob_poi
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001036 */
Sergey Lapin3a38a552013-01-14 03:46:50 +00001037static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1038 uint8_t *buf, int oob_required, int page)
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001039{
1040 int eccsize = chip->ecc.size;
1041 int eccbytes = chip->ecc.bytes;
1042 uint32_t *eccpos = chip->ecc.layout->eccpos;
1043 uint8_t *p = buf;
1044 uint8_t *oob = chip->oob_poi;
1045 uint8_t *ecc_pos;
1046 int stat;
1047
1048 /* read the page */
1049 chip->read_buf(mtd, p, eccsize);
1050
1051 /* move to ECC position if needed */
1052 if (eccpos[0] != 0) {
1053 /* This only works on large pages
1054 * because the ECC controller waits for
1055 * NAND_CMD_RNDOUTSTART after the
1056 * NAND_CMD_RNDOUT.
1057 * anyway, for small pages, the eccpos[0] == 0
1058 */
1059 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1060 mtd->writesize + eccpos[0], -1);
1061 }
1062
1063 /* the ECC controller needs to read the ECC just after the data */
1064 ecc_pos = oob + eccpos[0];
1065 chip->read_buf(mtd, ecc_pos, eccbytes);
1066
1067 /* check if there's an error */
1068 stat = chip->ecc.correct(mtd, p, oob, NULL);
1069
1070 if (stat < 0)
1071 mtd->ecc_stats.failed++;
1072 else
1073 mtd->ecc_stats.corrected += stat;
1074
1075 /* get back to oob start (end of page) */
1076 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1077
1078 /* read the oob */
1079 chip->read_buf(mtd, oob, mtd->oobsize);
1080
1081 return 0;
1082}
1083
1084/*
1085 * HW ECC Correction
1086 *
1087 * function called after a read
1088 *
1089 * mtd: MTD block structure
1090 * dat: raw data read from the chip
1091 * read_ecc: ECC from the chip (unused)
1092 * isnull: unused
1093 *
1094 * Detect and correct a 1 bit error for a page
1095 */
1096static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1097 u_char *read_ecc, u_char *isnull)
1098{
Scott Wood17fed142016-05-30 13:57:56 -05001099 struct nand_chip *nand_chip = mtd_to_nand(mtd);
Wu, Josh1586d1b2012-08-23 00:05:35 +00001100 unsigned int ecc_status;
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001101 unsigned int ecc_word, ecc_bit;
1102
1103 /* get the status from the Status Register */
1104 ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1105
1106 /* if there's no error */
1107 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1108 return 0;
1109
1110 /* get error bit offset (4 bits) */
1111 ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1112 /* get word address (12 bits) */
1113 ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1114 ecc_word >>= 4;
1115
1116 /* if there are multiple errors */
1117 if (ecc_status & ATMEL_ECC_MULERR) {
1118 /* check if it is a freshly erased block
1119 * (filled with 0xff) */
1120 if ((ecc_bit == ATMEL_ECC_BITADDR)
1121 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1122 /* the block has just been erased, return OK */
1123 return 0;
1124 }
1125 /* it doesn't seems to be a freshly
1126 * erased block.
1127 * We can't correct so many errors */
Sean Andersondfff1c12020-09-15 10:44:49 -04001128 dev_warn(mtd->dev,
1129 "multiple errors detected. Unable to correct.\n");
Scott Wood52ab7ce2016-05-30 13:57:58 -05001130 return -EBADMSG;
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001131 }
1132
1133 /* if there's a single bit error : we can correct it */
1134 if (ecc_status & ATMEL_ECC_ECCERR) {
1135 /* there's nothing much to do here.
1136 * the bit error is on the ECC itself.
1137 */
Sean Andersondfff1c12020-09-15 10:44:49 -04001138 dev_warn(mtd->dev,
1139 "one bit error on ECC code. Nothing to correct\n");
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001140 return 0;
1141 }
1142
Sean Andersondfff1c12020-09-15 10:44:49 -04001143 dev_warn(mtd->dev,
1144 "one bit error on data. (word offset in the page : 0x%x bit offset : 0x%x)\n",
1145 ecc_word, ecc_bit);
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001146 /* correct the error */
1147 if (nand_chip->options & NAND_BUSWIDTH_16) {
1148 /* 16 bits words */
1149 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1150 } else {
1151 /* 8 bits words */
1152 dat[ecc_word] ^= (1 << ecc_bit);
1153 }
Sean Andersondfff1c12020-09-15 10:44:49 -04001154 dev_warn(mtd->dev, "error corrected\n");
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001155 return 1;
1156}
1157
1158/*
1159 * Enable HW ECC : unused on most chips
1160 */
1161static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1162{
1163}
Wu, Josh6cded6d2012-08-23 00:05:34 +00001164
1165int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1166{
1167 nand->ecc.mode = NAND_ECC_HW;
1168 nand->ecc.calculate = atmel_nand_calculate;
1169 nand->ecc.correct = atmel_nand_correct;
1170 nand->ecc.hwctl = atmel_nand_hwctl;
1171 nand->ecc.read_page = atmel_nand_read_page;
1172 nand->ecc.bytes = 4;
Andre Renaudeaf23212016-05-05 07:28:15 -06001173 nand->ecc.strength = 4;
Wu, Josh6cded6d2012-08-23 00:05:34 +00001174
1175 if (nand->ecc.mode == NAND_ECC_HW) {
1176 /* ECC is calculated for the whole page (1 step) */
1177 nand->ecc.size = mtd->writesize;
1178
1179 /* set ECC page size and oob layout */
1180 switch (mtd->writesize) {
1181 case 512:
1182 nand->ecc.layout = &atmel_oobinfo_small;
1183 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1184 ATMEL_ECC_PAGESIZE_528);
1185 break;
1186 case 1024:
1187 nand->ecc.layout = &atmel_oobinfo_large;
1188 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1189 ATMEL_ECC_PAGESIZE_1056);
1190 break;
1191 case 2048:
1192 nand->ecc.layout = &atmel_oobinfo_large;
1193 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1194 ATMEL_ECC_PAGESIZE_2112);
1195 break;
1196 case 4096:
1197 nand->ecc.layout = &atmel_oobinfo_large;
1198 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1199 ATMEL_ECC_PAGESIZE_4224);
1200 break;
1201 default:
1202 /* page size not handled by HW ECC */
1203 /* switching back to soft ECC */
1204 nand->ecc.mode = NAND_ECC_SOFT;
1205 nand->ecc.calculate = NULL;
1206 nand->ecc.correct = NULL;
1207 nand->ecc.hwctl = NULL;
1208 nand->ecc.read_page = NULL;
1209 nand->ecc.postpad = 0;
1210 nand->ecc.prepad = 0;
1211 nand->ecc.bytes = 0;
1212 break;
1213 }
1214 }
1215
1216 return 0;
1217}
1218
Wu, Joshfd3091d2012-08-23 00:05:36 +00001219#endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1220
1221#endif /* CONFIG_ATMEL_NAND_HWECC */
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001222
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +01001223static void at91_nand_hwcontrol(struct mtd_info *mtd,
Sergey Lapin77e524c2008-10-31 12:28:43 +01001224 int cmd, unsigned int ctrl)
1225{
Scott Wood17fed142016-05-30 13:57:56 -05001226 struct nand_chip *this = mtd_to_nand(mtd);
Sergey Lapin77e524c2008-10-31 12:28:43 +01001227
1228 if (ctrl & NAND_CTRL_CHANGE) {
1229 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +01001230 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1231 | CONFIG_SYS_NAND_MASK_CLE);
Sergey Lapin77e524c2008-10-31 12:28:43 +01001232
1233 if (ctrl & NAND_CLE)
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +01001234 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
Sergey Lapin77e524c2008-10-31 12:28:43 +01001235 if (ctrl & NAND_ALE)
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +01001236 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
Sergey Lapin77e524c2008-10-31 12:28:43 +01001237
michael4b5cef72011-03-14 21:16:38 +00001238#ifdef CONFIG_SYS_NAND_ENABLE_PIN
Wenyou Yangd4aab6b2017-03-23 12:55:21 +08001239 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1240 !(ctrl & NAND_NCE));
michael4b5cef72011-03-14 21:16:38 +00001241#endif
Sergey Lapin77e524c2008-10-31 12:28:43 +01001242 this->IO_ADDR_W = (void *) IO_ADDR_W;
1243 }
1244
1245 if (cmd != NAND_CMD_NONE)
1246 writeb(cmd, this->IO_ADDR_W);
1247}
1248
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +01001249#ifdef CONFIG_SYS_NAND_READY_PIN
1250static int at91_nand_ready(struct mtd_info *mtd)
Sergey Lapin77e524c2008-10-31 12:28:43 +01001251{
Wenyou Yangd4aab6b2017-03-23 12:55:21 +08001252 return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
Sergey Lapin77e524c2008-10-31 12:28:43 +01001253}
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +01001254#endif
Sergey Lapin77e524c2008-10-31 12:28:43 +01001255
Bo Shen9415b872014-03-03 14:47:16 +08001256#ifdef CONFIG_SPL_BUILD
1257/* The following code is for SPL */
Scott Wood2c1b7e12016-05-30 13:57:55 -05001258static struct mtd_info *mtd;
Bo Shen9415b872014-03-03 14:47:16 +08001259static struct nand_chip nand_chip;
1260
1261static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1262{
Scott Wood17fed142016-05-30 13:57:56 -05001263 struct nand_chip *this = mtd_to_nand(mtd);
Bo Shen9415b872014-03-03 14:47:16 +08001264 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1265 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1266 unsigned int ctrl) = this->cmd_ctrl;
1267
Scott Wood2c1b7e12016-05-30 13:57:55 -05001268 while (!this->dev_ready(mtd))
Bo Shen9415b872014-03-03 14:47:16 +08001269 ;
1270
1271 if (cmd == NAND_CMD_READOOB) {
1272 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1273 cmd = NAND_CMD_READ0;
1274 }
1275
Scott Wood2c1b7e12016-05-30 13:57:55 -05001276 hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
Bo Shen9415b872014-03-03 14:47:16 +08001277
Brian Norris67675222014-05-06 00:46:17 +05301278 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
Bo Shen9415b872014-03-03 14:47:16 +08001279 offs >>= 1;
1280
Scott Wood2c1b7e12016-05-30 13:57:55 -05001281 hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1282 hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1283 hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1284 hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
Bo Shen9415b872014-03-03 14:47:16 +08001285#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
Scott Wood2c1b7e12016-05-30 13:57:55 -05001286 hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
Bo Shen9415b872014-03-03 14:47:16 +08001287#endif
Scott Wood2c1b7e12016-05-30 13:57:55 -05001288 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
Bo Shen9415b872014-03-03 14:47:16 +08001289
Scott Wood2c1b7e12016-05-30 13:57:55 -05001290 hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1291 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
Bo Shen9415b872014-03-03 14:47:16 +08001292
Scott Wood2c1b7e12016-05-30 13:57:55 -05001293 while (!this->dev_ready(mtd))
Bo Shen9415b872014-03-03 14:47:16 +08001294 ;
1295
1296 return 0;
1297}
1298
1299static int nand_is_bad_block(int block)
1300{
Scott Wood17fed142016-05-30 13:57:56 -05001301 struct nand_chip *this = mtd_to_nand(mtd);
Bo Shen9415b872014-03-03 14:47:16 +08001302
1303 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1304
1305 if (this->options & NAND_BUSWIDTH_16) {
1306 if (readw(this->IO_ADDR_R) != 0xffff)
1307 return 1;
1308 } else {
1309 if (readb(this->IO_ADDR_R) != 0xff)
1310 return 1;
1311 }
1312
1313 return 0;
1314}
1315
1316#ifdef CONFIG_SPL_NAND_ECC
1317static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1318#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1319 CONFIG_SYS_NAND_ECCSIZE)
1320#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1321
1322static int nand_read_page(int block, int page, void *dst)
1323{
Scott Wood17fed142016-05-30 13:57:56 -05001324 struct nand_chip *this = mtd_to_nand(mtd);
Bo Shen9415b872014-03-03 14:47:16 +08001325 u_char ecc_calc[ECCTOTAL];
1326 u_char ecc_code[ECCTOTAL];
1327 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1328 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1329 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1330 int eccsteps = ECCSTEPS;
1331 int i;
1332 uint8_t *p = dst;
1333 nand_command(block, page, 0, NAND_CMD_READ0);
1334
1335 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1336 if (this->ecc.mode != NAND_ECC_SOFT)
Scott Wood2c1b7e12016-05-30 13:57:55 -05001337 this->ecc.hwctl(mtd, NAND_ECC_READ);
1338 this->read_buf(mtd, p, eccsize);
1339 this->ecc.calculate(mtd, p, &ecc_calc[i]);
Bo Shen9415b872014-03-03 14:47:16 +08001340 }
Scott Wood2c1b7e12016-05-30 13:57:55 -05001341 this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
Bo Shen9415b872014-03-03 14:47:16 +08001342
1343 for (i = 0; i < ECCTOTAL; i++)
1344 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1345
1346 eccsteps = ECCSTEPS;
1347 p = dst;
1348
1349 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
Scott Wood2c1b7e12016-05-30 13:57:55 -05001350 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
Bo Shen9415b872014-03-03 14:47:16 +08001351
1352 return 0;
1353}
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001354
1355int spl_nand_erase_one(int block, int page)
1356{
Scott Wood17fed142016-05-30 13:57:56 -05001357 struct nand_chip *this = mtd_to_nand(mtd);
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001358 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1359 unsigned int ctrl) = this->cmd_ctrl;
1360 int page_addr;
1361
1362 if (nand_chip.select_chip)
Scott Wood2c1b7e12016-05-30 13:57:55 -05001363 nand_chip.select_chip(mtd, 0);
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001364
1365 page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
Scott Wood2c1b7e12016-05-30 13:57:55 -05001366 hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001367 /* Row address */
Scott Wood2c1b7e12016-05-30 13:57:55 -05001368 hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1369 hwctrl(mtd, ((page_addr >> 8) & 0xff),
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001370 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1371#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1372 /* One more address cycle for devices > 128MiB */
Scott Wood2c1b7e12016-05-30 13:57:55 -05001373 hwctrl(mtd, (page_addr >> 16) & 0x0f,
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001374 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1375#endif
Scott Wood2c1b7e12016-05-30 13:57:55 -05001376 hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001377
Scott Wood2c1b7e12016-05-30 13:57:55 -05001378 while (!this->dev_ready(mtd))
Heiko Schocher4ff0c372014-10-31 08:31:02 +01001379 ;
1380
1381 nand_deselect();
1382
1383 return 0;
1384}
Bo Shen9415b872014-03-03 14:47:16 +08001385#else
1386static int nand_read_page(int block, int page, void *dst)
1387{
Scott Wood17fed142016-05-30 13:57:56 -05001388 struct nand_chip *this = mtd_to_nand(mtd);
Bo Shen9415b872014-03-03 14:47:16 +08001389
1390 nand_command(block, page, 0, NAND_CMD_READ0);
Scott Wood2c1b7e12016-05-30 13:57:55 -05001391 atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
Bo Shen9415b872014-03-03 14:47:16 +08001392
1393 return 0;
1394}
1395#endif /* CONFIG_SPL_NAND_ECC */
1396
Bo Shen9415b872014-03-03 14:47:16 +08001397int at91_nand_wait_ready(struct mtd_info *mtd)
1398{
Scott Wood17fed142016-05-30 13:57:56 -05001399 struct nand_chip *this = mtd_to_nand(mtd);
Bo Shen9415b872014-03-03 14:47:16 +08001400
1401 udelay(this->chip_delay);
1402
Heiko Schocherae2af0a2014-10-31 08:31:03 +01001403 return 1;
Bo Shen9415b872014-03-03 14:47:16 +08001404}
1405
1406int board_nand_init(struct nand_chip *nand)
1407{
1408 int ret = 0;
1409
1410 nand->ecc.mode = NAND_ECC_SOFT;
1411#ifdef CONFIG_SYS_NAND_DBW_16
1412 nand->options = NAND_BUSWIDTH_16;
1413 nand->read_buf = nand_read_buf16;
1414#else
1415 nand->read_buf = nand_read_buf;
1416#endif
1417 nand->cmd_ctrl = at91_nand_hwcontrol;
1418#ifdef CONFIG_SYS_NAND_READY_PIN
1419 nand->dev_ready = at91_nand_ready;
1420#else
1421 nand->dev_ready = at91_nand_wait_ready;
1422#endif
1423 nand->chip_delay = 20;
David Dueckab7ec112015-03-20 10:52:49 +01001424#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1425 nand->bbt_options |= NAND_BBT_USE_FLASH;
1426#endif
Bo Shen9415b872014-03-03 14:47:16 +08001427
1428#ifdef CONFIG_ATMEL_NAND_HWECC
1429#ifdef CONFIG_ATMEL_NAND_HW_PMECC
Scott Wood2c1b7e12016-05-30 13:57:55 -05001430 ret = atmel_pmecc_nand_init_params(nand, mtd);
Bo Shen9415b872014-03-03 14:47:16 +08001431#endif
1432#endif
1433
1434 return ret;
1435}
1436
1437void nand_init(void)
1438{
Boris Brezillon3b5f8842016-06-15 20:56:10 +02001439 mtd = nand_to_mtd(&nand_chip);
Scott Wood2c1b7e12016-05-30 13:57:55 -05001440 mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1441 mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
Bo Shen9415b872014-03-03 14:47:16 +08001442 nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1443 nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1444 board_nand_init(&nand_chip);
1445
1446#ifdef CONFIG_SPL_NAND_ECC
1447 if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1448 nand_chip.ecc.calculate = nand_calculate_ecc;
1449 nand_chip.ecc.correct = nand_correct_data;
1450 }
1451#endif
1452
1453 if (nand_chip.select_chip)
Scott Wood2c1b7e12016-05-30 13:57:55 -05001454 nand_chip.select_chip(mtd, 0);
Bo Shen9415b872014-03-03 14:47:16 +08001455}
1456
1457void nand_deselect(void)
1458{
1459 if (nand_chip.select_chip)
Scott Wood2c1b7e12016-05-30 13:57:55 -05001460 nand_chip.select_chip(mtd, -1);
Bo Shen9415b872014-03-03 14:47:16 +08001461}
1462
Ladislav Michlc6a42002017-04-16 15:31:59 +02001463#include "nand_spl_loaders.c"
1464
Bo Shen9415b872014-03-03 14:47:16 +08001465#else
1466
Wu, Josh6cded6d2012-08-23 00:05:34 +00001467#ifndef CONFIG_SYS_NAND_BASE_LIST
1468#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001469#endif
Wu, Josh6cded6d2012-08-23 00:05:34 +00001470static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1471static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1472
1473int atmel_nand_chip_init(int devnum, ulong base_addr)
1474{
1475 int ret;
Wu, Josh6cded6d2012-08-23 00:05:34 +00001476 struct nand_chip *nand = &nand_chip[devnum];
Scott Wood17fed142016-05-30 13:57:56 -05001477 struct mtd_info *mtd = nand_to_mtd(nand);
Wu, Josh6cded6d2012-08-23 00:05:34 +00001478
Wu, Josh6cded6d2012-08-23 00:05:34 +00001479 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001480
Bo Shenbb5a12f2013-08-28 14:54:26 +00001481#ifdef CONFIG_NAND_ECC_BCH
1482 nand->ecc.mode = NAND_ECC_SOFT_BCH;
1483#else
Sergey Lapin77e524c2008-10-31 12:28:43 +01001484 nand->ecc.mode = NAND_ECC_SOFT;
Bo Shenbb5a12f2013-08-28 14:54:26 +00001485#endif
Sergey Lapin77e524c2008-10-31 12:28:43 +01001486#ifdef CONFIG_SYS_NAND_DBW_16
1487 nand->options = NAND_BUSWIDTH_16;
1488#endif
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +01001489 nand->cmd_ctrl = at91_nand_hwcontrol;
1490#ifdef CONFIG_SYS_NAND_READY_PIN
1491 nand->dev_ready = at91_nand_ready;
1492#endif
Wu, Joshf9f69b12013-10-18 17:46:31 +08001493 nand->chip_delay = 75;
David Dueckab7ec112015-03-20 10:52:49 +01001494#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1495 nand->bbt_options |= NAND_BBT_USE_FLASH;
1496#endif
Sergey Lapin77e524c2008-10-31 12:28:43 +01001497
Wu, Josh6cded6d2012-08-23 00:05:34 +00001498 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1499 if (ret)
1500 return ret;
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001501
1502#ifdef CONFIG_ATMEL_NAND_HWECC
Wu, Joshfd3091d2012-08-23 00:05:36 +00001503#ifdef CONFIG_ATMEL_NAND_HW_PMECC
1504 ret = atmel_pmecc_nand_init_params(nand, mtd);
1505#else
Wu, Josh6cded6d2012-08-23 00:05:34 +00001506 ret = atmel_hwecc_nand_init_param(nand, mtd);
Wu, Joshfd3091d2012-08-23 00:05:36 +00001507#endif
Wu, Josh6cded6d2012-08-23 00:05:34 +00001508 if (ret)
1509 return ret;
1510#endif
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001511
Wu, Josh6cded6d2012-08-23 00:05:34 +00001512 ret = nand_scan_tail(mtd);
1513 if (!ret)
Scott Wood2c1b7e12016-05-30 13:57:55 -05001514 nand_register(devnum, mtd);
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001515
Wu, Josh6cded6d2012-08-23 00:05:34 +00001516 return ret;
1517}
Nikolay Petukhove6015ca2010-03-19 10:49:27 +05001518
Wu, Josh6cded6d2012-08-23 00:05:34 +00001519void board_nand_init(void)
1520{
1521 int i;
1522 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1523 if (atmel_nand_chip_init(i, base_addr[i]))
Sean Andersondfff1c12020-09-15 10:44:49 -04001524 log_err("atmel_nand: Fail to initialize #%d chip", i);
Sergey Lapin77e524c2008-10-31 12:28:43 +01001525}
Bo Shen9415b872014-03-03 14:47:16 +08001526#endif /* CONFIG_SPL_BUILD */