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Stelian Pop0bf5cad2008-05-08 18:52:25 +02001/*
2 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Pop0bf5cad2008-05-08 18:52:25 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * Configuation settings for the AT91SAM9RLEK board.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Stelian Pop0bf5cad2008-05-08 18:52:25 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Xu, Hong0c0fb212011-08-01 03:56:53 +000014#include <asm/hardware.h>
15
16#define CONFIG_SYS_TEXT_BASE 0x21F00000
Jens Scharsig128ecd02010-02-03 22:45:42 +010017
Stelian Pop0bf5cad2008-05-08 18:52:25 +020018/* ARM asynchronous clock */
Xu, Hong0c0fb212011-08-01 03:56:53 +000019#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
20#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
Stelian Pop0bf5cad2008-05-08 18:52:25 +020021
Xu, Hong0c0fb212011-08-01 03:56:53 +000022#define CONFIG_AT91SAM9RLEK 1 /* It's an AT91SAM9RLEK Board */
23
Jean-Christophe PLAGNIOL-VILLARD23164f12009-04-16 21:30:44 +020024#define CONFIG_ARCH_CPU_INIT
Xu, Hong0c0fb212011-08-01 03:56:53 +000025#define CONFIG_SKIP_LOWLEVEL_INIT
26#define CONFIG_BOARD_EARLY_INIT_F
Stelian Pop0bf5cad2008-05-08 18:52:25 +020027
Xu, Hong0c0fb212011-08-01 03:56:53 +000028#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
29#define CONFIG_SETUP_MEMORY_TAGS 1
30#define CONFIG_INITRD_TAG 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +020031
Xu, Hong0c0fb212011-08-01 03:56:53 +000032#define CONFIG_DISPLAY_CPUINFO
33
34#define CONFIG_ATMEL_LEGACY
35#define CONFIG_AT91_GPIO 1
36#define CONFIG_AT91_GPIO_PULLUP 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +020037
38/*
39 * Hardware drivers
40 */
Xu, Hong0c0fb212011-08-01 03:56:53 +000041
42/* serial console */
43#define CONFIG_ATMEL_USART
44#define CONFIG_USART_BASE ATMEL_BASE_DBGU
45#define CONFIG_USART_ID ATMEL_ID_SYS
46#define CONFIG_BAUDRATE 115200
Stelian Pop0bf5cad2008-05-08 18:52:25 +020047
Stelian Popcea5c532008-05-08 14:52:32 +020048/* LCD */
49#define CONFIG_LCD 1
50#define LCD_BPP LCD_COLOR8
51#define CONFIG_LCD_LOGO 1
52#undef LCD_TEST_PATTERN
53#define CONFIG_LCD_INFO 1
54#define CONFIG_LCD_INFO_BELOW_LOGO 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000055#define CONFIG_SYS_WHITE_ON_BLACK 1
Stelian Popcea5c532008-05-08 14:52:32 +020056#define CONFIG_ATMEL_LCD 1
57#define CONFIG_ATMEL_LCD_RGB565 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000058/* Let board_init_f handle the framebuffer allocation */
59#undef CONFIG_FB_ADDR
60#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
61
Jean-Christophe PLAGNIOL-VILLARD476d10e2009-03-21 21:08:00 +010062/* LED */
63#define CONFIG_AT91_LED
64#define CONFIG_RED_LED AT91_PIN_PD14 /* this is the power led */
65#define CONFIG_GREEN_LED AT91_PIN_PD15 /* this is the user1 led */
66#define CONFIG_YELLOW_LED AT91_PIN_PD16 /* this is the user2 led */
67
Stelian Pop0bf5cad2008-05-08 18:52:25 +020068#define CONFIG_BOOTDELAY 3
69
Stelian Pop0bf5cad2008-05-08 18:52:25 +020070/*
71 * Command line configuration.
72 */
Stelian Pop0bf5cad2008-05-08 18:52:25 +020073
Xu, Hong0c0fb212011-08-01 03:56:53 +000074#define CONFIG_CMD_NAND 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +020075
76/* SDRAM */
77#define CONFIG_NR_DRAM_BANKS 1
Xu, Hong0c0fb212011-08-01 03:56:53 +000078#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
79#define CONFIG_SYS_SDRAM_SIZE 0x04000000
80
81#define CONFIG_SYS_INIT_SP_ADDR \
82 (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
Stelian Pop0bf5cad2008-05-08 18:52:25 +020083
84/* DataFlash */
Jean-Christophe PLAGNIOL-VILLARDe5437ac2009-03-27 23:26:44 +010085#define CONFIG_ATMEL_DATAFLASH_SPI
Xu, Hong0c0fb212011-08-01 03:56:53 +000086#define CONFIG_HAS_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
88#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
Xu, Hong0c0fb212011-08-01 03:56:53 +000089#define AT91_SPI_CLK 15000000
90#define DATAFLASH_TCSS (0x1a << 16)
91#define DATAFLASH_TCHS (0x1 << 24)
Stelian Pop0bf5cad2008-05-08 18:52:25 +020092
93/* NOR flash - not present */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#define CONFIG_SYS_NO_FLASH 1
Stelian Pop0bf5cad2008-05-08 18:52:25 +020095
96/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +010097#ifdef CONFIG_CMD_NAND
98#define CONFIG_NAND_ATMEL
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_MAX_NAND_DEVICE 1
Xu, Hong0c0fb212011-08-01 03:56:53 +0000100#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_NAND_DBW_8 1
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100102/* our ALE is AD21 */
103#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
104/* our CLE is AD22 */
105#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
106#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
107#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
Wolfgang Denk1f797742009-07-18 21:52:24 +0200108
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100109#endif
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200110
Wu, Joshb12259b2015-02-02 17:51:00 +0800111/* MMC */
Wu, Joshb12259b2015-02-02 17:51:00 +0800112
113#ifdef CONFIG_CMD_MMC
114#define CONFIG_MMC
115#define CONFIG_GENERIC_MMC
116#define CONFIG_GENERIC_ATMEL_MCI
Wu, Joshb12259b2015-02-02 17:51:00 +0800117#define CONFIG_DOS_PARTITION
118#endif
119
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200120/* Ethernet - not present */
121
122/* USB - not supported */
123
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200124#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200125
Xu, Hong0c0fb212011-08-01 03:56:53 +0000126#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200128
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#ifdef CONFIG_SYS_USE_DATAFLASH
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200130
131/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Jean-Christophe PLAGNIOL-VILLARD2b14d2b2008-09-10 22:47:58 +0200132#define CONFIG_ENV_IS_IN_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200134#define CONFIG_ENV_OFFSET 0x4200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200136#define CONFIG_ENV_SIZE 0x4200
Alexandre Belloni9ef19ba2012-07-02 04:26:58 +0000137#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200138#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
139 "root=/dev/mtdblock0 " \
Albin Tonnerreeaa6db22009-07-22 18:30:03 +0200140 "mtdparts=atmel_nand:-(root) "\
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200141 "rw rootfstype=jffs2"
142
Wu, Josh7ff194f2015-02-02 17:51:01 +0800143#elif CONFIG_SYS_USE_NANDFLASH
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200144
145/* bootstrap + u-boot + env + linux in nandflash */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000146#define CONFIG_ENV_IS_IN_NAND 1
Wu, Joshf8e70d92015-02-03 11:38:30 +0800147#define CONFIG_ENV_OFFSET 0xc0000
148#define CONFIG_ENV_OFFSET_REDUND 0x100000
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200149#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
Wu, Joshf8e70d92015-02-03 11:38:30 +0800150#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x600000; " \
151 "nand read 0x21000000 0x180000 0x80000; " \
152 "bootz 0x22000000 - 0x21000000"
153#define CONFIG_BOOTARGS \
154 "console=ttyS0,115200 earlyprintk " \
155 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
Wu, Joshbdfcebb2015-04-30 18:22:02 +0800156 "256K(env),256k(env_redundent),256k(spare)," \
Wu, Joshf8e70d92015-02-03 11:38:30 +0800157 "512k(dtb),6M(kernel)ro,-(rootfs) " \
158 "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200159
Wu, Josh7ff194f2015-02-02 17:51:01 +0800160#else /* CONFIG_SYS_USE_MMC */
161
162/* bootstrap + u-boot + env + linux in mmc */
163#define CONFIG_ENV_IS_IN_FAT
164#define CONFIG_FAT_WRITE
165#define FAT_ENV_INTERFACE "mmc"
166#define FAT_ENV_FILE "uboot.env"
167#define FAT_ENV_DEVICE_AND_PART "0"
168#define CONFIG_ENV_SIZE 0x4000
169#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; " \
170 "fatload mmc 0:1 0x22000000 zImage; " \
171 "bootz 0x22000000 - 0x21000000"
172#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
173 "mtdparts=atmel_nand:" \
174 "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
175 "root=/dev/mmcblk0p2 rw rootwait"
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200176#endif
177
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178#define CONFIG_SYS_CBSIZE 256
179#define CONFIG_SYS_MAXARGS 16
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_LONGHELP 1
Xu, Hong0c0fb212011-08-01 03:56:53 +0000181#define CONFIG_CMDLINE_EDITING 1
Alexandre Belloni9ef19ba2012-07-02 04:26:58 +0000182#define CONFIG_AUTO_COMPLETE
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200183
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200184/*
185 * Size of malloc() pool
186 */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000187#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200188
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200189#endif