blob: 1f519219e7e641ff5465b10425acec63281e1001 [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2022 Nuvoton Technology Corp.
4 */
5
Jim Liu147c0002022-09-27 16:45:15 +08006#include <dm.h>
7#include <asm/io.h>
8#include <asm/arch/gcr.h>
Jim Liuc32c95c2023-11-14 16:51:59 +08009#include "../common/uart.h"
Jim Liu147c0002022-09-27 16:45:15 +080010
Jim Liuc5cc4bc2023-07-04 16:00:14 +080011#define SR_MII_CTRL_SWR_BIT15 15
12
13#define DRAM_512MB_ECC_SIZE 0x1C000000ULL
14#define DRAM_512MB_SIZE 0x20000000ULL
15#define DRAM_1GB_ECC_SIZE 0x38000000ULL
16#define DRAM_1GB_SIZE 0x40000000ULL
17#define DRAM_2GB_ECC_SIZE 0x70000000ULL
18#define DRAM_2GB_SIZE 0x80000000ULL
Jim Liu25efe152023-10-23 15:02:24 +080019#define DRAM_4GB_ECC_SIZE 0xE0000000ULL
Jim Liuc5cc4bc2023-07-04 16:00:14 +080020#define DRAM_4GB_SIZE 0x100000000ULL
21
Jim Liu147c0002022-09-27 16:45:15 +080022DECLARE_GLOBAL_DATA_PTR;
23
24int board_init(void)
25{
26 return 0;
27}
28
Jim Liua7fe44a2024-04-23 15:22:10 +080029phys_size_t get_effective_memsize(void)
30{
31 /* Use bank0 only */
32 if (gd->ram_size > DRAM_2GB_SIZE)
33 return DRAM_2GB_SIZE;
34
35 return gd->ram_size;
36}
37
Jim Liu147c0002022-09-27 16:45:15 +080038int dram_init(void)
39{
40 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
41
42 /*
Jim Liuc5cc4bc2023-07-04 16:00:14 +080043 * get dram active size value from bootblock.
44 * Value sent using scrpad_03 register.
45 * feature available in bootblock 0.0.6 and above.
Jim Liu147c0002022-09-27 16:45:15 +080046 */
Jim Liuc5cc4bc2023-07-04 16:00:14 +080047
48 gd->ram_size = readl(&gcr->scrpad_c);
Jim Liuc5cc4bc2023-07-04 16:00:14 +080049
Jim Liu25efe152023-10-23 15:02:24 +080050 if (gd->ram_size == 0)
Jim Liuc5cc4bc2023-07-04 16:00:14 +080051 gd->ram_size = readl(&gcr->scrpad_b);
Jim Liu25efe152023-10-23 15:02:24 +080052 else
Jim Liuc5cc4bc2023-07-04 16:00:14 +080053 gd->ram_size *= 0x100000ULL;
Jim Liuc5cc4bc2023-07-04 16:00:14 +080054
Jim Liuc5cc4bc2023-07-04 16:00:14 +080055 debug("ram_size: %llx ", gd->ram_size);
56
Jim Liu25efe152023-10-23 15:02:24 +080057 return 0;
58}
59
60int dram_init_banksize(void)
61{
62
63 gd->bd->bi_dram[0].start = 0;
64
Jim Liuc5cc4bc2023-07-04 16:00:14 +080065 switch (gd->ram_size) {
66 case DRAM_512MB_ECC_SIZE:
67 case DRAM_512MB_SIZE:
68 case DRAM_1GB_ECC_SIZE:
69 case DRAM_1GB_SIZE:
70 case DRAM_2GB_ECC_SIZE:
71 case DRAM_2GB_SIZE:
72 gd->bd->bi_dram[0].size = gd->ram_size;
73 gd->bd->bi_dram[1].start = 0;
74 gd->bd->bi_dram[1].size = 0;
75 break;
76 case DRAM_4GB_ECC_SIZE:
Jim Liu25efe152023-10-23 15:02:24 +080077 gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
Jim Liuc5cc4bc2023-07-04 16:00:14 +080078 gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
Jim Liu25efe152023-10-23 15:02:24 +080079 gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
80 (DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
Jim Liuc5cc4bc2023-07-04 16:00:14 +080081 break;
82 case DRAM_4GB_SIZE:
83 gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
84 gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
85 gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
Jim Liuc5cc4bc2023-07-04 16:00:14 +080086 break;
87 default:
88 gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
89 gd->bd->bi_dram[1].start = 0;
90 gd->bd->bi_dram[1].size = 0;
91 break;
92 }
93
Jim Liuc5cc4bc2023-07-04 16:00:14 +080094 return 0;
95}
96
Jim Liuc32c95c2023-11-14 16:51:59 +080097int last_stage_init(void)
98{
99 board_set_console();
100
101 return 0;
102}