blob: 53c931c3c2443647e8c3424e4e0c93086aff1a6a [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2022 Nuvoton Technology Corp.
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <asm/io.h>
9#include <asm/arch/gcr.h>
Jim Liuc32c95c2023-11-14 16:51:59 +080010#include "../common/uart.h"
Jim Liu147c0002022-09-27 16:45:15 +080011
Jim Liuc5cc4bc2023-07-04 16:00:14 +080012#define SR_MII_CTRL_SWR_BIT15 15
13
14#define DRAM_512MB_ECC_SIZE 0x1C000000ULL
15#define DRAM_512MB_SIZE 0x20000000ULL
16#define DRAM_1GB_ECC_SIZE 0x38000000ULL
17#define DRAM_1GB_SIZE 0x40000000ULL
18#define DRAM_2GB_ECC_SIZE 0x70000000ULL
19#define DRAM_2GB_SIZE 0x80000000ULL
Jim Liu25efe152023-10-23 15:02:24 +080020#define DRAM_4GB_ECC_SIZE 0xE0000000ULL
Jim Liuc5cc4bc2023-07-04 16:00:14 +080021#define DRAM_4GB_SIZE 0x100000000ULL
22
Jim Liu147c0002022-09-27 16:45:15 +080023DECLARE_GLOBAL_DATA_PTR;
24
25int board_init(void)
26{
27 return 0;
28}
29
Jim Liua7fe44a2024-04-23 15:22:10 +080030phys_size_t get_effective_memsize(void)
31{
32 /* Use bank0 only */
33 if (gd->ram_size > DRAM_2GB_SIZE)
34 return DRAM_2GB_SIZE;
35
36 return gd->ram_size;
37}
38
Jim Liu147c0002022-09-27 16:45:15 +080039int dram_init(void)
40{
41 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
42
43 /*
Jim Liuc5cc4bc2023-07-04 16:00:14 +080044 * get dram active size value from bootblock.
45 * Value sent using scrpad_03 register.
46 * feature available in bootblock 0.0.6 and above.
Jim Liu147c0002022-09-27 16:45:15 +080047 */
Jim Liuc5cc4bc2023-07-04 16:00:14 +080048
49 gd->ram_size = readl(&gcr->scrpad_c);
Jim Liuc5cc4bc2023-07-04 16:00:14 +080050
Jim Liu25efe152023-10-23 15:02:24 +080051 if (gd->ram_size == 0)
Jim Liuc5cc4bc2023-07-04 16:00:14 +080052 gd->ram_size = readl(&gcr->scrpad_b);
Jim Liu25efe152023-10-23 15:02:24 +080053 else
Jim Liuc5cc4bc2023-07-04 16:00:14 +080054 gd->ram_size *= 0x100000ULL;
Jim Liuc5cc4bc2023-07-04 16:00:14 +080055
Jim Liuc5cc4bc2023-07-04 16:00:14 +080056 debug("ram_size: %llx ", gd->ram_size);
57
Jim Liu25efe152023-10-23 15:02:24 +080058 return 0;
59}
60
61int dram_init_banksize(void)
62{
63
64 gd->bd->bi_dram[0].start = 0;
65
Jim Liuc5cc4bc2023-07-04 16:00:14 +080066 switch (gd->ram_size) {
67 case DRAM_512MB_ECC_SIZE:
68 case DRAM_512MB_SIZE:
69 case DRAM_1GB_ECC_SIZE:
70 case DRAM_1GB_SIZE:
71 case DRAM_2GB_ECC_SIZE:
72 case DRAM_2GB_SIZE:
73 gd->bd->bi_dram[0].size = gd->ram_size;
74 gd->bd->bi_dram[1].start = 0;
75 gd->bd->bi_dram[1].size = 0;
76 break;
77 case DRAM_4GB_ECC_SIZE:
Jim Liu25efe152023-10-23 15:02:24 +080078 gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
Jim Liuc5cc4bc2023-07-04 16:00:14 +080079 gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
Jim Liu25efe152023-10-23 15:02:24 +080080 gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
81 (DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
Jim Liuc5cc4bc2023-07-04 16:00:14 +080082 break;
83 case DRAM_4GB_SIZE:
84 gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
85 gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
86 gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
Jim Liuc5cc4bc2023-07-04 16:00:14 +080087 break;
88 default:
89 gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
90 gd->bd->bi_dram[1].start = 0;
91 gd->bd->bi_dram[1].size = 0;
92 break;
93 }
94
Jim Liuc5cc4bc2023-07-04 16:00:14 +080095 return 0;
96}
97
Jim Liuc32c95c2023-11-14 16:51:59 +080098int last_stage_init(void)
99{
100 board_set_console();
101
102 return 0;
103}