blob: e52e0a59abcd6d0733cd983898af6b61401f73de [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2022 Nuvoton Technology Corp.
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <asm/io.h>
9#include <asm/arch/gcr.h>
10
Jim Liuc5cc4bc2023-07-04 16:00:14 +080011#define SR_MII_CTRL_SWR_BIT15 15
12
13#define DRAM_512MB_ECC_SIZE 0x1C000000ULL
14#define DRAM_512MB_SIZE 0x20000000ULL
15#define DRAM_1GB_ECC_SIZE 0x38000000ULL
16#define DRAM_1GB_SIZE 0x40000000ULL
17#define DRAM_2GB_ECC_SIZE 0x70000000ULL
18#define DRAM_2GB_SIZE 0x80000000ULL
19#define DRAM_4GB_ECC_SIZE 0xE00000000ULL
20#define DRAM_4GB_SIZE 0x100000000ULL
21
Jim Liu147c0002022-09-27 16:45:15 +080022DECLARE_GLOBAL_DATA_PTR;
23
24int board_init(void)
25{
26 return 0;
27}
28
29int dram_init(void)
30{
31 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
Jim Liuc5cc4bc2023-07-04 16:00:14 +080032 uint64_t delta = 0ULL;
Jim Liu147c0002022-09-27 16:45:15 +080033
34 /*
Jim Liuc5cc4bc2023-07-04 16:00:14 +080035 * get dram active size value from bootblock.
36 * Value sent using scrpad_03 register.
37 * feature available in bootblock 0.0.6 and above.
Jim Liu147c0002022-09-27 16:45:15 +080038 */
Jim Liuc5cc4bc2023-07-04 16:00:14 +080039
40 gd->ram_size = readl(&gcr->scrpad_c);
41 debug("%s: scrpad_c: %llx ", __func__, gd->ram_size);
42
43 if (gd->ram_size == 0) {
44 gd->ram_size = readl(&gcr->scrpad_b);
45 debug("%s: scrpad_b: %llx ", __func__, gd->ram_size);
46 } else {
47 gd->ram_size *= 0x100000ULL;
48 }
49
50 gd->bd->bi_dram[0].start = 0;
51 debug("ram_size: %llx ", gd->ram_size);
52
53 switch (gd->ram_size) {
54 case DRAM_512MB_ECC_SIZE:
55 case DRAM_512MB_SIZE:
56 case DRAM_1GB_ECC_SIZE:
57 case DRAM_1GB_SIZE:
58 case DRAM_2GB_ECC_SIZE:
59 case DRAM_2GB_SIZE:
60 gd->bd->bi_dram[0].size = gd->ram_size;
61 gd->bd->bi_dram[1].start = 0;
62 gd->bd->bi_dram[1].size = 0;
63 break;
64 case DRAM_4GB_ECC_SIZE:
65 gd->bd->bi_dram[0].size = DRAM_2GB_ECC_SIZE;
66 gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
67 gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
68 delta = DRAM_4GB_SIZE - DRAM_2GB_ECC_SIZE;
69 break;
70 case DRAM_4GB_SIZE:
71 gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
72 gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
73 gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
74 delta = DRAM_4GB_SIZE - DRAM_2GB_SIZE;
75 break;
76 default:
77 gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
78 gd->bd->bi_dram[1].start = 0;
79 gd->bd->bi_dram[1].size = 0;
80 break;
81 }
82
83 gd->ram_size -= delta;
84
85 return 0;
86}
87
88int dram_init_banksize(void)
89{
90 dram_init();
Jim Liu147c0002022-09-27 16:45:15 +080091
92 return 0;
93}