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git01.mediatek.com / filogic / uboot / 8246ae0786d722f7a3d44ae53d422ca26177dd5c / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: 04ca989b0e7a977344cd571a55960eebbc29d7dc [file] [log] [blame]
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
26/* Number of TLB CAM entries we have on FSL Book-E chips */
27#if defined(CONFIG_E500MC)
28#define CONFIG_SYS_NUM_TLBCAMS 64
29#elif defined(CONFIG_E500)
30#define CONFIG_SYS_NUM_TLBCAMS 16
31#endif
32
33#if defined(CONFIG_MPC8536)
34#define CONFIG_MAX_CPUS 1
35#define CONFIG_SYS_FSL_NUM_LAWS 12
36#define CONFIG_SYS_FSL_SEC_COMPAT 2
37
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]38#elif defined(CONFIG_MPC8540)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]39#define CONFIG_MAX_CPUS 1
40#define CONFIG_SYS_FSL_NUM_LAWS 8
41
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]42#elif defined(CONFIG_MPC8541)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]43#define CONFIG_MAX_CPUS 1
44#define CONFIG_SYS_FSL_NUM_LAWS 8
45#define CONFIG_SYS_FSL_SEC_COMPAT 2
46
47#elif defined(CONFIG_MPC8544)
48#define CONFIG_MAX_CPUS 1
49#define CONFIG_SYS_FSL_NUM_LAWS 10
50#define CONFIG_SYS_FSL_SEC_COMPAT 2
51
52#elif defined(CONFIG_MPC8548)
53#define CONFIG_MAX_CPUS 1
54#define CONFIG_SYS_FSL_NUM_LAWS 10
55#define CONFIG_SYS_FSL_SEC_COMPAT 2
56
57#elif defined(CONFIG_MPC8555)
58#define CONFIG_MAX_CPUS 1
59#define CONFIG_SYS_FSL_NUM_LAWS 8
60#define CONFIG_SYS_FSL_SEC_COMPAT 2
61
62#elif defined(CONFIG_MPC8560)
63#define CONFIG_MAX_CPUS 1
64#define CONFIG_SYS_FSL_NUM_LAWS 8
65
66#elif defined(CONFIG_MPC8568)
67#define CONFIG_MAX_CPUS 1
68#define CONFIG_SYS_FSL_NUM_LAWS 10
69#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]70#define QE_MURAM_SIZE 0x10000UL
71#define MAX_QE_RISC 2
72#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]73
74#elif defined(CONFIG_MPC8569)
75#define CONFIG_MAX_CPUS 1
76#define CONFIG_SYS_FSL_NUM_LAWS 10
77#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]78#define QE_MURAM_SIZE 0x20000UL
79#define MAX_QE_RISC 4
80#define QE_NUM_OF_SNUM 46
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]81
82#elif defined(CONFIG_MPC8572)
83#define CONFIG_MAX_CPUS 2
84#define CONFIG_SYS_FSL_NUM_LAWS 12
85#define CONFIG_SYS_FSL_SEC_COMPAT 2
York Sun9aa857b2011-01-25 21:51:27 -0800[diff] [blame]86#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sunc8fc9592011-01-25 22:05:49 -0800[diff] [blame]87#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]88
89#elif defined(CONFIG_P1010)
90#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]91#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]92#define CONFIG_SYS_FSL_NUM_LAWS 12
93#define CONFIG_TSECV2
94#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]95#define CONFIG_FSL_SATA_V2
96#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
97#define CONFIG_NUM_DDR_CONTROLLERS 1
98#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]99#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]100
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]101/* P1011 is single core version of P1020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]102#elif defined(CONFIG_P1011)
103#define CONFIG_MAX_CPUS 1
104#define CONFIG_SYS_FSL_NUM_LAWS 12
105#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]106#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]107#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]108#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
109#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]110
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]111/* P1012 is single core version of P1021 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]112#elif defined(CONFIG_P1012)
113#define CONFIG_MAX_CPUS 1
114#define CONFIG_SYS_FSL_NUM_LAWS 12
115#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]116#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]117#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]118#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
119#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]120#define QE_MURAM_SIZE 0x6000UL
121#define MAX_QE_RISC 1
122#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]123
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]124/* P1013 is single core version of P1022 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]125#elif defined(CONFIG_P1013)
126#define CONFIG_MAX_CPUS 1
127#define CONFIG_SYS_FSL_NUM_LAWS 12
128#define CONFIG_TSECV2
129#define CONFIG_SYS_FSL_SEC_COMPAT 2
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]130#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
131#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
132#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]133
134#elif defined(CONFIG_P1014)
135#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]136#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]137#define CONFIG_SYS_FSL_NUM_LAWS 12
138#define CONFIG_TSECV2
139#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]140#define CONFIG_FSL_SATA_V2
141#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
142#define CONFIG_NUM_DDR_CONTROLLERS 1
143#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]144
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]145/* P1015 is single core version of P1024 */
146#elif defined(CONFIG_P1015)
147#define CONFIG_MAX_CPUS 1
148#define CONFIG_SYS_FSL_NUM_LAWS 12
149#define CONFIG_TSECV2
150#define CONFIG_FSL_PCIE_DISABLE_ASPM
151#define CONFIG_SYS_FSL_SEC_COMPAT 2
152#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
153#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
154
155/* P1016 is single core version of P1025 */
156#elif defined(CONFIG_P1016)
157#define CONFIG_MAX_CPUS 1
158#define CONFIG_SYS_FSL_NUM_LAWS 12
159#define CONFIG_TSECV2
160#define CONFIG_FSL_PCIE_DISABLE_ASPM
161#define CONFIG_SYS_FSL_SEC_COMPAT 2
162#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
163#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]164#define QE_MURAM_SIZE 0x6000UL
165#define MAX_QE_RISC 1
166#define QE_NUM_OF_SNUM 28
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]167
168/* P1017 is single core version of P1023 */
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]169#elif defined(CONFIG_P1017)
170#define CONFIG_MAX_CPUS 1
171#define CONFIG_SYS_FSL_NUM_LAWS 12
172#define CONFIG_SYS_FSL_SEC_COMPAT 4
173#define CONFIG_SYS_NUM_FMAN 1
174#define CONFIG_SYS_NUM_FM1_DTSEC 2
175#define CONFIG_NUM_DDR_CONTROLLERS 1
176#define CONFIG_SYS_QMAN_NUM_PORTALS 3
177#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]178#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]179#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]180
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]181#elif defined(CONFIG_P1020)
182#define CONFIG_MAX_CPUS 2
183#define CONFIG_SYS_FSL_NUM_LAWS 12
184#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]185#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]186#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]187#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
188#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]189
190#elif defined(CONFIG_P1021)
191#define CONFIG_MAX_CPUS 2
192#define CONFIG_SYS_FSL_NUM_LAWS 12
193#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]194#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]195#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]196#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
197#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]198#define QE_MURAM_SIZE 0x6000UL
199#define MAX_QE_RISC 1
200#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]201
202#elif defined(CONFIG_P1022)
203#define CONFIG_MAX_CPUS 2
204#define CONFIG_SYS_FSL_NUM_LAWS 12
205#define CONFIG_TSECV2
206#define CONFIG_SYS_FSL_SEC_COMPAT 2
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]207#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
208#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
209#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]210
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]211#elif defined(CONFIG_P1023)
212#define CONFIG_MAX_CPUS 2
213#define CONFIG_SYS_FSL_NUM_LAWS 12
214#define CONFIG_SYS_FSL_SEC_COMPAT 4
215#define CONFIG_SYS_NUM_FMAN 1
216#define CONFIG_SYS_NUM_FM1_DTSEC 2
217#define CONFIG_NUM_DDR_CONTROLLERS 1
218#define CONFIG_SYS_QMAN_NUM_PORTALS 3
219#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]220#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]221#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]222
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]223/* P1024 is lower end variant of P1020 */
224#elif defined(CONFIG_P1024)
225#define CONFIG_MAX_CPUS 2
226#define CONFIG_SYS_FSL_NUM_LAWS 12
227#define CONFIG_TSECV2
228#define CONFIG_FSL_PCIE_DISABLE_ASPM
229#define CONFIG_SYS_FSL_SEC_COMPAT 2
230#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
231#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
232
233/* P1025 is lower end variant of P1021 */
234#elif defined(CONFIG_P1025)
235#define CONFIG_MAX_CPUS 2
236#define CONFIG_SYS_FSL_NUM_LAWS 12
237#define CONFIG_TSECV2
238#define CONFIG_FSL_PCIE_DISABLE_ASPM
239#define CONFIG_SYS_FSL_SEC_COMPAT 2
240#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
241#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]242#define QE_MURAM_SIZE 0x6000UL
243#define MAX_QE_RISC 1
244#define QE_NUM_OF_SNUM 28
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]245
246/* P2010 is single core version of P2020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]247#elif defined(CONFIG_P2010)
248#define CONFIG_MAX_CPUS 1
249#define CONFIG_SYS_FSL_NUM_LAWS 12
250#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]251#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]252#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]253
254#elif defined(CONFIG_P2020)
255#define CONFIG_MAX_CPUS 2
256#define CONFIG_SYS_FSL_NUM_LAWS 12
257#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]258#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]259#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]260
261#elif defined(CONFIG_PPC_P2040)
262#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]263#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]264#define CONFIG_SYS_FSL_NUM_LAWS 32
265#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]266#define CONFIG_SYS_NUM_FMAN 1
267#define CONFIG_SYS_NUM_FM1_DTSEC 5
268#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]269#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]270#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]271#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]272#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
273#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]274#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]275
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]276#elif defined(CONFIG_PPC_P2041)
277#define CONFIG_MAX_CPUS 4
278#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
279#define CONFIG_SYS_FSL_NUM_LAWS 32
280#define CONFIG_SYS_FSL_SEC_COMPAT 4
281#define CONFIG_SYS_NUM_FMAN 1
282#define CONFIG_SYS_NUM_FM1_DTSEC 5
283#define CONFIG_SYS_NUM_FM1_10GEC 1
284#define CONFIG_NUM_DDR_CONTROLLERS 1
285#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
286#define CONFIG_SYS_FSL_TBCLK_DIV 32
287#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
288#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
289#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
290#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
291
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]292#elif defined(CONFIG_PPC_P3041)
293#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]294#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]295#define CONFIG_SYS_FSL_NUM_LAWS 32
296#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]297#define CONFIG_SYS_NUM_FMAN 1
298#define CONFIG_SYS_NUM_FM1_DTSEC 5
299#define CONFIG_SYS_NUM_FM1_10GEC 1
300#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]301#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]302#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]303#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]304#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
305#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]306#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]307
308#elif defined(CONFIG_PPC_P4040)
309#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]310#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]311#define CONFIG_SYS_FSL_NUM_LAWS 32
312#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]313#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]314#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]315#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]316
317#elif defined(CONFIG_PPC_P4080)
318#define CONFIG_MAX_CPUS 8
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]319#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]320#define CONFIG_SYS_FSL_NUM_LAWS 32
321#define CONFIG_SYS_FSL_SEC_COMPAT 4
322#define CONFIG_SYS_NUM_FMAN 2
323#define CONFIG_SYS_NUM_FM1_DTSEC 4
324#define CONFIG_SYS_NUM_FM2_DTSEC 4
325#define CONFIG_SYS_NUM_FM1_10GEC 1
326#define CONFIG_SYS_NUM_FM2_10GEC 1
327#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]328#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]329#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]330#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]331#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
332#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun922f40f2011-01-10 12:03:01 +0000[diff] [blame]333#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]334#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
335#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
336#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
337#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
338#define CONFIG_SYS_P4080_ERRATUM_CPU22
339#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medveb01c81f2010-08-31 22:57:38 -0500[diff] [blame]340#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi6a62dc42011-04-18 17:16:00 -0500[diff] [blame]341#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi90f381d2011-04-01 13:19:36 -0500[diff] [blame]342#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]343
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]344/* P5010 is single core version of P5020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]345#elif defined(CONFIG_PPC_P5010)
346#define CONFIG_MAX_CPUS 1
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]347#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]348#define CONFIG_SYS_FSL_NUM_LAWS 32
349#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]350#define CONFIG_SYS_NUM_FMAN 1
351#define CONFIG_SYS_NUM_FM1_DTSEC 5
352#define CONFIG_SYS_NUM_FM1_10GEC 1
353#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]354#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]355#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]356#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]357#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
358#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]359#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]360
361#elif defined(CONFIG_PPC_P5020)
362#define CONFIG_MAX_CPUS 2
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]363#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]364#define CONFIG_SYS_FSL_NUM_LAWS 32
365#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]366#define CONFIG_SYS_NUM_FMAN 1
367#define CONFIG_SYS_NUM_FM1_DTSEC 5
368#define CONFIG_SYS_NUM_FM1_10GEC 1
369#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]370#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]371#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]372#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]373#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
374#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]375#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]376
377#else
378#error Processor type not defined for this platform
379#endif
380
381#endif /* _ASM_MPC85xx_CONFIG_H_ */