Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 8156f113033a4706756226504de5950a8f8e72b0 / . / arch / arm / dts / tegra186.dtsi
blob: 25e1e8dfc0355b318fca161f3c36830b4e23f11a [file] [log] [blame]
Stephen Warren03667eb2016-05-12 13:32:55 -0600[diff] [blame]1#include "skeleton.dtsi"
Stephen Warren8156f112016-07-27 15:24:51 -0600[diff] [blame^]2#include <dt-bindings/clock/tegra186-clock.h>
Stephen Warren0a6002f2016-07-18 12:15:03 -0600[diff] [blame]3#include <dt-bindings/gpio/tegra186-gpio.h>
Stephen Warren03667eb2016-05-12 13:32:55 -0600[diff] [blame]4#include <dt-bindings/interrupt-controller/arm-gic.h>
Stephen Warrenc5317312016-07-27 15:24:49 -0600[diff] [blame]5#include <dt-bindings/mailbox/tegra186-hsp.h>
Stephen Warren8156f112016-07-27 15:24:51 -0600[diff] [blame^]6#include <dt-bindings/reset/tegra186-reset.h>
Stephen Warren03667eb2016-05-12 13:32:55 -0600[diff] [blame]7
8/ {
9 compatible = "nvidia,tegra186";
10 #address-cells = <2>;
11 #size-cells = <2>;
12
Stephen Warren8156f112016-07-27 15:24:51 -0600[diff] [blame^]13 gpio_main: gpio@2200000 {
Stephen Warren03667eb2016-05-12 13:32:55 -0600[diff] [blame]14 compatible = "nvidia,tegra186-gpio";
15 reg-names = "security", "gpio";
16 reg =
17 <0x0 0x2200000 0x0 0x10000>,
18 <0x0 0x2210000 0x0 0x10000>;
19 interrupts =
20 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
21 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
22 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
23 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
24 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
25 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
26 gpio-controller;
27 #gpio-cells = <2>;
28 interrupt-controller;
29 #interrupt-cells = <2>;
30 };
31
32 uarta: serial@3100000 {
33 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
34 reg = <0x0 0x03100000 0x0 0x10000>;
35 reg-shift = <2>;
36 status = "disabled";
37 };
38
Stephen Warren8156f112016-07-27 15:24:51 -0600[diff] [blame^]39 sdhci@3400000 {
40 compatible = "nvidia,tegra186-sdhci";
41 reg = <0x0 0x03400000 0x0 0x200>;
42 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
43 reset-names = "sdmmc";
44 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
45 clock-names = "sdmmc";
46 interrupts = <GIC_SPI 62 0x04>;
47 status = "disabled";
48 };
49
Stephen Warren03667eb2016-05-12 13:32:55 -0600[diff] [blame]50 sdhci@3460000 {
51 compatible = "nvidia,tegra186-sdhci";
52 reg = <0x0 0x03460000 0x0 0x200>;
Stephen Warren8156f112016-07-27 15:24:51 -0600[diff] [blame^]53 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
54 reset-names = "sdmmc";
55 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
56 clock-names = "sdmmc";
Stephen Warren03667eb2016-05-12 13:32:55 -0600[diff] [blame]57 interrupts = <GIC_SPI 31 0x04>;
58 status = "disabled";
59 };
60
Stephen Warrene0e2b262016-06-17 09:43:57 -0600[diff] [blame]61 hsp: hsp@3c00000 {
62 compatible = "nvidia,tegra186-hsp";
63 reg = <0x0 0x03c00000 0x0 0xa0000>;
64 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warrenc5317312016-07-27 15:24:49 -0600[diff] [blame]65 interrupt-names = "doorbell";
66 #mbox-cells = <2>;
Stephen Warrene0e2b262016-06-17 09:43:57 -0600[diff] [blame]67 };
68
Stephen Warren8156f112016-07-27 15:24:51 -0600[diff] [blame^]69 gpio_aon: gpio@c2f0000 {
Stephen Warren03667eb2016-05-12 13:32:55 -0600[diff] [blame]70 compatible = "nvidia,tegra186-gpio-aon";
71 reg-names = "security", "gpio";
72 reg =
73 <0x0 0xc2f0000 0x0 0x1000>,
74 <0x0 0xc2f1000 0x0 0x1000>;
75 interrupts =
76 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
77 gpio-controller;
78 #gpio-cells = <2>;
79 interrupt-controller;
80 #interrupt-cells = <2>;
81 };
Stephen Warren8156f112016-07-27 15:24:51 -0600[diff] [blame^]82
83 sysram@30000000 {
84 compatible = "nvidia,tegra186-sysram", "mmio-sram";
85 reg = <0x0 0x30000000 0x0 0x50000>;
86 #address-cells = <2>;
87 #size-cells = <2>;
88 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
89
90 sysram_cpu_bpmp_tx: shmem@4e000 {
91 compatible = "nvidia,tegra186-bpmp-shmem";
92 reg = <0x0 0x4e000 0x0 0x1000>;
93 };
94
95 sysram_cpu_bpmp_rx: shmem@4f000 {
96 compatible = "nvidia,tegra186-bpmp-shmem";
97 reg = <0x0 0x4f000 0x0 0x1000>;
98 };
99 };
100
101 bpmp: bpmp {
102 compatible = "nvidia,tegra186-bpmp";
103 mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>;
104 /*
105 * In theory, these references, and the configuration in the
106 * node these reference point at, are board-specific, since
107 * they depend on the BCT's memory carve-out setup, the
108 * firmware that's actually loaded onto the BPMP, etc. However,
109 * in practice, all boards are likely to use identical values.
110 */
111 shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>;
112 #clock-cells = <1>;
113 #power-domain-cells = <1>;
114 #reset-cells = <1>;
115 };
Stephen Warren03667eb2016-05-12 13:32:55 -0600[diff] [blame]116};