| Rick Chen | 842d580 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 1 | config RISCV_NDS |
| Bin Meng | 4b284ad | 2018-12-12 06:12:28 -0800 | [diff] [blame] | 2 | bool |
| Rick Chen | 14a1075 | 2019-04-02 15:56:41 +0800 | [diff] [blame] | 3 | select ARCH_EARLY_INIT_R |
| 4 | imply CPU |
| 5 | imply CPU_RISCV |
| 6 | imply RISCV_TIMER |
| 7 | imply ANDES_PLIC if RISCV_MMODE |
| 8 | imply ANDES_PLMT if RISCV_MMODE |
| Bin Meng | 4b284ad | 2018-12-12 06:12:28 -0800 | [diff] [blame] | 9 | help |
| 10 | Run U-Boot on AndeStar V5 platforms and use some specific features |
| 11 | which are provided by Andes Technology AndeStar V5 families. |
| 12 | |
| 13 | if RISCV_NDS |
| 14 | |
| 15 | config RISCV_NDS_CACHE |
| 16 | bool "AndeStar V5 families specific cache support" |
| Rick Chen | f71410a | 2019-04-02 15:56:42 +0800 | [diff] [blame] | 17 | depends on RISCV_MMODE |
| Rick Chen | 842d580 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 18 | help |
| Bin Meng | 4b284ad | 2018-12-12 06:12:28 -0800 | [diff] [blame] | 19 | Provide Andes Technology AndeStar V5 families specific cache support. |
| 20 | |
| 21 | endif |