Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Rick Chen | e76b804 | 2017-12-26 13:55:48 +0800 | [diff] [blame] | 2 | /* |
Yu Chien Peter Lin | 82f0f53 | 2023-02-06 16:10:47 +0800 | [diff] [blame] | 3 | * Copyright (C) 2023 Andes Technology Corporation |
Rick Chen | e76b804 | 2017-12-26 13:55:48 +0800 | [diff] [blame] | 4 | * Rick Chen, Andes Technology Corporation <rick@andestech.com> |
Rick Chen | e76b804 | 2017-12-26 13:55:48 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* CPU specific code */ |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 8 | #include <cpu_func.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 9 | #include <irq_func.h> |
Rick Chen | 842d580 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 10 | #include <asm/cache.h> |
Leo Yu-Chi Liang | 2795bf2 | 2021-09-23 10:34:29 +0800 | [diff] [blame] | 11 | #include <asm/csr.h> |
Yu Chien Peter Lin | 82f0f53 | 2023-02-06 16:10:47 +0800 | [diff] [blame] | 12 | #include <asm/arch-andes/csr.h> |
Rick Chen | e76b804 | 2017-12-26 13:55:48 +0800 | [diff] [blame] | 13 | |
| 14 | /* |
| 15 | * cleanup_before_linux() is called just before we call linux |
| 16 | * it prepares the processor for linux |
| 17 | * |
| 18 | * we disable interrupt and caches. |
| 19 | */ |
| 20 | int cleanup_before_linux(void) |
| 21 | { |
| 22 | disable_interrupts(); |
| 23 | |
Rick Chen | 842d580 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 24 | cache_flush(); |
Rick Chen | e76b804 | 2017-12-26 13:55:48 +0800 | [diff] [blame] | 25 | |
| 26 | return 0; |
| 27 | } |
Leo Yu-Chi Liang | 2795bf2 | 2021-09-23 10:34:29 +0800 | [diff] [blame] | 28 | |
| 29 | void harts_early_init(void) |
| 30 | { |
Yu Chien Peter Lin | 82f0f53 | 2023-02-06 16:10:47 +0800 | [diff] [blame] | 31 | /* Enable I/D-cache in SPL */ |
Leo Yu-Chi Liang | 2795bf2 | 2021-09-23 10:34:29 +0800 | [diff] [blame] | 32 | if (CONFIG_IS_ENABLED(RISCV_MMODE)) { |
Yu Chien Peter Lin | 82f0f53 | 2023-02-06 16:10:47 +0800 | [diff] [blame] | 33 | unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); |
Leo Yu-Chi Liang | 96e75a8 | 2023-12-26 14:17:34 +0800 | [diff] [blame] | 34 | unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL); |
Leo Yu-Chi Liang | 2795bf2 | 2021-09-23 10:34:29 +0800 | [diff] [blame] | 35 | |
Leo Yu-Chi Liang | 96e75a8 | 2023-12-26 14:17:34 +0800 | [diff] [blame] | 36 | mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \ |
| 37 | MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ |
Leo Yu-Chi Liang | 7862a2a | 2023-12-26 14:17:35 +0800 | [diff] [blame^] | 38 | MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \ |
| 39 | MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN); |
Leo Yu-Chi Liang | 1eb9f91 | 2023-12-26 14:17:33 +0800 | [diff] [blame] | 40 | |
| 41 | if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) |
| 42 | mcache_ctl_val |= MCACHE_CTL_IC_EN; |
| 43 | |
| 44 | if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) |
| 45 | mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN); |
Yu Chien Peter Lin | 82f0f53 | 2023-02-06 16:10:47 +0800 | [diff] [blame] | 46 | |
Leo Yu-Chi Liang | 2795bf2 | 2021-09-23 10:34:29 +0800 | [diff] [blame] | 47 | csr_write(CSR_MCACHE_CTL, mcache_ctl_val); |
| 48 | |
Leo Yu-Chi Liang | 1eb9f91 | 2023-12-26 14:17:33 +0800 | [diff] [blame] | 49 | if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { |
| 50 | /* |
| 51 | * Check mcache_ctl.DC_COHEN, we assume this platform does |
| 52 | * not support CM if the bit is hard-wired to 0. |
| 53 | */ |
| 54 | if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { |
| 55 | /* Wait for DC_COHSTA bit to be set */ |
| 56 | while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); |
| 57 | } |
Leo Yu-Chi Liang | 2795bf2 | 2021-09-23 10:34:29 +0800 | [diff] [blame] | 58 | } |
Leo Yu-Chi Liang | 96e75a8 | 2023-12-26 14:17:34 +0800 | [diff] [blame] | 59 | |
| 60 | mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN; |
| 61 | |
| 62 | csr_write(CSR_MMISC_CTL, mmisc_ctl_val); |
Leo Yu-Chi Liang | 2795bf2 | 2021-09-23 10:34:29 +0800 | [diff] [blame] | 63 | } |
| 64 | } |