Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 756bf0ef4bab765e29cd3cb70bac8b1aaa014378 / . / arch / arm / dts / k3-am642-sk-u-boot.dtsi
blob: 7e6b2981346637e0d3d32794395c53ad17de6125 [file] [log] [blame]
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9a1b2712023-07-22 00:14:34 +0530[diff] [blame]6#include "k3-am64x-binman.dtsi"
7
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]8/ {
9 chosen {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]10 tick-timer = &main_timer0;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]11 };
12};
13
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]14&main_timer0 {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]15 clock-frequency = <200000000>;
16};
17
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]18&dmsc {
Suman Anna91eda102021-05-13 20:10:57 -0500[diff] [blame]19 k3_sysreset: sysreset-controller {
20 compatible = "ti,sci-sysreset";
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]21 bootph-all;
Suman Anna91eda102021-05-13 20:10:57 -0500[diff] [blame]22 };
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]23};
24
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]25&sdhci0 {
Aswath Govindrajua15380e2021-07-26 20:58:03 +0530[diff] [blame]26 status = "disabled";
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]27};
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]28
Roger Quadrosc9b17ae2023-09-29 16:46:44 +0300[diff] [blame]29&inta_main_dmss {
30 bootph-all;
31};
32
Roger Quadrosc9b17ae2023-09-29 16:46:44 +0300[diff] [blame]33&mdio1_pins_default {
34 bootph-all;
35};
36
37&cpsw3g_mdio {
38 bootph-all;
39};
40
41&cpsw3g_phy0 {
42 bootph-all;
43};
44
45&cpsw3g_phy1 {
46 bootph-all;
47};
48
49&rgmii1_pins_default {
50 bootph-all;
51};
52
53&rgmii2_pins_default {
54 bootph-all;
55};
56
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]57&cpsw3g {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]58 bootph-all;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]59
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]60 ethernet-ports {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]61 bootph-all;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]62 };
63};
64
Roger Quadrosc9b17ae2023-09-29 16:46:44 +0300[diff] [blame]65&phy_gmii_sel {
66 bootph-all;
67};
68
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]69&cpsw_port2 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]70 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]71};
72
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]73&main_bcdma {
Siddharth Vadapallie4f41ae2023-10-28 20:36:03 +0300[diff] [blame]74 reg = <0x00 0x485c0100 0x00 0x100>,
75 <0x00 0x4c000000 0x00 0x20000>,
76 <0x00 0x4a820000 0x00 0x20000>,
77 <0x00 0x4aa40000 0x00 0x20000>,
78 <0x00 0x4bc00000 0x00 0x100000>,
79 <0x00 0x48600000 0x00 0x8000>,
80 <0x00 0x484a4000 0x00 0x2000>,
81 <0x00 0x484c2000 0x00 0x2000>;
82 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
83 "cfg", "tchan", "rchan";
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]84 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]85};
86
87&main_pktdma {
Siddharth Vadapallie4f41ae2023-10-28 20:36:03 +0300[diff] [blame]88 reg = <0x00 0x485c0000 0x00 0x100>,
89 <0x00 0x4a800000 0x00 0x20000>,
90 <0x00 0x4aa00000 0x00 0x40000>,
91 <0x00 0x4b800000 0x00 0x400000>,
92 <0x00 0x485e0000 0x00 0x20000>,
93 <0x00 0x484a0000 0x00 0x4000>,
94 <0x00 0x484c0000 0x00 0x2000>,
95 <0x00 0x48430000 0x00 0x4000>;
96 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
97 "tchan", "rchan", "rflow";
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]98 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]99};
100
101&rgmii1_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]102 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]103};
104
105&rgmii2_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]106 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]107};
108
109&mdio1_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]110 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]111};
112
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]113&cpsw3g_phy1 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]114 bootph-all;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]115};
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]116
Roger Quadros672caea2024-01-31 15:33:48 +0200[diff] [blame]117&serdes_ln_ctrl {
118 bootph-all;
119};
120
Jonathan Humphreyse1ce4f42024-02-23 18:17:02 -0600[diff] [blame]121&ospi0_pins_default {
122 bootph-all;
123};
124
125&fss {
126 bootph-all;
127};
128
129&ospi0 {
130 bootph-all;
131
132 flash@0 {
133 bootph-all;
134 };
135};