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wdenk0f8c9762002-08-19 11:57:05 +00001/*
Stefan Roese3e1f1b32005-08-01 16:49:12 +02002 * (C) Copyright 2000-2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
wdenk0f8c9762002-08-19 11:57:05 +00004 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk0f8c9762002-08-19 11:57:05 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405GP 1 /* This is a PPC405 CPU */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020021#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020022 /* ...or on a SYCAMORE board */
23
24#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
wdenk0f8c9762002-08-19 11:57:05 +000025
Stefan Roesecfe58022008-06-06 15:55:21 +020026/*
27 * Include common defines/options for all AMCC eval boards
28 */
29#define CONFIG_HOSTNAME walnut
30#include "amcc-common.h"
31
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020032#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
wdenk0f8c9762002-08-19 11:57:05 +000033
Stefan Roesecfe58022008-06-06 15:55:21 +020034/*
35 * Default environment variables
36 */
37#define CONFIG_EXTRA_ENV_SETTINGS \
38 CONFIG_AMCC_DEF_ENV \
39 CONFIG_AMCC_DEF_ENV_POWERPC \
40 CONFIG_AMCC_DEF_ENV_PPC_OLD \
41 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese3e1f1b32005-08-01 16:49:12 +020042 "kernel_addr=fff80000\0" \
43 "ramdisk_addr=fff80000\0" \
Stefan Roese3e1f1b32005-08-01 16:49:12 +020044 ""
wdenk0f8c9762002-08-19 11:57:05 +000045
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020046#define CONFIG_PHY_ADDR 1 /* PHY address */
Stefan Roesea98dfe62008-05-08 11:05:15 +020047#define CONFIG_HAS_ETH0 1
Stefan Roeseb0ff2142006-08-07 14:33:32 +020048
wdenk0f8c9762002-08-19 11:57:05 +000049#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
50
Jon Loeliger5c4ddae2007-07-10 10:12:10 -050051/*
Stefan Roesecfe58022008-06-06 15:55:21 +020052 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger03bfcb92007-07-04 22:33:46 -050053 */
Jon Loeliger03bfcb92007-07-04 22:33:46 -050054#define CONFIG_CMD_DATE
Jon Loeliger03bfcb92007-07-04 22:33:46 -050055#define CONFIG_CMD_PCI
Jon Loeliger03bfcb92007-07-04 22:33:46 -050056#define CONFIG_CMD_SDRAM
Jon Loeliger03bfcb92007-07-04 22:33:46 -050057
wdenk0f8c9762002-08-19 11:57:05 +000058#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
59
60/*
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
62 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
63 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
wdenk0f8c9762002-08-19 11:57:05 +000064 * The Linux BASE_BAUD define should match this configuration.
65 * baseBaud = cpuClock/(uartDivisor*16)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020066 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
wdenk0f8c9762002-08-19 11:57:05 +000067 * set Linux BASE_BAUD to 403200.
68 */
Stefan Roese3ddce572010-09-20 16:05:31 +020069#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
71#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
72#define CONFIG_SYS_BASE_BAUD 691200
wdenk0f8c9762002-08-19 11:57:05 +000073
Stefan Roese3e1f1b32005-08-01 16:49:12 +020074/*-----------------------------------------------------------------------
75 * I2C stuff
76 *-----------------------------------------------------------------------
77 */
Dirk Eibach42b204f2013-04-25 02:40:01 +000078#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
wdenk0f8c9762002-08-19 11:57:05 +000079
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
81#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
82#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
83#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roeseb0ff2142006-08-07 14:33:32 +020084
wdenk0f8c9762002-08-19 11:57:05 +000085/*-----------------------------------------------------------------------
86 * PCI stuff
87 *-----------------------------------------------------------------------
88 */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020089#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
90#define PCI_HOST_FORCE 1 /* configure as pci host */
91#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenk0f8c9762002-08-19 11:57:05 +000092
Gabor Juhosb4458732013-05-30 07:06:12 +000093#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020094#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020095 /* resource configuration */
Stefan Roese3e1f1b32005-08-01 16:49:12 +020096#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
wdenk0f8c9762002-08-19 11:57:05 +000097
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
99#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
100#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
101#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
102#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
103#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
104#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
105#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk0f8c9762002-08-19 11:57:05 +0000106
107/*-----------------------------------------------------------------------
wdenk0f8c9762002-08-19 11:57:05 +0000108 * Start addresses for the final memory configuration
109 * (Set up by the startup code)
wdenk0f8c9762002-08-19 11:57:05 +0000110 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111#define CONFIG_SYS_FLASH_BASE 0xFFF80000
wdenk0f8c9762002-08-19 11:57:05 +0000112
113/*
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200114 * Define here the location of the environment variables (FLASH or NVRAM).
115 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200116 * supported for backward compatibility.
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200117 */
118#if 1
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200119#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200120#else
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +0200121#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200122#endif
123
wdenk0f8c9762002-08-19 11:57:05 +0000124/*-----------------------------------------------------------------------
125 * FLASH organization
126 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200128#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200129
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
131#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000132
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
134#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200137
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_FLASH_ADDR0 0x5555
139#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
140#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200141
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200142#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200143#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200145#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200146
147/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200148#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
149#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200150#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200151
wdenk0f8c9762002-08-19 11:57:05 +0000152/*-----------------------------------------------------------------------
153 * NVRAM organization
154 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
156#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
wdenk0f8c9762002-08-19 11:57:05 +0000157
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +0200158#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200159#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
160#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200161 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
wdenk0f8c9762002-08-19 11:57:05 +0000162#endif
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200163
wdenk0f8c9762002-08-19 11:57:05 +0000164/*-----------------------------------------------------------------------
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200165 * External Bus Controller (EBC) Setup
wdenk0f8c9762002-08-19 11:57:05 +0000166 */
167
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200168/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200169#define CONFIG_SYS_EBC_PB0AP 0x9B015480
170#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200171
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_EBC_PB1AP 0x02815480
173#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200174
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_EBC_PB2AP 0x04815A80
176#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000177
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178#define CONFIG_SYS_EBC_PB3AP 0x01815280
179#define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000180
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181#define CONFIG_SYS_EBC_PB7AP 0x01815280
182#define CONFIG_SYS_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000183
184/*-----------------------------------------------------------------------
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200185 * External peripheral base address
186 *-----------------------------------------------------------------------
187 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200188#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
189#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
190#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200191
192/*-----------------------------------------------------------------------
193 * Definitions for initial stack pointer and data area
wdenk0f8c9762002-08-19 11:57:05 +0000194 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
wdenk0f8c9762002-08-19 11:57:05 +0000196
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200198#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200199#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000201
202/*-----------------------------------------------------------------------
203 * Definitions for Serial Presence Detect EEPROM address
204 * (to get SDRAM settings)
205 */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200206#define SPD_EEPROM_ADDRESS 0x50
wdenk0f8c9762002-08-19 11:57:05 +0000207
wdenk0f8c9762002-08-19 11:57:05 +0000208#endif /* __CONFIG_H */