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wdenk0f8c9762002-08-19 11:57:05 +00001/*
Stefan Roese3e1f1b32005-08-01 16:49:12 +02002 * (C) Copyright 2000-2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
wdenk0f8c9762002-08-19 11:57:05 +00004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020039 /* ...or on a SYCAMORE board */
40
41#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
wdenk0f8c9762002-08-19 11:57:05 +000042
Stefan Roesecfe58022008-06-06 15:55:21 +020043/*
44 * Include common defines/options for all AMCC eval boards
45 */
46#define CONFIG_HOSTNAME walnut
47#include "amcc-common.h"
48
wdenkda55c6e2004-01-20 23:12:12 +000049#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenk0f8c9762002-08-19 11:57:05 +000050
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020051#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
wdenk0f8c9762002-08-19 11:57:05 +000052
Stefan Roesecfe58022008-06-06 15:55:21 +020053/*
54 * Default environment variables
55 */
56#define CONFIG_EXTRA_ENV_SETTINGS \
57 CONFIG_AMCC_DEF_ENV \
58 CONFIG_AMCC_DEF_ENV_POWERPC \
59 CONFIG_AMCC_DEF_ENV_PPC_OLD \
60 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese3e1f1b32005-08-01 16:49:12 +020061 "kernel_addr=fff80000\0" \
62 "ramdisk_addr=fff80000\0" \
Stefan Roese3e1f1b32005-08-01 16:49:12 +020063 ""
wdenk0f8c9762002-08-19 11:57:05 +000064
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020065#define CONFIG_PHY_ADDR 1 /* PHY address */
Stefan Roesea98dfe62008-05-08 11:05:15 +020066#define CONFIG_HAS_ETH0 1
Stefan Roeseb0ff2142006-08-07 14:33:32 +020067
wdenk0f8c9762002-08-19 11:57:05 +000068#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
69
Jon Loeliger5c4ddae2007-07-10 10:12:10 -050070/*
Stefan Roesecfe58022008-06-06 15:55:21 +020071 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger03bfcb92007-07-04 22:33:46 -050072 */
Jon Loeliger03bfcb92007-07-04 22:33:46 -050073#define CONFIG_CMD_DATE
Jon Loeliger03bfcb92007-07-04 22:33:46 -050074#define CONFIG_CMD_PCI
Jon Loeliger03bfcb92007-07-04 22:33:46 -050075#define CONFIG_CMD_SDRAM
76#define CONFIG_CMD_SNTP
77
wdenk0f8c9762002-08-19 11:57:05 +000078#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
79
80/*
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
82 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
83 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
wdenk0f8c9762002-08-19 11:57:05 +000084 * The Linux BASE_BAUD define should match this configuration.
85 * baseBaud = cpuClock/(uartDivisor*16)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
wdenk0f8c9762002-08-19 11:57:05 +000087 * set Linux BASE_BAUD to 403200.
88 */
Stefan Roese3ddce572010-09-20 16:05:31 +020089#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
91#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
92#define CONFIG_SYS_BASE_BAUD 691200
wdenk0f8c9762002-08-19 11:57:05 +000093
Stefan Roese3e1f1b32005-08-01 16:49:12 +020094/*-----------------------------------------------------------------------
95 * I2C stuff
96 *-----------------------------------------------------------------------
97 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
wdenk0f8c9762002-08-19 11:57:05 +000099
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_I2C_MULTI_EEPROMS
101#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
102#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
103#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
104#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roeseb0ff2142006-08-07 14:33:32 +0200105
wdenk0f8c9762002-08-19 11:57:05 +0000106/*-----------------------------------------------------------------------
107 * PCI stuff
108 *-----------------------------------------------------------------------
109 */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200110#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
111#define PCI_HOST_FORCE 1 /* configure as pci host */
112#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenk0f8c9762002-08-19 11:57:05 +0000113
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200114#define CONFIG_PCI /* include pci support */
115#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
116#define CONFIG_PCI_PNP /* do pci plug-and-play */
117 /* resource configuration */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200118#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
wdenk0f8c9762002-08-19 11:57:05 +0000119
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
121#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
122#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
123#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
124#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
125#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
126#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
127#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk0f8c9762002-08-19 11:57:05 +0000128
129/*-----------------------------------------------------------------------
wdenk0f8c9762002-08-19 11:57:05 +0000130 * Start addresses for the final memory configuration
131 * (Set up by the startup code)
wdenk0f8c9762002-08-19 11:57:05 +0000132 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_BASE 0xFFF80000
wdenk0f8c9762002-08-19 11:57:05 +0000134
135/*
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200136 * Define here the location of the environment variables (FLASH or NVRAM).
137 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200138 * supported for backward compatibility.
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200139 */
140#if 1
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200141#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200142#else
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +0200143#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200144#endif
145
wdenk0f8c9762002-08-19 11:57:05 +0000146/*-----------------------------------------------------------------------
147 * FLASH organization
148 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200150#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200151
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
153#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000154
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
156#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000157
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200159
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160#define CONFIG_SYS_FLASH_ADDR0 0x5555
161#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
162#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200163
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200164#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200165#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200167#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200168
169/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200170#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
171#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200172#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200173
wdenk0f8c9762002-08-19 11:57:05 +0000174/*-----------------------------------------------------------------------
175 * NVRAM organization
176 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
178#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
wdenk0f8c9762002-08-19 11:57:05 +0000179
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +0200180#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200181#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
182#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
wdenk0f8c9762002-08-19 11:57:05 +0000184#endif
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200185
wdenk0f8c9762002-08-19 11:57:05 +0000186/*-----------------------------------------------------------------------
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200187 * External Bus Controller (EBC) Setup
wdenk0f8c9762002-08-19 11:57:05 +0000188 */
189
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200190/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200191#define CONFIG_SYS_EBC_PB0AP 0x9B015480
192#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200193
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194#define CONFIG_SYS_EBC_PB1AP 0x02815480
195#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200196
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#define CONFIG_SYS_EBC_PB2AP 0x04815A80
198#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000199
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_EBC_PB3AP 0x01815280
201#define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000202
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#define CONFIG_SYS_EBC_PB7AP 0x01815280
204#define CONFIG_SYS_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000205
206/*-----------------------------------------------------------------------
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200207 * External peripheral base address
208 *-----------------------------------------------------------------------
209 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
211#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
212#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200213
214/*-----------------------------------------------------------------------
215 * Definitions for initial stack pointer and data area
wdenk0f8c9762002-08-19 11:57:05 +0000216 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200217#define CONFIG_SYS_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
wdenk0f8c9762002-08-19 11:57:05 +0000218
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200219#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200220#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200221#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000223
224/*-----------------------------------------------------------------------
225 * Definitions for Serial Presence Detect EEPROM address
226 * (to get SDRAM settings)
227 */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200228#define SPD_EEPROM_ADDRESS 0x50
wdenk0f8c9762002-08-19 11:57:05 +0000229
wdenk0f8c9762002-08-19 11:57:05 +0000230#endif /* __CONFIG_H */