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wdenk0f8c9762002-08-19 11:57:05 +00001/*
Stefan Roese3e1f1b32005-08-01 16:49:12 +02002 * (C) Copyright 2000-2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
wdenk0f8c9762002-08-19 11:57:05 +00004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
39 /* ...and on a SYCAMORE board */
wdenk0f8c9762002-08-19 11:57:05 +000040
wdenkda55c6e2004-01-20 23:12:12 +000041#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenk0f8c9762002-08-19 11:57:05 +000042
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020043#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
wdenk0f8c9762002-08-19 11:57:05 +000044
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020045#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk1baed662008-03-03 12:16:44 +010046 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Stefan Roese3e1f1b32005-08-01 16:49:12 +020047 "echo"
wdenk0f8c9762002-08-19 11:57:05 +000048
Stefan Roese3e1f1b32005-08-01 16:49:12 +020049#undef CONFIG_BOOTARGS
wdenk0f8c9762002-08-19 11:57:05 +000050
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020051#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese3e1f1b32005-08-01 16:49:12 +020052 "netdev=eth0\0" \
53 "hostname=walnut\0" \
54 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010055 "nfsroot=${serverip}:${rootpath}\0" \
Stefan Roese3e1f1b32005-08-01 16:49:12 +020056 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010057 "addip=setenv bootargs ${bootargs} " \
58 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
59 ":${hostname}:${netdev}:off panic=1\0" \
60 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
Stefan Roese3e1f1b32005-08-01 16:49:12 +020061 "flash_nfs=run nfsargs addip addtty;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010062 "bootm ${kernel_addr}\0" \
Stefan Roese3e1f1b32005-08-01 16:49:12 +020063 "flash_self=run ramargs addip addtty;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010064 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
65 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020066 "bootm\0" \
Stefan Roese3e1f1b32005-08-01 16:49:12 +020067 "rootpath=/opt/eldk/ppc_4xx\0" \
68 "bootfile=/tftpboot/walnut/uImage\0" \
69 "kernel_addr=fff80000\0" \
70 "ramdisk_addr=fff80000\0" \
Stefan Roesea05e1992007-02-07 16:51:08 +010071 "initrd_high=30000000\0" \
Stefan Roese3e1f1b32005-08-01 16:49:12 +020072 "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \
73 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020074 "cp.b 100000 fffc0000 40000;" \
Stefan Roese3e1f1b32005-08-01 16:49:12 +020075 "setenv filesize;saveenv\0" \
Detlev Zundel406e5782008-03-06 16:45:53 +010076 "upd=run load update\0" \
Stefan Roese3e1f1b32005-08-01 16:49:12 +020077 ""
78#define CONFIG_BOOTCOMMAND "run net_nfs"
wdenk0f8c9762002-08-19 11:57:05 +000079
wdenk0f8c9762002-08-19 11:57:05 +000080#if 0
Stefan Roese3e1f1b32005-08-01 16:49:12 +020081#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
wdenk0f8c9762002-08-19 11:57:05 +000082#else
Stefan Roese3e1f1b32005-08-01 16:49:12 +020083#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk0f8c9762002-08-19 11:57:05 +000084#endif
85
Stefan Roese3e1f1b32005-08-01 16:49:12 +020086#define CONFIG_BAUDRATE 115200
wdenk0f8c9762002-08-19 11:57:05 +000087
88#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
89#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
90
91#define CONFIG_MII 1 /* MII PHY management */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +020092#define CONFIG_PHY_ADDR 1 /* PHY address */
wdenk0f8c9762002-08-19 11:57:05 +000093
Stefan Roeseb0ff2142006-08-07 14:33:32 +020094#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
Stefan Roesea98dfe62008-05-08 11:05:15 +020095#define CONFIG_HAS_ETH0 1
Stefan Roeseb0ff2142006-08-07 14:33:32 +020096
97#define CONFIG_NETCONSOLE /* include NetConsole support */
98#define CONFIG_NET_MULTI /* needed for NetConsole */
99
wdenk0f8c9762002-08-19 11:57:05 +0000100#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
101
wdenk0f8c9762002-08-19 11:57:05 +0000102
Jon Loeliger03bfcb92007-07-04 22:33:46 -0500103/*
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500104 * BOOTP options
105 */
106#define CONFIG_BOOTP_BOOTFILESIZE
107#define CONFIG_BOOTP_BOOTPATH
108#define CONFIG_BOOTP_GATEWAY
109#define CONFIG_BOOTP_HOSTNAME
110
111
112/*
Jon Loeliger03bfcb92007-07-04 22:33:46 -0500113 * Command line configuration.
114 */
115#include <config_cmd_default.h>
116
117#define CONFIG_CMD_ASKENV
118#define CONFIG_CMD_DATE
119#define CONFIG_CMD_DHCP
120#define CONFIG_CMD_DIAG
121#define CONFIG_CMD_EEPROM
122#define CONFIG_CMD_ELF
123#define CONFIG_CMD_I2C
124#define CONFIG_CMD_IRQ
125#define CONFIG_CMD_MII
126#define CONFIG_CMD_NET
127#define CONFIG_CMD_NFS
128#define CONFIG_CMD_PCI
129#define CONFIG_CMD_PING
130#define CONFIG_CMD_REGINFO
131#define CONFIG_CMD_SDRAM
132#define CONFIG_CMD_SNTP
133
wdenk0f8c9762002-08-19 11:57:05 +0000134
135#undef CONFIG_WATCHDOG /* watchdog disabled */
136
137#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
138
139/*
140 * Miscellaneous configurable options
141 */
142#define CFG_LONGHELP /* undef to save memory */
143#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger03bfcb92007-07-04 22:33:46 -0500144#if defined(CONFIG_CMD_KGDB)
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200145#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000146#else
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200147#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000148#endif
149#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
150#define CFG_MAXARGS 16 /* max number of command args */
151#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
152
153#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
154#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
155
156/*
157 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
158 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
159 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
160 * The Linux BASE_BAUD define should match this configuration.
161 * baseBaud = cpuClock/(uartDivisor*16)
162 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
163 * set Linux BASE_BAUD to 403200.
164 */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200165#undef CONFIG_SERIAL_SOFTWARE_FIFO
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200166#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
167#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
168#define CFG_BASE_BAUD 691200
wdenk0f8c9762002-08-19 11:57:05 +0000169
170/* The following table includes the supported baudrates */
171#define CFG_BAUDRATE_TABLE \
172 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
173
174#define CFG_LOAD_ADDR 0x100000 /* default load address */
175#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
176
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200177#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000178
Stefan Roeseb0ff2142006-08-07 14:33:32 +0200179#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200180#define CONFIG_LOOPW 1 /* enable loopw command */
Stefan Roeseb0ff2142006-08-07 14:33:32 +0200181#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200182#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
183#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
184
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200185/*-----------------------------------------------------------------------
186 * I2C stuff
187 *-----------------------------------------------------------------------
188 */
wdenk0f8c9762002-08-19 11:57:05 +0000189#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200190#undef CONFIG_SOFT_I2C /* I2C bit-banged */
wdenk0f8c9762002-08-19 11:57:05 +0000191#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
192#define CFG_I2C_SLAVE 0x7F
193
Stefan Roeseb0ff2142006-08-07 14:33:32 +0200194#define CFG_I2C_MULTI_EEPROMS
195#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
196#define CFG_I2C_EEPROM_ADDR_LEN 1
197#define CFG_EEPROM_PAGE_WRITE_ENABLE
198#define CFG_EEPROM_PAGE_WRITE_BITS 3
199#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
200
wdenk0f8c9762002-08-19 11:57:05 +0000201/*-----------------------------------------------------------------------
202 * PCI stuff
203 *-----------------------------------------------------------------------
204 */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200205#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
206#define PCI_HOST_FORCE 1 /* configure as pci host */
207#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenk0f8c9762002-08-19 11:57:05 +0000208
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200209#define CONFIG_PCI /* include pci support */
210#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
211#define CONFIG_PCI_PNP /* do pci plug-and-play */
212 /* resource configuration */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200213#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
wdenk0f8c9762002-08-19 11:57:05 +0000214
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200215#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
216#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200217#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
218#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
219#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
220#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
221#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
222#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk0f8c9762002-08-19 11:57:05 +0000223
224/*-----------------------------------------------------------------------
wdenk0f8c9762002-08-19 11:57:05 +0000225 * Start addresses for the final memory configuration
226 * (Set up by the startup code)
227 * Please note that CFG_SDRAM_BASE _must_ start at 0
228 */
229#define CFG_SDRAM_BASE 0x00000000
230#define CFG_FLASH_BASE 0xFFF80000
wdenkbf2f8c92003-05-22 22:52:13 +0000231#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
wdenk0f8c9762002-08-19 11:57:05 +0000232#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200233#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
wdenk0f8c9762002-08-19 11:57:05 +0000234
235/*
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200236 * Define here the location of the environment variables (FLASH or NVRAM).
237 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200238 * supported for backward compatibility.
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200239 */
240#if 1
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200241#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200242#else
243#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
244#endif
245
246/*
wdenk0f8c9762002-08-19 11:57:05 +0000247 * For booting Linux, the board info and command line data
248 * have to be in the first 8 MB of memory, since this is
249 * the maximum mapped by the Linux kernel during initialization.
250 */
251#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200252
wdenk0f8c9762002-08-19 11:57:05 +0000253/*-----------------------------------------------------------------------
254 * FLASH organization
255 */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200256#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
257#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200258
wdenk0f8c9762002-08-19 11:57:05 +0000259#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
260#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
261
262#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
263#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
264
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200265#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
266
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200267#define CFG_FLASH_ADDR0 0x5555
268#define CFG_FLASH_ADDR1 0x2aaa
269#define CFG_FLASH_WORD_SIZE unsigned char
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200270
wdenk0f8c9762002-08-19 11:57:05 +0000271#ifdef CFG_ENV_IS_IN_FLASH
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200272#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200273#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200274#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200275
276/* Address and size of Redundant Environment Sector */
277#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
278#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
279#endif /* CFG_ENV_IS_IN_FLASH */
280
wdenk0f8c9762002-08-19 11:57:05 +0000281/*-----------------------------------------------------------------------
282 * NVRAM organization
283 */
284#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
285#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
286
287#ifdef CFG_ENV_IS_IN_NVRAM
288#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
289#define CFG_ENV_ADDR \
290 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
291#endif
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200292
wdenk0f8c9762002-08-19 11:57:05 +0000293/*-----------------------------------------------------------------------
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200294 * External Bus Controller (EBC) Setup
wdenk0f8c9762002-08-19 11:57:05 +0000295 */
296
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200297/* Memory Bank 0 (Flash Bank 0) initialization */
298#define CFG_EBC_PB0AP 0x9B015480
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200299#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200300
301#define CFG_EBC_PB1AP 0x02815480
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200302#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200303
304#define CFG_EBC_PB2AP 0x04815A80
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200305#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000306
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200307#define CFG_EBC_PB3AP 0x01815280
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200308#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000309
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200310#define CFG_EBC_PB7AP 0x01815280
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200311#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000312
313/*-----------------------------------------------------------------------
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200314 * External peripheral base address
315 *-----------------------------------------------------------------------
316 */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200317#define CFG_KEY_REG_BASE_ADDR 0xF0100000
318#define CFG_IR_REG_BASE_ADDR 0xF0200000
319#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
Stefan Roese3e1f1b32005-08-01 16:49:12 +0200320
321/*-----------------------------------------------------------------------
322 * Definitions for initial stack pointer and data area
wdenk0f8c9762002-08-19 11:57:05 +0000323 */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200324#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
wdenk0f8c9762002-08-19 11:57:05 +0000325
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200326#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
327#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
wdenk0f8c9762002-08-19 11:57:05 +0000328#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
329#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200330#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000331
332/*-----------------------------------------------------------------------
333 * Definitions for Serial Presence Detect EEPROM address
334 * (to get SDRAM settings)
335 */
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +0200336#define SPD_EEPROM_ADDRESS 0x50
wdenk0f8c9762002-08-19 11:57:05 +0000337
338/*
339 * Internal Definitions
340 *
341 * Boot Flags
342 */
343#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
344#define BOOTFLAG_WARM 0x02 /* Software reboot */
345
Jon Loeliger03bfcb92007-07-04 22:33:46 -0500346#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000347#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
348#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
349#endif
Stefan Roesea98dfe62008-05-08 11:05:15 +0200350
351/* pass open firmware flat tree */
352#define CONFIG_OF_LIBFDT 1
353#define CONFIG_OF_BOARD_SETUP 1
354
wdenk0f8c9762002-08-19 11:57:05 +0000355#endif /* __CONFIG_H */