Blame - arch/arm/mach-socfpga/Kconfig - filogic/uboot

blob: 5e87371f8ca84dcc5d95c71cdb369a980a57da2b [file] [log] [blame]

Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	1	if ARCH_SOCFPGA
				2
Dalon Westergreen	8d770f4	2017-02-10 17:15:34 -0800	[diff] [blame]	3	config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
				4	default 0xa2
				5
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	6	config TARGET_SOCFPGA_ARRIA5
				7	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame]	8	select TARGET_SOCFPGA_GEN5
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	9
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	10	config TARGET_SOCFPGA_ARRIA10
				11	bool
Tien Fong Chee	4d447a5	2017-12-05 15:58:03 +0800	[diff] [blame]	12	select ALTERA_SDRAM
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	13	select SPL_BOARD_INIT if SPL
Marek Vasut	e1dcd62	2018-07-30 15:56:19 +0200	[diff] [blame]	14	select CLK
				15	select SPL_CLK if SPL
Marek Vasut	69fbb88	2018-08-13 18:32:38 +0200	[diff] [blame]	16	select DM_I2C
Marek Vasut	700b2c6	2018-08-13 18:32:38 +0200	[diff] [blame]	17	select DM_RESET
				18	select SPL_DM_RESET if SPL
Marek Vasut	04c8f4f	2018-08-13 20:06:46 +0200	[diff] [blame]	19	select REGMAP
				20	select SPL_REGMAP if SPL
				21	select SYSCON
				22	select SPL_SYSCON if SPL
				23	select ETH_DESIGNWARE_SOCFPGA
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	24
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	25	config TARGET_SOCFPGA_CYCLONE5
				26	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame]	27	select TARGET_SOCFPGA_GEN5
				28
				29	config TARGET_SOCFPGA_GEN5
				30	bool
Ley Foon Tan	016539e	2017-04-05 17:32:51 +0800	[diff] [blame]	31	select ALTERA_SDRAM
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	32
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	33	config TARGET_SOCFPGA_STRATIX10
				34	bool
				35	select ARMV8_MULTIENTRY
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	36	select ARMV8_SET_SMPEN
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	37	select ARMV8_SPIN_TABLE
Ang, Chee Hong	da9640e	2018-12-19 18:35:16 -0800	[diff] [blame]	38	select FPGA_STRATIX10
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	39
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	40	choice
				41	prompt "Altera SOCFPGA board select"
Joe Hershberger	f069960	2015-05-12 14:46:23 -0500	[diff] [blame]	42	optional
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	43
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	44	config TARGET_SOCFPGA_ARRIA10_SOCDK
				45	bool "Altera SOCFPGA SoCDK (Arria 10)"
				46	select TARGET_SOCFPGA_ARRIA10
				47
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	48	config TARGET_SOCFPGA_ARRIA5_SOCDK
				49	bool "Altera SOCFPGA SoCDK (Arria V)"
				50	select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	51
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	52	config TARGET_SOCFPGA_CYCLONE5_SOCDK
				53	bool "Altera SOCFPGA SoCDK (Cyclone V)"
				54	select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	55
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame]	56	config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
				57	bool "Devboards DBM-SoC1 (Cyclone V)"
				58	select TARGET_SOCFPGA_CYCLONE5
				59
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	60	config TARGET_SOCFPGA_EBV_SOCRATES
				61	bool "EBV SoCrates (Cyclone V)"
				62	select TARGET_SOCFPGA_CYCLONE5
				63
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	64	config TARGET_SOCFPGA_IS1
				65	bool "IS1 (Cyclone V)"
				66	select TARGET_SOCFPGA_CYCLONE5
				67
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	68	config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
				69	bool "samtec VIN\|ING FPGA (Cyclone V)"
Tom Rini	22d567e	2017-01-22 19:43:11 -0500	[diff] [blame]	70	select BOARD_LATE_INIT
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	71	select TARGET_SOCFPGA_CYCLONE5
				72
Marek Vasut	2e717ec	2016-06-08 02:57:05 +0200	[diff] [blame]	73	config TARGET_SOCFPGA_SR1500
				74	bool "SR1500 (Cyclone V)"
				75	select TARGET_SOCFPGA_CYCLONE5
				76
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	77	config TARGET_SOCFPGA_STRATIX10_SOCDK
				78	bool "Intel SOCFPGA SoCDK (Stratix 10)"
				79	select TARGET_SOCFPGA_STRATIX10
				80
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	81	config TARGET_SOCFPGA_TERASIC_DE0_NANO
				82	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
				83	select TARGET_SOCFPGA_CYCLONE5
				84
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	85	config TARGET_SOCFPGA_TERASIC_DE10_NANO
				86	bool "Terasic DE10-Nano (Cyclone V)"
				87	select TARGET_SOCFPGA_CYCLONE5
				88
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	89	config TARGET_SOCFPGA_TERASIC_DE1_SOC
				90	bool "Terasic DE1-SoC (Cyclone V)"
				91	select TARGET_SOCFPGA_CYCLONE5
				92
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	93	config TARGET_SOCFPGA_TERASIC_SOCKIT
				94	bool "Terasic SoCkit (Cyclone V)"
				95	select TARGET_SOCFPGA_CYCLONE5
				96
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	97	endchoice
				98
				99	config SYS_BOARD
Marek Vasut	3f4c561	2015-08-10 21:24:53 +0200	[diff] [blame]	100	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	101	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	3f4c561	2015-08-10 21:24:53 +0200	[diff] [blame]	102	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame]	103	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	104	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	105	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	106	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	107	default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	108	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	109	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	110	default "sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	111	default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	112	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	113
				114	config SYS_VENDOR
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	115	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	116	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	117	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	118	default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame]	119	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	120	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	121	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	122	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	123	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	124	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	125	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	126
				127	config SYS_SOC
				128	default "socfpga"
				129
				130	config SYS_CONFIG_NAME
Dinh Nguyen	16f6ffd	2015-09-22 17:01:32 -0500	[diff] [blame]	131	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	132	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Dinh Nguyen	16f6ffd	2015-09-22 17:01:32 -0500	[diff] [blame]	133	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame]	134	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	135	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	136	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	137	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	138	default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	139	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	140	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	141	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	142	default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	143	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	144
				145	endif