Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 1 | /*- |
| 2 | * Copyright (c) 2007-2008, Juniper Networks, Inc. |
Remy Böhmer | 33e8748 | 2008-12-13 22:51:58 +0100 | [diff] [blame] | 3 | * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 4 | * All rights reserved. |
| 5 | * |
Simon Glass | 1b2e365 | 2015-07-06 16:47:42 -0600 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0 |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef USB_EHCI_H |
| 10 | #define USB_EHCI_H |
| 11 | |
Marek Vasut | fd349a1 | 2013-07-10 03:16:31 +0200 | [diff] [blame] | 12 | #include <usb.h> |
| 13 | |
Remy Böhmer | 33e8748 | 2008-12-13 22:51:58 +0100 | [diff] [blame] | 14 | #if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) |
| 15 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 |
| 16 | #endif |
| 17 | |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 18 | /* |
| 19 | * Register Space. |
| 20 | */ |
| 21 | struct ehci_hccr { |
michael | 0a32610 | 2008-12-10 17:55:19 +0100 | [diff] [blame] | 22 | uint32_t cr_capbase; |
| 23 | #define HC_LENGTH(p) (((p) >> 0) & 0x00ff) |
| 24 | #define HC_VERSION(p) (((p) >> 16) & 0xffff) |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 25 | uint32_t cr_hcsparams; |
Remy Böhmer | 33e8748 | 2008-12-13 22:51:58 +0100 | [diff] [blame] | 26 | #define HCS_PPC(p) ((p) & (1 << 4)) |
| 27 | #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */ |
michael | 0bf2a03 | 2008-12-11 13:43:55 +0100 | [diff] [blame] | 28 | #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 29 | uint32_t cr_hccparams; |
| 30 | uint8_t cr_hcsp_portrt[8]; |
Jason Kridner | 8c2465c | 2011-04-20 08:54:16 -0500 | [diff] [blame] | 31 | } __attribute__ ((packed, aligned(4))); |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 32 | |
| 33 | struct ehci_hcor { |
| 34 | uint32_t or_usbcmd; |
michael | 0bf2a03 | 2008-12-11 13:43:55 +0100 | [diff] [blame] | 35 | #define CMD_PARK (1 << 11) /* enable "park" */ |
| 36 | #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */ |
michael | 0bf2a03 | 2008-12-11 13:43:55 +0100 | [diff] [blame] | 37 | #define CMD_LRESET (1 << 7) /* partial reset */ |
Masahiro Yamada | c6f9d82 | 2014-11-05 23:11:10 +0900 | [diff] [blame] | 38 | #define CMD_IAAD (1 << 6) /* "doorbell" interrupt */ |
| 39 | #define CMD_ASE (1 << 5) /* async schedule enable */ |
michael | 0bf2a03 | 2008-12-11 13:43:55 +0100 | [diff] [blame] | 40 | #define CMD_PSE (1 << 4) /* periodic schedule enable */ |
| 41 | #define CMD_RESET (1 << 1) /* reset HC not bus */ |
| 42 | #define CMD_RUN (1 << 0) /* start/stop HC */ |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 43 | uint32_t or_usbsts; |
Benoît Thébaudeau | 458fb1e | 2012-08-10 18:22:11 +0200 | [diff] [blame] | 44 | #define STS_ASS (1 << 15) |
Patrick Georgi | e55fdac | 2013-03-06 14:08:31 +0000 | [diff] [blame] | 45 | #define STS_PSS (1 << 14) |
michael | 0bf2a03 | 2008-12-11 13:43:55 +0100 | [diff] [blame] | 46 | #define STS_HALT (1 << 12) |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 47 | uint32_t or_usbintr; |
Damien Dusha | 7c3be66 | 2010-10-14 15:27:06 +0200 | [diff] [blame] | 48 | #define INTR_UE (1 << 0) /* USB interrupt enable */ |
| 49 | #define INTR_UEE (1 << 1) /* USB error interrupt enable */ |
| 50 | #define INTR_PCE (1 << 2) /* Port change detect enable */ |
| 51 | #define INTR_SEE (1 << 4) /* system error enable */ |
| 52 | #define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */ |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 53 | uint32_t or_frindex; |
| 54 | uint32_t or_ctrldssegment; |
| 55 | uint32_t or_periodiclistbase; |
| 56 | uint32_t or_asynclistaddr; |
Simon Glass | 5978cdb | 2012-02-27 10:52:47 +0000 | [diff] [blame] | 57 | uint32_t _reserved_0_; |
| 58 | uint32_t or_burstsize; |
| 59 | uint32_t or_txfilltuning; |
Benoît Thébaudeau | 458fb1e | 2012-08-10 18:22:11 +0200 | [diff] [blame] | 60 | #define TXFIFO_THRESH_MASK (0x3f << 16) |
Simon Glass | 5978cdb | 2012-02-27 10:52:47 +0000 | [diff] [blame] | 61 | #define TXFIFO_THRESH(p) ((p & 0x3f) << 16) |
| 62 | uint32_t _reserved_1_[6]; |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 63 | uint32_t or_configflag; |
michael | 0bf2a03 | 2008-12-11 13:43:55 +0100 | [diff] [blame] | 64 | #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ |
Remy Böhmer | 33e8748 | 2008-12-13 22:51:58 +0100 | [diff] [blame] | 65 | uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS]; |
Benoît Thébaudeau | 458fb1e | 2012-08-10 18:22:11 +0200 | [diff] [blame] | 66 | #define PORTSC_PSPD(x) (((x) >> 26) & 0x3) |
| 67 | #define PORTSC_PSPD_FS 0x0 |
| 68 | #define PORTSC_PSPD_LS 0x1 |
| 69 | #define PORTSC_PSPD_HS 0x2 |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 70 | uint32_t or_systune; |
Jason Kridner | 8c2465c | 2011-04-20 08:54:16 -0500 | [diff] [blame] | 71 | } __attribute__ ((packed, aligned(4))); |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 72 | |
michael | 0bf2a03 | 2008-12-11 13:43:55 +0100 | [diff] [blame] | 73 | #define USBMODE 0x68 /* USB Device mode */ |
| 74 | #define USBMODE_SDIS (1 << 3) /* Stream disable */ |
| 75 | #define USBMODE_BE (1 << 2) /* BE/LE endiannes select */ |
| 76 | #define USBMODE_CM_HC (3 << 0) /* host controller mode */ |
| 77 | #define USBMODE_CM_IDLE (0 << 0) /* idle state */ |
| 78 | |
michael | 0a32610 | 2008-12-10 17:55:19 +0100 | [diff] [blame] | 79 | /* Interface descriptor */ |
| 80 | struct usb_linux_interface_descriptor { |
| 81 | unsigned char bLength; |
| 82 | unsigned char bDescriptorType; |
| 83 | unsigned char bInterfaceNumber; |
| 84 | unsigned char bAlternateSetting; |
| 85 | unsigned char bNumEndpoints; |
| 86 | unsigned char bInterfaceClass; |
| 87 | unsigned char bInterfaceSubClass; |
| 88 | unsigned char bInterfaceProtocol; |
| 89 | unsigned char iInterface; |
| 90 | } __attribute__ ((packed)); |
| 91 | |
| 92 | /* Configuration descriptor information.. */ |
| 93 | struct usb_linux_config_descriptor { |
| 94 | unsigned char bLength; |
| 95 | unsigned char bDescriptorType; |
| 96 | unsigned short wTotalLength; |
| 97 | unsigned char bNumInterfaces; |
| 98 | unsigned char bConfigurationValue; |
| 99 | unsigned char iConfiguration; |
| 100 | unsigned char bmAttributes; |
| 101 | unsigned char MaxPower; |
| 102 | } __attribute__ ((packed)); |
| 103 | |
| 104 | #if defined CONFIG_EHCI_DESC_BIG_ENDIAN |
Alexey Brodkin | bb1cd63 | 2017-06-05 22:31:51 +0300 | [diff] [blame] | 105 | #define ehci_readl(x) cpu_to_be32(readl(x)) |
| 106 | #define ehci_writel(a, b) writel(cpu_to_be32(b), a) |
michael | 0a32610 | 2008-12-10 17:55:19 +0100 | [diff] [blame] | 107 | #else |
Alexey Brodkin | bb1cd63 | 2017-06-05 22:31:51 +0300 | [diff] [blame] | 108 | #define ehci_readl(x) cpu_to_le32(readl(x)) |
| 109 | #define ehci_writel(a, b) writel(cpu_to_le32(b), a) |
michael | 0a32610 | 2008-12-10 17:55:19 +0100 | [diff] [blame] | 110 | #endif |
| 111 | |
| 112 | #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN |
| 113 | #define hc32_to_cpu(x) be32_to_cpu((x)) |
| 114 | #define cpu_to_hc32(x) cpu_to_be32((x)) |
| 115 | #else |
| 116 | #define hc32_to_cpu(x) le32_to_cpu((x)) |
| 117 | #define cpu_to_hc32(x) cpu_to_le32((x)) |
| 118 | #endif |
| 119 | |
Remy Böhmer | 33e8748 | 2008-12-13 22:51:58 +0100 | [diff] [blame] | 120 | #define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */ |
| 121 | #define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */ |
| 122 | #define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */ |
| 123 | #define EHCI_PS_PO (1 << 13) /* RW port owner */ |
| 124 | #define EHCI_PS_PP (1 << 12) /* RW,RO port power */ |
| 125 | #define EHCI_PS_LS (3 << 10) /* RO line status */ |
| 126 | #define EHCI_PS_PR (1 << 8) /* RW port reset */ |
| 127 | #define EHCI_PS_SUSP (1 << 7) /* RW suspend */ |
| 128 | #define EHCI_PS_FPR (1 << 6) /* RW force port resume */ |
| 129 | #define EHCI_PS_OCC (1 << 5) /* RWC over current change */ |
| 130 | #define EHCI_PS_OCA (1 << 4) /* RO over current active */ |
| 131 | #define EHCI_PS_PEC (1 << 3) /* RWC port enable change */ |
| 132 | #define EHCI_PS_PE (1 << 2) /* RW port enable */ |
| 133 | #define EHCI_PS_CSC (1 << 1) /* RWC connect status change */ |
| 134 | #define EHCI_PS_CS (1 << 0) /* RO connect status */ |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 135 | #define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC) |
| 136 | |
Remy Böhmer | 33e8748 | 2008-12-13 22:51:58 +0100 | [diff] [blame] | 137 | #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10)) |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 138 | |
| 139 | /* |
| 140 | * Schedule Interface Space. |
| 141 | * |
| 142 | * IMPORTANT: Software must ensure that no interface data structure |
| 143 | * reachable by the EHCI host controller spans a 4K page boundary! |
| 144 | * |
| 145 | * Periodic transfers (i.e. isochronous and interrupt transfers) are |
| 146 | * not supported. |
| 147 | */ |
| 148 | |
| 149 | /* Queue Element Transfer Descriptor (qTD). */ |
| 150 | struct qTD { |
Wolfgang Denk | ebb829f | 2010-10-19 16:13:15 +0200 | [diff] [blame] | 151 | /* this part defined by EHCI spec */ |
Benoît Thébaudeau | e68f48a | 2012-07-19 22:16:38 +0200 | [diff] [blame] | 152 | uint32_t qt_next; /* see EHCI 3.5.1 */ |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 153 | #define QT_NEXT_TERMINATE 1 |
Benoît Thébaudeau | e68f48a | 2012-07-19 22:16:38 +0200 | [diff] [blame] | 154 | uint32_t qt_altnext; /* see EHCI 3.5.2 */ |
| 155 | uint32_t qt_token; /* see EHCI 3.5.3 */ |
Benoît Thébaudeau | 458fb1e | 2012-08-10 18:22:11 +0200 | [diff] [blame] | 156 | #define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */ |
| 157 | #define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1) |
| 158 | #define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */ |
| 159 | #define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff) |
| 160 | #define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */ |
| 161 | #define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */ |
| 162 | #define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */ |
| 163 | #define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */ |
| 164 | #define QT_TOKEN_PID_OUT 0x0 |
| 165 | #define QT_TOKEN_PID_IN 0x1 |
| 166 | #define QT_TOKEN_PID_SETUP 0x2 |
| 167 | #define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */ |
| 168 | #define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff) |
| 169 | #define QT_TOKEN_STATUS_ACTIVE 0x80 |
| 170 | #define QT_TOKEN_STATUS_HALTED 0x40 |
| 171 | #define QT_TOKEN_STATUS_DATBUFERR 0x20 |
| 172 | #define QT_TOKEN_STATUS_BABBLEDET 0x10 |
| 173 | #define QT_TOKEN_STATUS_XACTERR 0x08 |
| 174 | #define QT_TOKEN_STATUS_MISSEDUFRAME 0x04 |
| 175 | #define QT_TOKEN_STATUS_SPLITXSTATE 0x02 |
| 176 | #define QT_TOKEN_STATUS_PERR 0x01 |
Benoît Thébaudeau | e68f48a | 2012-07-19 22:16:38 +0200 | [diff] [blame] | 177 | #define QT_BUFFER_CNT 5 |
| 178 | uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */ |
| 179 | uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */ |
Wolfgang Denk | ebb829f | 2010-10-19 16:13:15 +0200 | [diff] [blame] | 180 | /* pad struct for 32 byte alignment */ |
| 181 | uint32_t unused[3]; |
Wolfgang Denk | cd6cbd9 | 2010-10-20 21:08:17 +0200 | [diff] [blame] | 182 | }; |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 183 | |
Benoît Thébaudeau | 458fb1e | 2012-08-10 18:22:11 +0200 | [diff] [blame] | 184 | #define EHCI_PAGE_SIZE 4096 |
| 185 | |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 186 | /* Queue Head (QH). */ |
| 187 | struct QH { |
| 188 | uint32_t qh_link; |
| 189 | #define QH_LINK_TERMINATE 1 |
| 190 | #define QH_LINK_TYPE_ITD 0 |
| 191 | #define QH_LINK_TYPE_QH 2 |
| 192 | #define QH_LINK_TYPE_SITD 4 |
| 193 | #define QH_LINK_TYPE_FSTN 6 |
| 194 | uint32_t qh_endpt1; |
Benoît Thébaudeau | 458fb1e | 2012-08-10 18:22:11 +0200 | [diff] [blame] | 195 | #define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */ |
| 196 | #define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */ |
| 197 | #define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */ |
| 198 | #define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */ |
| 199 | #define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */ |
| 200 | #define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0 |
| 201 | #define QH_ENDPT1_DTC_DT_FROM_QTD 0x1 |
| 202 | #define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */ |
| 203 | #define QH_ENDPT1_EPS_FS 0x0 |
| 204 | #define QH_ENDPT1_EPS_LS 0x1 |
| 205 | #define QH_ENDPT1_EPS_HS 0x2 |
| 206 | #define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */ |
| 207 | #define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */ |
| 208 | #define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */ |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 209 | uint32_t qh_endpt2; |
Benoît Thébaudeau | 458fb1e | 2012-08-10 18:22:11 +0200 | [diff] [blame] | 210 | #define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */ |
| 211 | #define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */ |
| 212 | #define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */ |
| 213 | #define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */ |
| 214 | #define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */ |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 215 | uint32_t qh_curtd; |
| 216 | struct qTD qh_overlay; |
Stefan Roese | 25983c1 | 2009-01-21 17:12:19 +0100 | [diff] [blame] | 217 | /* |
| 218 | * Add dummy fill value to make the size of this struct |
| 219 | * aligned to 32 bytes |
| 220 | */ |
Patrick Georgi | e55fdac | 2013-03-06 14:08:31 +0000 | [diff] [blame] | 221 | union { |
Vincent Palatin | 28e1d9c | 2013-03-06 14:08:32 +0000 | [diff] [blame] | 222 | uint32_t fill[4]; |
Patrick Georgi | e55fdac | 2013-03-06 14:08:31 +0000 | [diff] [blame] | 223 | void *buffer; |
| 224 | }; |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 225 | }; |
| 226 | |
Simon Glass | ccc40fd | 2015-03-25 12:22:26 -0600 | [diff] [blame] | 227 | /* Tweak flags for EHCI, used to control operation */ |
| 228 | enum { |
| 229 | /* don't use or_configflag in init */ |
| 230 | EHCI_TWEAK_NO_INIT_CF = 1 << 0, |
| 231 | }; |
| 232 | |
Simon Glass | dc9f3ed | 2015-03-25 12:22:27 -0600 | [diff] [blame] | 233 | struct ehci_ctrl; |
| 234 | |
| 235 | struct ehci_ops { |
| 236 | void (*set_usb_mode)(struct ehci_ctrl *ctrl); |
| 237 | int (*get_port_speed)(struct ehci_ctrl *ctrl, uint32_t reg); |
| 238 | void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg, |
| 239 | uint32_t *reg); |
| 240 | uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port); |
Mateusz Kulikowski | aab5a5a | 2016-03-31 23:12:17 +0200 | [diff] [blame] | 241 | int (*init_after_reset)(struct ehci_ctrl *ctrl); |
Simon Glass | dc9f3ed | 2015-03-25 12:22:27 -0600 | [diff] [blame] | 242 | }; |
| 243 | |
Marek Vasut | fd349a1 | 2013-07-10 03:16:31 +0200 | [diff] [blame] | 244 | struct ehci_ctrl { |
Stephen Warren | 71eced3 | 2015-08-20 17:38:05 -0600 | [diff] [blame] | 245 | enum usb_init_type init; |
Marek Vasut | fd349a1 | 2013-07-10 03:16:31 +0200 | [diff] [blame] | 246 | struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ |
| 247 | struct ehci_hcor *hcor; |
| 248 | int rootdev; |
| 249 | uint16_t portreset; |
| 250 | struct QH qh_list __aligned(USB_DMA_MINALIGN); |
| 251 | struct QH periodic_queue __aligned(USB_DMA_MINALIGN); |
| 252 | uint32_t *periodic_list; |
Hans de Goede | 8f5f4f7 | 2014-09-20 16:51:25 +0200 | [diff] [blame] | 253 | int periodic_schedules; |
Marek Vasut | fd349a1 | 2013-07-10 03:16:31 +0200 | [diff] [blame] | 254 | int ntds; |
Simon Glass | dc9f3ed | 2015-03-25 12:22:27 -0600 | [diff] [blame] | 255 | struct ehci_ops ops; |
Simon Glass | 0851caa | 2015-03-25 12:22:19 -0600 | [diff] [blame] | 256 | void *priv; /* client's private data */ |
Marek Vasut | fd349a1 | 2013-07-10 03:16:31 +0200 | [diff] [blame] | 257 | }; |
| 258 | |
Simon Glass | 0851caa | 2015-03-25 12:22:19 -0600 | [diff] [blame] | 259 | /** |
Simon Glass | dc9f3ed | 2015-03-25 12:22:27 -0600 | [diff] [blame] | 260 | * ehci_set_controller_info() - Set up private data for the controller |
Simon Glass | 0851caa | 2015-03-25 12:22:19 -0600 | [diff] [blame] | 261 | * |
| 262 | * This function can be called in ehci_hcd_init() to tell the EHCI layer |
| 263 | * about the controller's private data pointer. Then in the above functions |
Simon Glass | dc9f3ed | 2015-03-25 12:22:27 -0600 | [diff] [blame] | 264 | * this can be accessed given the struct ehci_ctrl pointer. Also special |
| 265 | * EHCI operation methods can be provided if required |
Simon Glass | 0851caa | 2015-03-25 12:22:19 -0600 | [diff] [blame] | 266 | * |
| 267 | * @index: Controller number to set |
| 268 | * @priv: Controller pointer |
Simon Glass | dc9f3ed | 2015-03-25 12:22:27 -0600 | [diff] [blame] | 269 | * @ops: Controller operations, or NULL to use default |
Simon Glass | 0851caa | 2015-03-25 12:22:19 -0600 | [diff] [blame] | 270 | */ |
Simon Glass | dc9f3ed | 2015-03-25 12:22:27 -0600 | [diff] [blame] | 271 | void ehci_set_controller_priv(int index, void *priv, |
| 272 | const struct ehci_ops *ops); |
Simon Glass | 0851caa | 2015-03-25 12:22:19 -0600 | [diff] [blame] | 273 | |
| 274 | /** |
| 275 | * ehci_get_controller_priv() - Get controller private data |
| 276 | * |
| 277 | * @index Controller number to get |
| 278 | * @return controller pointer for this index |
| 279 | */ |
| 280 | void *ehci_get_controller_priv(int index); |
| 281 | |
Remy Böhmer | 33e8748 | 2008-12-13 22:51:58 +0100 | [diff] [blame] | 282 | /* Low level init functions */ |
Troy Kisky | 7d6bbb9 | 2013-10-10 15:27:57 -0700 | [diff] [blame] | 283 | int ehci_hcd_init(int index, enum usb_init_type init, |
| 284 | struct ehci_hccr **hccr, struct ehci_hcor **hcor); |
Lucas Stach | 3494a4c | 2012-09-26 00:14:35 +0200 | [diff] [blame] | 285 | int ehci_hcd_stop(int index); |
Remy Böhmer | 33e8748 | 2008-12-13 22:51:58 +0100 | [diff] [blame] | 286 | |
Simon Glass | a194b25 | 2015-03-25 12:22:29 -0600 | [diff] [blame] | 287 | int ehci_register(struct udevice *dev, struct ehci_hccr *hccr, |
| 288 | struct ehci_hcor *hcor, const struct ehci_ops *ops, |
| 289 | uint tweaks, enum usb_init_type init); |
| 290 | int ehci_deregister(struct udevice *dev); |
| 291 | extern struct dm_usb_ops ehci_usb_ops; |
| 292 | |
Michael Trimarchi | 241f751 | 2008-11-28 13:20:46 +0100 | [diff] [blame] | 293 | #endif /* USB_EHCI_H */ |