blob: b5178db394f01421e9f841c4fdb585f0caff6541 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glassc5915f72016-01-21 19:44:55 -07002/*
3 * (C) Copyright 2016 Google, Inc
4 * (C) Copyright 2008-2014 Rockchip Electronics
Simon Glassc5915f72016-01-21 19:44:55 -07005 */
6
7#ifndef _ASM_ARCH_PWM_H
8#define _ASM_ARCH_PWM_H
9
10struct rk3288_pwm {
11 u32 cnt;
Kever Yang7ac41cf2016-09-23 15:57:18 +080012 u32 period_hpr;
eric.gao@rock-chips.combdd37312017-06-19 14:45:36 +080013 u32 duty_lpr;
Simon Glassc5915f72016-01-21 19:44:55 -070014 u32 ctrl;
15};
16check_member(rk3288_pwm, ctrl, 0xc);
17
18#define RK_PWM_DISABLE (0 << 0)
19#define RK_PWM_ENABLE (1 << 0)
20
21#define PWM_ONE_SHOT (0 << 1)
22#define PWM_CONTINUOUS (1 << 1)
23#define RK_PWM_CAPTURE (1 << 2)
24
25#define PWM_DUTY_POSTIVE (1 << 3)
26#define PWM_DUTY_NEGATIVE (0 << 3)
Kever Yang2291e492017-07-19 19:54:23 +080027#define PWM_DUTY_MASK (1 << 3)
Simon Glassc5915f72016-01-21 19:44:55 -070028
29#define PWM_INACTIVE_POSTIVE (1 << 4)
30#define PWM_INACTIVE_NEGATIVE (0 << 4)
Kever Yang2291e492017-07-19 19:54:23 +080031#define PWM_INACTIVE_MASK (1 << 4)
Simon Glassc5915f72016-01-21 19:44:55 -070032
33#define PWM_OUTPUT_LEFT (0 << 5)
34#define PWM_OUTPUT_CENTER (1 << 5)
35
36#define PWM_LP_ENABLE (1 << 8)
37#define PWM_LP_DISABLE (0 << 8)
38
39#define PWM_SEL_SCALE_CLK (1 << 9)
40#define PWM_SEL_SRC_CLK (0 << 9)
41
42#endif