blob: b1d8047691e77804a7f67e5bf2c0b653c19f2d58 [file] [log] [blame]
Simon Glassc5915f72016-01-21 19:44:55 -07001/*
2 * (C) Copyright 2016 Google, Inc
3 * (C) Copyright 2008-2014 Rockchip Electronics
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef _ASM_ARCH_PWM_H
9#define _ASM_ARCH_PWM_H
10
11struct rk3288_pwm {
12 u32 cnt;
Kever Yang7ac41cf2016-09-23 15:57:18 +080013 u32 period_hpr;
eric.gao@rock-chips.combdd37312017-06-19 14:45:36 +080014 u32 duty_lpr;
Simon Glassc5915f72016-01-21 19:44:55 -070015 u32 ctrl;
16};
17check_member(rk3288_pwm, ctrl, 0xc);
18
19#define RK_PWM_DISABLE (0 << 0)
20#define RK_PWM_ENABLE (1 << 0)
21
22#define PWM_ONE_SHOT (0 << 1)
23#define PWM_CONTINUOUS (1 << 1)
24#define RK_PWM_CAPTURE (1 << 2)
25
26#define PWM_DUTY_POSTIVE (1 << 3)
27#define PWM_DUTY_NEGATIVE (0 << 3)
Kever Yang2291e492017-07-19 19:54:23 +080028#define PWM_DUTY_MASK (1 << 3)
Simon Glassc5915f72016-01-21 19:44:55 -070029
30#define PWM_INACTIVE_POSTIVE (1 << 4)
31#define PWM_INACTIVE_NEGATIVE (0 << 4)
Kever Yang2291e492017-07-19 19:54:23 +080032#define PWM_INACTIVE_MASK (1 << 4)
Simon Glassc5915f72016-01-21 19:44:55 -070033
34#define PWM_OUTPUT_LEFT (0 << 5)
35#define PWM_OUTPUT_CENTER (1 << 5)
36
37#define PWM_LP_ENABLE (1 << 8)
38#define PWM_LP_DISABLE (0 << 8)
39
40#define PWM_SEL_SCALE_CLK (1 << 9)
41#define PWM_SEL_SRC_CLK (0 << 9)
42
43#endif