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git01.mediatek.com / filogic / uboot / 69a5321c429773b672a053fd2087358eddec8882 / . / board / freescale / t104xrdb / eth.c
blob: b034f11d68aaae85177903c8e41430b4c86d0a63 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]2/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]4 */
5
6#include <common.h>
Simon Glass274e0b02020-05-10 11:39:56 -0600[diff] [blame]7#include <net.h>
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]8#include <netdev.h>
Codrin Ciubotariub29e5e22015-01-21 11:54:12 +0200[diff] [blame]9#include <asm/fsl_serdes.h>
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]10#include <asm/immap_85xx.h>
11#include <fm_eth.h>
12#include <fsl_mdio.h>
13#include <malloc.h>
Shaohui Xie513eaf22015-10-26 19:47:47 +0800[diff] [blame]14#include <fsl_dtsec.h>
Codrin Ciubotariub29e5e22015-01-21 11:54:12 +0200[diff] [blame]15#include <vsc9953.h>
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]16
17#include "../common/fman.h"
18
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900[diff] [blame]19int board_eth_init(struct bd_info *bis)
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]20{
21#ifdef CONFIG_FMAN_ENET
22 struct memac_mdio_info memac_mdio_info;
23 unsigned int i;
24 int phy_addr = 0;
Codrin Ciubotariub29e5e22015-01-21 11:54:12 +0200[diff] [blame]25#ifdef CONFIG_VSC9953
26 phy_interface_t phy_int;
27 struct mii_dev *bus;
28#endif
29
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]30 printf("Initializing Fman\n");
31
32 memac_mdio_info.regs =
33 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
34 memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
35
36 /* Register the real 1G MDIO bus */
37 fm_memac_mdio_init(bis, &memac_mdio_info);
38
39 /*
40 * Program on board RGMII, SGMII PHY addresses.
41 */
42 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
43 int idx = i - FM1_DTSEC1;
44
45 switch (fm_info_get_enet_if(i)) {
York Sun37cdf5d2016-11-18 13:31:27 -0800[diff] [blame]46#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]47 case PHY_INTERFACE_MODE_SGMII:
Priyanka Jaine7597fe2015-06-05 15:29:02 +0530[diff] [blame]48 /* T1040RDB & T1040D4RDB only supports SGMII on
49 * DTSEC3
50 */
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]51 fm_info_set_phy_address(FM1_DTSEC3,
52 CONFIG_SYS_SGMII1_PHY_ADDR);
Shaohui Xief7cbfe52014-04-11 12:12:30 +0800[diff] [blame]53 break;
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]54#endif
York Sun5e471552016-11-21 11:08:49 -0800[diff] [blame]55#ifdef CONFIG_TARGET_T1042RDB
vijay rai6eb8e0c2014-08-19 12:46:53 +0530[diff] [blame]56 case PHY_INTERFACE_MODE_SGMII:
57 /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
58 if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
59 fm_info_set_phy_address(i, 0);
60 /* T1042RDB only supports SGMII on DTSEC3 */
61 fm_info_set_phy_address(FM1_DTSEC3,
62 CONFIG_SYS_SGMII1_PHY_ADDR);
63 break;
64#endif
York Sund08610d2016-11-21 11:04:34 -0800[diff] [blame]65#ifdef CONFIG_TARGET_T1042D4RDB
Priyanka Jaine7597fe2015-06-05 15:29:02 +0530[diff] [blame]66 case PHY_INTERFACE_MODE_SGMII:
67 /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
68 * & DTSEC3
69 */
70 if (FM1_DTSEC1 == i)
71 phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
72 if (FM1_DTSEC2 == i)
73 phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
74 if (FM1_DTSEC3 == i)
75 phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
76 fm_info_set_phy_address(i, phy_addr);
77 break;
78#endif
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]79 case PHY_INTERFACE_MODE_RGMII:
Madalin Bucur03b80152020-11-04 15:09:17 +0200[diff] [blame]80 case PHY_INTERFACE_MODE_RGMII_TXID:
81 case PHY_INTERFACE_MODE_RGMII_RXID:
82 case PHY_INTERFACE_MODE_RGMII_ID:
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]83 if (FM1_DTSEC4 == i)
84 phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
85 if (FM1_DTSEC5 == i)
86 phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
87 fm_info_set_phy_address(i, phy_addr);
88 break;
89 case PHY_INTERFACE_MODE_QSGMII:
90 fm_info_set_phy_address(i, 0);
91 break;
92 case PHY_INTERFACE_MODE_NONE:
93 fm_info_set_phy_address(i, 0);
94 break;
95 default:
96 printf("Fman1: DTSEC%u set to unknown interface %i\n",
97 idx + 1, fm_info_get_enet_if(i));
98 fm_info_set_phy_address(i, 0);
99 break;
100 }
Codrin Ciubotariu3df7b7a2015-01-12 14:08:37 +0200[diff] [blame]101 if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
102 fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
103 fm_info_set_mdio(i, NULL);
104 else
105 fm_info_set_mdio(i,
106 miiphy_get_dev_by_name(
107 DEFAULT_FM_MDIO_NAME));
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]108 }
109
Codrin Ciubotariub29e5e22015-01-21 11:54:12 +0200[diff] [blame]110#ifdef CONFIG_VSC9953
111 /* SerDes configured for QSGMII */
112 if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
113 for (i = 0; i < 4; i++) {
114 bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
115 phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
116 phy_int = PHY_INTERFACE_MODE_QSGMII;
117
118 vsc9953_port_info_set_mdio(i, bus);
119 vsc9953_port_info_set_phy_address(i, phy_addr);
120 vsc9953_port_info_set_phy_int(i, phy_int);
121 vsc9953_port_enable(i);
122 }
123 }
124 if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
125 for (i = 4; i < 8; i++) {
126 bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
127 phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
128 phy_int = PHY_INTERFACE_MODE_QSGMII;
129
130 vsc9953_port_info_set_mdio(i, bus);
131 vsc9953_port_info_set_phy_address(i, phy_addr);
132 vsc9953_port_info_set_phy_int(i, phy_int);
133 vsc9953_port_enable(i);
134 }
135 }
136
137 /* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
138 if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
139 vsc9953_port_enable(8);
140
141 /* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
142 if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
143 /* Enable L2 On MAC2 using SCFG */
144 struct ccsr_scfg *scfg = (struct ccsr_scfg *)
145 CONFIG_SYS_MPC85xx_SCFG;
146
147 out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
148 (0x80000000));
149 vsc9953_port_enable(9);
150 }
151#endif
152
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]153 cpu_eth_init(bis);
154#endif
155
156 return pci_eth_init(bis);
157}