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git01.mediatek.com / filogic / uboot / 6eb8e0cb6a3985168adcfd1666f4dc0a179dc866 / . / board / freescale / t104xrdb / eth.c
blob: c8b6c672a683a2e5b19213e792a575e621003457 [file] [log] [blame]
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <netdev.h>
9#include <asm/immap_85xx.h>
10#include <fm_eth.h>
11#include <fsl_mdio.h>
12#include <malloc.h>
13#include <asm/fsl_dtsec.h>
14
15#include "../common/fman.h"
16
17int board_eth_init(bd_t *bis)
18{
19#ifdef CONFIG_FMAN_ENET
20 struct memac_mdio_info memac_mdio_info;
21 unsigned int i;
22 int phy_addr = 0;
23 printf("Initializing Fman\n");
24
25 memac_mdio_info.regs =
26 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
27 memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
28
29 /* Register the real 1G MDIO bus */
30 fm_memac_mdio_init(bis, &memac_mdio_info);
31
32 /*
33 * Program on board RGMII, SGMII PHY addresses.
34 */
35 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
36 int idx = i - FM1_DTSEC1;
37
38 switch (fm_info_get_enet_if(i)) {
39#ifdef CONFIG_T1040RDB
40 case PHY_INTERFACE_MODE_SGMII:
41 /* T1040RDB only supports SGMII on DTSEC3 */
42 fm_info_set_phy_address(FM1_DTSEC3,
43 CONFIG_SYS_SGMII1_PHY_ADDR);
Shaohui Xief7cbfe52014-04-11 12:12:30 +0800[diff] [blame]44 break;
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]45#endif
vijay rai6eb8e0c2014-08-19 12:46:53 +0530[diff] [blame^]46#ifdef CONFIG_T1042RDB
47 case PHY_INTERFACE_MODE_SGMII:
48 /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
49 if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
50 fm_info_set_phy_address(i, 0);
51 /* T1042RDB only supports SGMII on DTSEC3 */
52 fm_info_set_phy_address(FM1_DTSEC3,
53 CONFIG_SYS_SGMII1_PHY_ADDR);
54 break;
55#endif
Priyanka Jain29b426b2014-01-30 11:30:04 +0530[diff] [blame]56 case PHY_INTERFACE_MODE_RGMII:
57 if (FM1_DTSEC4 == i)
58 phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
59 if (FM1_DTSEC5 == i)
60 phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
61 fm_info_set_phy_address(i, phy_addr);
62 break;
63 case PHY_INTERFACE_MODE_QSGMII:
64 fm_info_set_phy_address(i, 0);
65 break;
66 case PHY_INTERFACE_MODE_NONE:
67 fm_info_set_phy_address(i, 0);
68 break;
69 default:
70 printf("Fman1: DTSEC%u set to unknown interface %i\n",
71 idx + 1, fm_info_get_enet_if(i));
72 fm_info_set_phy_address(i, 0);
73 break;
74 }
75 fm_info_set_mdio(i,
76 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
77 }
78
79 cpu_eth_init(bis);
80#endif
81
82 return pci_eth_init(bis);
83}