blob: 2b5239ccb4752dbbe1af490d8c139d8652f41438 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek04b7e622015-01-15 10:01:51 +01002/*
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
Michal Simek04b7e622015-01-15 10:01:51 +01005 */
6
7#include <common.h>
Simon Glassed38aef2020-05-10 11:40:03 -06008#include <command.h>
Simon Glass370382c2019-11-14 12:57:35 -07009#include <cpu_func.h>
Michal Simek09a7d7d2020-01-07 09:02:52 +010010#include <debug_uart.h>
Michal Simekcfb37602021-07-27 16:19:18 +020011#include <dfu.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060012#include <env.h>
Michal Simek8d4a8d42020-07-30 13:37:49 +020013#include <env_internal.h>
Simon Glassa7b51302019-11-14 12:57:46 -070014#include <init.h>
Michal Simek97ab9612021-05-31 11:03:19 +020015#include <image.h>
16#include <lmb.h>
Simon Glass0f2af882020-05-10 11:40:05 -060017#include <log.h>
Simon Glass274e0b02020-05-10 11:39:56 -060018#include <net.h>
Michal Simekd54b1af2015-09-30 17:26:55 +020019#include <sata.h>
Michal Simekb216cc12015-07-23 13:27:40 +020020#include <ahci.h>
21#include <scsi.h>
Michal Simekecfb6dc2016-04-22 14:28:54 +020022#include <malloc.h>
Michal Simekcfb37602021-07-27 16:19:18 +020023#include <memalign.h>
Michal Simekbf0f9ca2018-04-19 15:43:38 +020024#include <wdt.h>
Michal Simekc23d3f82015-11-05 08:34:35 +010025#include <asm/arch/clk.h>
Michal Simek04b7e622015-01-15 10:01:51 +010026#include <asm/arch/hardware.h>
27#include <asm/arch/sys_proto.h>
Michal Simekf2f08642018-01-10 09:36:09 +010028#include <asm/arch/psu_init_gpl.h>
Simon Glass274e0b02020-05-10 11:39:56 -060029#include <asm/cache.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060030#include <asm/global_data.h>
Michal Simek04b7e622015-01-15 10:01:51 +010031#include <asm/io.h>
Simon Glass6b9f0102020-05-10 11:40:06 -060032#include <asm/ptrace.h>
Michal Simekf183a982018-04-25 11:20:43 +020033#include <dm/device.h>
Michal Simekbf0f9ca2018-04-19 15:43:38 +020034#include <dm/uclass.h>
Siva Durga Prasad Paladuguba1f68e2015-08-04 13:03:26 +053035#include <usb.h>
36#include <dwc3-uboot.h>
Michal Simek8111aff2016-02-01 15:05:58 +010037#include <zynqmppl.h>
Ibai Erkiagac8a3efa2019-09-27 11:37:01 +010038#include <zynqmp_firmware.h>
Michal Simek76d0a772016-09-01 11:16:40 +020039#include <g_dnl.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060040#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060041#include <linux/delay.h>
42#include <linux/sizes.h>
Michal Simek705d44a2020-03-31 12:39:37 +020043#include "../common/board.h"
Michal Simek04b7e622015-01-15 10:01:51 +010044
Luca Ceresoli23e65002019-05-21 18:06:43 +020045#include "pm_cfg_obj.h"
46
Ibai Erkiaga4f736182020-08-04 23:17:31 +010047#define ZYNQMP_VERSION_SIZE 7
Michal Simekc702a742020-10-21 12:23:17 +020048#define EFUSE_VCU_DIS_MASK 0x100
49#define EFUSE_VCU_DIS_SHIFT 8
50#define EFUSE_GPU_DIS_MASK 0x20
51#define EFUSE_GPU_DIS_SHIFT 5
52#define IDCODE2_PL_INIT_MASK 0x200
53#define IDCODE2_PL_INIT_SHIFT 9
Ibai Erkiaga4f736182020-08-04 23:17:31 +010054
Michal Simek04b7e622015-01-15 10:01:51 +010055DECLARE_GLOBAL_DATA_PTR;
56
Michal Simek1aab1142020-09-09 14:41:56 +020057#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
Michal Simek8111aff2016-02-01 15:05:58 +010058static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
59
Ibai Erkiaga4f736182020-08-04 23:17:31 +010060enum {
61 ZYNQMP_VARIANT_EG = BIT(0U),
62 ZYNQMP_VARIANT_EV = BIT(1U),
63 ZYNQMP_VARIANT_CG = BIT(2U),
64 ZYNQMP_VARIANT_DR = BIT(3U),
65};
66
Michal Simek8111aff2016-02-01 15:05:58 +010067static const struct {
Michal Simek6908b862017-11-06 12:55:59 +010068 u32 id;
Ibai Erkiaga4f736182020-08-04 23:17:31 +010069 u8 device;
70 u8 variants;
Michal Simek8111aff2016-02-01 15:05:58 +010071} zynqmp_devices[] = {
72 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +010073 .id = 0x04711093,
74 .device = 2,
75 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
Michal Simek50d8cef2017-08-22 14:58:53 +020076 },
77 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +010078 .id = 0x04710093,
79 .device = 3,
80 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
Michal Simek8111aff2016-02-01 15:05:58 +010081 },
82 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +010083 .id = 0x04721093,
84 .device = 4,
85 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
86 ZYNQMP_VARIANT_EV,
Michal Simek50d8cef2017-08-22 14:58:53 +020087 },
88 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +010089 .id = 0x04720093,
90 .device = 5,
91 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
92 ZYNQMP_VARIANT_EV,
Michal Simek50d8cef2017-08-22 14:58:53 +020093 },
94 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +010095 .id = 0x04739093,
96 .device = 6,
97 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
Michal Simek8111aff2016-02-01 15:05:58 +010098 },
99 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100100 .id = 0x04730093,
101 .device = 7,
102 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
103 ZYNQMP_VARIANT_EV,
Michal Simek50d8cef2017-08-22 14:58:53 +0200104 },
105 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100106 .id = 0x04738093,
107 .device = 9,
Michal Simek3626f2c2020-10-02 14:42:05 +0200108 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
Michal Simek50d8cef2017-08-22 14:58:53 +0200109 },
110 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100111 .id = 0x04740093,
112 .device = 11,
113 .variants = ZYNQMP_VARIANT_EG,
Michal Simek8111aff2016-02-01 15:05:58 +0100114 },
115 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100116 .id = 0x04750093,
117 .device = 15,
118 .variants = ZYNQMP_VARIANT_EG,
Michal Simek50d8cef2017-08-22 14:58:53 +0200119 },
120 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100121 .id = 0x04759093,
122 .device = 17,
123 .variants = ZYNQMP_VARIANT_EG,
Michal Simek50d8cef2017-08-22 14:58:53 +0200124 },
125 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100126 .id = 0x04758093,
127 .device = 19,
128 .variants = ZYNQMP_VARIANT_EG,
Michal Simek8111aff2016-02-01 15:05:58 +0100129 },
130 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100131 .id = 0x047E1093,
132 .device = 21,
133 .variants = ZYNQMP_VARIANT_DR,
Michal Simek50d8cef2017-08-22 14:58:53 +0200134 },
135 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100136 .id = 0x047E3093,
137 .device = 23,
138 .variants = ZYNQMP_VARIANT_DR,
Michal Simek8111aff2016-02-01 15:05:58 +0100139 },
140 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100141 .id = 0x047E5093,
142 .device = 25,
143 .variants = ZYNQMP_VARIANT_DR,
Michal Simek50d8cef2017-08-22 14:58:53 +0200144 },
145 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100146 .id = 0x047E4093,
147 .device = 27,
148 .variants = ZYNQMP_VARIANT_DR,
Michal Simek8111aff2016-02-01 15:05:58 +0100149 },
150 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100151 .id = 0x047E0093,
152 .device = 28,
153 .variants = ZYNQMP_VARIANT_DR,
Michal Simek8111aff2016-02-01 15:05:58 +0100154 },
155 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100156 .id = 0x047E2093,
157 .device = 29,
158 .variants = ZYNQMP_VARIANT_DR,
Michal Simek8111aff2016-02-01 15:05:58 +0100159 },
Michal Simekb510e532017-06-02 08:08:59 +0200160 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100161 .id = 0x047E6093,
162 .device = 39,
163 .variants = ZYNQMP_VARIANT_DR,
Michal Simekb510e532017-06-02 08:08:59 +0200164 },
165 {
Michal Simek3fd2ed32020-09-11 09:22:15 +0200166 .id = 0x047FD093,
167 .device = 43,
168 .variants = ZYNQMP_VARIANT_DR,
Michal Simekb510e532017-06-02 08:08:59 +0200169 },
170 {
Michal Simek3fd2ed32020-09-11 09:22:15 +0200171 .id = 0x047F8093,
172 .device = 46,
173 .variants = ZYNQMP_VARIANT_DR,
Michal Simekb510e532017-06-02 08:08:59 +0200174 },
175 {
Michal Simek3fd2ed32020-09-11 09:22:15 +0200176 .id = 0x047FF093,
177 .device = 47,
178 .variants = ZYNQMP_VARIANT_DR,
Michal Simekb510e532017-06-02 08:08:59 +0200179 },
180 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100181 .id = 0x047FB093,
182 .device = 48,
183 .variants = ZYNQMP_VARIANT_DR,
Michal Simekb510e532017-06-02 08:08:59 +0200184 },
185 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100186 .id = 0x047FE093,
187 .device = 49,
188 .variants = ZYNQMP_VARIANT_DR,
Siva Durga Prasad Paladugu85f61a82019-07-23 11:56:17 +0530189 },
T Karthik Reddy83df2cb2021-05-13 07:13:25 -0600190 {
191 .id = 0x046d0093,
192 .device = 67,
193 .variants = ZYNQMP_VARIANT_DR,
194 },
Michal Simek8111aff2016-02-01 15:05:58 +0100195};
Siva Durga Prasad Paladuguba2622d2018-03-02 16:20:10 +0530196
Michal Simek005cac02020-10-05 09:35:40 +0200197static const struct {
198 u32 id;
199 char *name;
200} zynqmp_svd_devices[] = {
201 {
202 .id = 0x04714093,
203 .name = "xck24"
204 },
205 {
206 .id = 0x04724093,
207 .name = "xck26",
208 },
209};
210
211static char *zynqmp_detect_svd_name(u32 idcode)
212{
213 u32 i;
214
215 for (i = 0; i < ARRAY_SIZE(zynqmp_svd_devices); i++) {
216 if (zynqmp_svd_devices[i].id == (idcode & 0x0FFFFFFF))
217 return zynqmp_svd_devices[i].name;
218 }
219
220 return "unknown";
221}
222
Michal Simek8111aff2016-02-01 15:05:58 +0100223static char *zynqmp_get_silicon_idcode_name(void)
224{
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100225 u32 i;
226 u32 idcode, idcode2;
Michal Simek051b8bc2020-08-05 12:41:35 +0200227 char name[ZYNQMP_VERSION_SIZE];
Ibai Erkiagac318ecb2020-08-04 23:17:30 +0100228 u32 ret_payload[PAYLOAD_ARG_CNT];
Michal Simekb5c3b0d2020-10-07 15:13:17 +0200229 int ret;
Ibai Erkiagac318ecb2020-08-04 23:17:30 +0100230
Michal Simek23c0def2020-10-21 12:16:02 +0200231 ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
232 if (ret) {
233 debug("%s: Getting chipid failed\n", __func__);
234 return "unknown";
235 }
Ibai Erkiagac318ecb2020-08-04 23:17:30 +0100236
237 /*
238 * Firmware returns:
239 * payload[0][31:0] = status of the operation
240 * payload[1]] = IDCODE
241 * payload[2][19:0] = Version
242 * payload[2][28:20] = EXTENDED_IDCODE
243 * payload[2][29] = PL_INIT
244 */
245
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100246 idcode = ret_payload[1];
247 idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
Michal Simekc76c96f2020-10-21 12:16:50 +0200248 debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100249 idcode2);
Michal Simek50d8cef2017-08-22 14:58:53 +0200250
Michal Simek8111aff2016-02-01 15:05:58 +0100251 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100252 if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
253 break;
Michal Simek8111aff2016-02-01 15:05:58 +0100254 }
Siva Durga Prasad Paladuguba2622d2018-03-02 16:20:10 +0530255
256 if (i >= ARRAY_SIZE(zynqmp_devices))
Michal Simek005cac02020-10-05 09:35:40 +0200257 return zynqmp_detect_svd_name(idcode);
Siva Durga Prasad Paladuguba2622d2018-03-02 16:20:10 +0530258
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100259 /* Add device prefix to the name */
Michal Simekb5c3b0d2020-10-07 15:13:17 +0200260 ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
261 zynqmp_devices[i].device);
Michal Simekd2281672020-10-21 12:17:44 +0200262 if (ret < 0)
Michal Simekb5c3b0d2020-10-07 15:13:17 +0200263 return "unknown";
Siva Durga Prasad Paladuguba2622d2018-03-02 16:20:10 +0530264
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100265 if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
266 /* Devices with EV variant might be EG/CG/EV family */
267 if (idcode2 & IDCODE2_PL_INIT_MASK) {
268 u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
269 EFUSE_VCU_DIS_SHIFT) << 1 |
270 ((idcode2 & EFUSE_GPU_DIS_MASK) >>
271 EFUSE_GPU_DIS_SHIFT);
Siva Durga Prasad Paladuguba2622d2018-03-02 16:20:10 +0530272
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100273 /*
274 * Get family name based on extended idcode values as
275 * determined on UG1087, EXTENDED_IDCODE register
276 * description
277 */
278 switch (family) {
279 case 0x00:
280 strncat(name, "ev", 2);
281 break;
282 case 0x10:
283 strncat(name, "eg", 2);
284 break;
285 case 0x11:
286 strncat(name, "cg", 2);
287 break;
288 default:
289 /* Do not append family name*/
290 break;
291 }
292 } else {
293 /*
294 * When PL powered down the VCU Disable efuse cannot be
295 * read. So, ignore the bit and just findout if it is CG
296 * or EG/EV variant.
297 */
298 strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
299 "e", 2);
300 }
301 } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
302 /* Devices with CG variant might be EG or CG family */
303 strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
304 } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
305 strncat(name, "eg", 2);
306 } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
307 strncat(name, "dr", 2);
308 } else {
309 debug("Variant not identified\n");
Siva Durga Prasad Paladuguba2622d2018-03-02 16:20:10 +0530310 }
311
Michal Simek051b8bc2020-08-05 12:41:35 +0200312 return strdup(name);
Michal Simek8111aff2016-02-01 15:05:58 +0100313}
314#endif
315
Michal Simek8b353302017-02-07 14:32:26 +0100316int board_early_init_f(void)
317{
Michal Simek1a1ab5a2018-01-15 12:52:59 +0100318#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
Michal Simek09a7d7d2020-01-07 09:02:52 +0100319 int ret;
320
Michal Simekc8785f22018-01-10 11:48:48 +0100321 ret = psu_init();
Michal Simek09a7d7d2020-01-07 09:02:52 +0100322 if (ret)
323 return ret;
Michal Simek1f55e572020-03-20 08:59:02 +0100324
Adrian Fiergolski8e87ecf2021-06-08 12:37:23 +0200325 /*
326 * PS_SYSMON_ANALOG_BUS register determines mapping between SysMon
327 * supply sense channel to SysMon supply registers inside the IP.
328 * This register must be programmed to complete SysMon IP
329 * configuration. The default register configuration after
330 * power-up is incorrect. Hence, fix this by writing the
331 * correct value - 0x3210.
332 */
333 writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
334 ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
335
Michal Simek1f55e572020-03-20 08:59:02 +0100336 /* Delay is required for clocks to be propagated */
337 udelay(1000000);
Michal Simeke0f36102017-07-12 13:08:41 +0200338#endif
339
Michal Simek09a7d7d2020-01-07 09:02:52 +0100340#ifdef CONFIG_DEBUG_UART
341 /* Uart debug for sure */
342 debug_uart_init();
343 puts("Debug uart enabled\n"); /* or printch() */
344#endif
345
346 return 0;
Michal Simek8b353302017-02-07 14:32:26 +0100347}
348
Michal Simek46900462020-02-11 12:43:14 +0100349static int multi_boot(void)
350{
Michal Simek6aca2832021-07-27 16:17:31 +0200351 u32 multiboot = 0;
352 int ret;
Michal Simek46900462020-02-11 12:43:14 +0100353
Michal Simek6aca2832021-07-27 16:17:31 +0200354 ret = zynqmp_mmio_read((ulong)&csu_base->multi_boot, &multiboot);
355 if (ret)
356 return -EINVAL;
Michal Simek46900462020-02-11 12:43:14 +0100357
Michal Simek21e5c322021-07-27 14:05:27 +0200358 return multiboot;
Michal Simek46900462020-02-11 12:43:14 +0100359}
360
Jorge Ramirez-Ortiz34deca52021-10-13 15:48:00 +0200361#if defined(CONFIG_SPL_BUILD)
362static void restore_jtag(void)
363{
364 if (current_el() != 3)
365 return;
366
367 writel(CSU_JTAG_SEC_GATE_DISABLE, &csu_base->jtag_sec);
368 writel(CSU_JTAG_DAP_ENABLE_DEBUG, &csu_base->jtag_dap_cfg);
369 writel(CSU_JTAG_CHAIN_WR_SETUP, &csu_base->jtag_chain_status_wr);
370 writel(CRLAPB_DBG_LPD_CTRL_SETUP_CLK, &crlapb_base->dbg_lpd_ctrl);
371 writel(CRLAPB_RST_LPD_DBG_RESET, &crlapb_base->rst_lpd_dbg);
372 writel(CSU_PCAP_PROG_RELEASE_PL, &csu_base->pcap_prog);
373}
374#endif
375
Mike Looijmans9863e2f2019-10-18 07:34:13 +0200376#define PS_SYSMON_ANALOG_BUS_VAL 0x3210
377#define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914
378
Michal Simek04b7e622015-01-15 10:01:51 +0100379int board_init(void)
380{
Michal Simek826d7eca2020-03-04 08:48:16 +0100381#if defined(CONFIG_ZYNQMP_FIRMWARE)
Ibai Erkiaga2d9b95b2019-09-27 11:37:04 +0100382 struct udevice *dev;
383
384 uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
385 if (!dev)
386 panic("PMU Firmware device not found - Enable it");
Michal Simek826d7eca2020-03-04 08:48:16 +0100387#endif
Ibai Erkiaga2d9b95b2019-09-27 11:37:04 +0100388
Luca Ceresoli23e65002019-05-21 18:06:43 +0200389#if defined(CONFIG_SPL_BUILD)
390 /* Check *at build time* if the filename is an non-empty string */
391 if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
392 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
393 zynqmp_pm_cfg_obj_size);
Michal Simekae9dc112021-02-02 16:34:48 +0100394 printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
Jorge Ramirez-Ortiz34deca52021-10-13 15:48:00 +0200395
396 /* the CSU disables the JTAG interface when secure boot is enabled */
Ricardo Salveti5b774f02021-11-04 16:28:02 -0300397 if (CONFIG_IS_ENABLED(ZYNQMP_RESTORE_JTAG))
Jorge Ramirez-Ortiz34deca52021-10-13 15:48:00 +0200398 restore_jtag();
Michal Simek394ee242020-08-03 13:01:45 +0200399#else
400 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
401 xilinx_read_eeprom();
Luca Ceresoli23e65002019-05-21 18:06:43 +0200402#endif
403
Michal Simekfb7242d2015-06-22 14:31:06 +0200404 printf("EL Level:\tEL%d\n", current_el());
405
Mike Looijmans9863e2f2019-10-18 07:34:13 +0200406 /* Bug in ROM sets wrong value in this register */
407 writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
408
Michal Simek1aab1142020-09-09 14:41:56 +0200409#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
Ibai Erkiagae91ca7c2020-08-04 23:17:29 +0100410 zynqmppl.name = zynqmp_get_silicon_idcode_name();
411 printf("Chip ID:\t%s\n", zynqmppl.name);
412 fpga_init();
413 fpga_add(fpga_xilinx, &zynqmppl);
Michal Simekbf0f9ca2018-04-19 15:43:38 +0200414#endif
415
Michal Simek46900462020-02-11 12:43:14 +0100416 if (current_el() == 3)
Michal Simek21e5c322021-07-27 14:05:27 +0200417 printf("Multiboot:\t%d\n", multi_boot());
Michal Simek46900462020-02-11 12:43:14 +0100418
Michal Simek04b7e622015-01-15 10:01:51 +0100419 return 0;
420}
421
422int board_early_init_r(void)
423{
424 u32 val;
425
Siva Durga Prasad Paladugu64d90002017-12-07 15:05:30 +0530426 if (current_el() != 3)
427 return 0;
428
Michal Simek245d5282017-07-12 10:32:18 +0200429 val = readl(&crlapb_base->timestamp_ref_ctrl);
430 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
431
Siva Durga Prasad Paladugu64d90002017-12-07 15:05:30 +0530432 if (!val) {
Michal Simekc23d3f82015-11-05 08:34:35 +0100433 val = readl(&crlapb_base->timestamp_ref_ctrl);
434 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
435 writel(val, &crlapb_base->timestamp_ref_ctrl);
Michal Simek04b7e622015-01-15 10:01:51 +0100436
Michal Simekc23d3f82015-11-05 08:34:35 +0100437 /* Program freq register in System counter */
438 writel(zynqmp_get_system_timer_freq(),
439 &iou_scntr_secure->base_frequency_id_register);
440 /* And enable system counter */
441 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
442 &iou_scntr_secure->counter_control_register);
443 }
Michal Simek04b7e622015-01-15 10:01:51 +0100444 return 0;
445}
446
Nitin Jainb2eb59b2018-02-16 12:56:17 +0530447unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
Simon Glassed38aef2020-05-10 11:40:03 -0600448 char *const argv[])
Nitin Jainb2eb59b2018-02-16 12:56:17 +0530449{
450 int ret = 0;
451
452 if (current_el() > 1) {
453 smp_kick_all_cpus();
454 dcache_disable();
455 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
456 ES_TO_AARCH64);
457 } else {
458 printf("FAIL: current EL is not above EL1\n");
459 ret = EINVAL;
460 }
461 return ret;
462}
463
Michal Simek8faa66a2016-02-08 09:34:53 +0100464#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
Simon Glass2f949c32017-03-31 08:40:32 -0600465int dram_init_banksize(void)
Michal Simek8faa66a2016-02-08 09:34:53 +0100466{
Nitin Jain9bcc76f2018-04-20 12:30:40 +0530467 int ret;
468
469 ret = fdtdec_setup_memory_banksize();
470 if (ret)
471 return ret;
472
473 mem_map_fill();
474
475 return 0;
Tom Riniedcfdbd2016-12-09 07:56:54 -0500476}
Michal Simek8faa66a2016-02-08 09:34:53 +0100477
Tom Riniedcfdbd2016-12-09 07:56:54 -0500478int dram_init(void)
479{
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +0530480 if (fdtdec_setup_mem_size_base() != 0)
Nathan Rossiac04bfa2016-12-19 00:03:34 +1000481 return -EINVAL;
Tom Riniedcfdbd2016-12-09 07:56:54 -0500482
483 return 0;
Michal Simek8faa66a2016-02-08 09:34:53 +0100484}
Michal Simek97ab9612021-05-31 11:03:19 +0200485
486ulong board_get_usable_ram_top(ulong total_size)
487{
488 phys_size_t size;
489 phys_addr_t reg;
490 struct lmb lmb;
491
Michal Simekf14a4f22021-08-19 11:07:59 +0200492 if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
493 panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
494
Michal Simek97ab9612021-05-31 11:03:19 +0200495 /* found enough not-reserved memory to relocated U-Boot */
496 lmb_init(&lmb);
497 lmb_add(&lmb, gd->ram_base, gd->ram_size);
498 boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
Michal Simek770264e2021-10-21 08:58:50 +0200499 size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
Michal Simek97ab9612021-05-31 11:03:19 +0200500 reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
501
502 if (!reg)
503 reg = gd->ram_top - size;
504
505 return reg + size;
506}
Michal Simek8faa66a2016-02-08 09:34:53 +0100507#else
Nitin Jain9bcc76f2018-04-20 12:30:40 +0530508int dram_init_banksize(void)
509{
Nitin Jain9bcc76f2018-04-20 12:30:40 +0530510 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
511 gd->bd->bi_dram[0].size = get_effective_memsize();
Nitin Jain9bcc76f2018-04-20 12:30:40 +0530512
513 mem_map_fill();
514
515 return 0;
516}
517
Michal Simek04b7e622015-01-15 10:01:51 +0100518int dram_init(void)
519{
Michal Simek1b846212018-04-11 16:12:28 +0200520 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
521 CONFIG_SYS_SDRAM_SIZE);
Michal Simek04b7e622015-01-15 10:01:51 +0100522
523 return 0;
524}
Michal Simek8faa66a2016-02-08 09:34:53 +0100525#endif
Michal Simek04b7e622015-01-15 10:01:51 +0100526
Michal Simek2a220332021-07-13 16:39:26 +0200527#if !CONFIG_IS_ENABLED(SYSRESET)
Harald Seiler6f14d5f2020-12-15 16:47:52 +0100528void reset_cpu(void)
Michal Simek04b7e622015-01-15 10:01:51 +0100529{
530}
Michal Simek2a220332021-07-13 16:39:26 +0200531#endif
Michal Simek04b7e622015-01-15 10:01:51 +0100532
Michal Simek8ec30042020-08-20 10:54:45 +0200533static u8 __maybe_unused zynqmp_get_bootmode(void)
534{
535 u8 bootmode;
536 u32 reg = 0;
537 int ret;
538
539 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
540 if (ret)
541 return -EINVAL;
542
Michal Simek58cc08c2021-07-28 12:25:49 +0200543 debug("HW boot mode: %x\n", reg & BOOT_MODES_MASK);
544 debug("ALT boot mode: %x\n", reg >> BOOT_MODE_ALT_SHIFT);
545
Michal Simek8ec30042020-08-20 10:54:45 +0200546 if (reg >> BOOT_MODE_ALT_SHIFT)
547 reg >>= BOOT_MODE_ALT_SHIFT;
548
549 bootmode = reg & BOOT_MODES_MASK;
550
551 return bootmode;
552}
553
Michal Simek342edfe2018-12-20 09:33:38 +0100554#if defined(CONFIG_BOARD_LATE_INIT)
Michal Simek29b9b712018-05-17 14:06:06 +0200555static const struct {
556 u32 bit;
557 const char *name;
558} reset_reasons[] = {
559 { RESET_REASON_DEBUG_SYS, "DEBUG" },
560 { RESET_REASON_SOFT, "SOFT" },
561 { RESET_REASON_SRST, "SRST" },
562 { RESET_REASON_PSONLY, "PS-ONLY" },
563 { RESET_REASON_PMU, "PMU" },
564 { RESET_REASON_INTERNAL, "INTERNAL" },
565 { RESET_REASON_EXTERNAL, "EXTERNAL" },
566 {}
567};
568
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530569static int reset_reason(void)
Michal Simek29b9b712018-05-17 14:06:06 +0200570{
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530571 u32 reg;
572 int i, ret;
Michal Simek29b9b712018-05-17 14:06:06 +0200573 const char *reason = NULL;
574
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530575 ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
576 if (ret)
577 return -EINVAL;
Michal Simek29b9b712018-05-17 14:06:06 +0200578
579 puts("Reset reason:\t");
580
581 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530582 if (reg & reset_reasons[i].bit) {
Michal Simek29b9b712018-05-17 14:06:06 +0200583 reason = reset_reasons[i].name;
584 printf("%s ", reset_reasons[i].name);
585 break;
586 }
587 }
588
589 puts("\n");
590
591 env_set("reset_reason", reason);
592
Michal Simek0954c8c2021-02-09 08:50:22 +0100593 return 0;
Michal Simek29b9b712018-05-17 14:06:06 +0200594}
595
Michal Simek1ca66d72019-02-14 13:14:30 +0100596static int set_fdtfile(void)
597{
598 char *compatible, *fdtfile;
599 const char *suffix = ".dtb";
600 const char *vendor = "xilinx/";
Igor Lantsmane167bac2020-06-24 14:33:46 +0200601 int fdt_compat_len;
Michal Simek1ca66d72019-02-14 13:14:30 +0100602
603 if (env_get("fdtfile"))
604 return 0;
605
Igor Lantsmane167bac2020-06-24 14:33:46 +0200606 compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
607 &fdt_compat_len);
608 if (compatible && fdt_compat_len) {
609 char *name;
610
Michal Simek1ca66d72019-02-14 13:14:30 +0100611 debug("Compatible: %s\n", compatible);
612
Igor Lantsmane167bac2020-06-24 14:33:46 +0200613 name = strchr(compatible, ',');
614 if (!name)
615 return -EINVAL;
Michal Simek1ca66d72019-02-14 13:14:30 +0100616
Igor Lantsmane167bac2020-06-24 14:33:46 +0200617 name++;
618
619 fdtfile = calloc(1, strlen(vendor) + strlen(name) +
Michal Simek1ca66d72019-02-14 13:14:30 +0100620 strlen(suffix) + 1);
621 if (!fdtfile)
622 return -ENOMEM;
623
Igor Lantsmane167bac2020-06-24 14:33:46 +0200624 sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
Michal Simek1ca66d72019-02-14 13:14:30 +0100625
626 env_set("fdtfile", fdtfile);
627 free(fdtfile);
628 }
629
630 return 0;
631}
632
Michal Simek9c91e612020-04-08 11:04:41 +0200633int board_late_init(void)
634{
Michal Simek04b7e622015-01-15 10:01:51 +0100635 u8 bootmode;
Michal Simekf183a982018-04-25 11:20:43 +0200636 struct udevice *dev;
637 int bootseq = -1;
638 int bootseq_len = 0;
Michal Simek7410b142018-04-25 11:10:34 +0200639 int env_targets_len = 0;
Michal Simekecfb6dc2016-04-22 14:28:54 +0200640 const char *mode;
641 char *new_targets;
Siva Durga Prasad Paladugu245c5562017-12-20 16:35:06 +0530642 char *env_targets;
Michal Simek7cb4cca2021-10-25 10:10:52 +0200643 int ret, multiboot;
Michal Simekecfb6dc2016-04-22 14:28:54 +0200644
Michal Simek482f5492018-10-05 08:55:16 +0200645#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
646 usb_ether_init();
647#endif
648
Michal Simekecfb6dc2016-04-22 14:28:54 +0200649 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
650 debug("Saved variables - Skipping\n");
651 return 0;
652 }
Michal Simek04b7e622015-01-15 10:01:51 +0100653
Michal Simekbab07b62020-07-28 12:45:47 +0200654 if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
655 return 0;
656
Michal Simek1ca66d72019-02-14 13:14:30 +0100657 ret = set_fdtfile();
658 if (ret)
659 return ret;
660
Michal Simek7cb4cca2021-10-25 10:10:52 +0200661 multiboot = multi_boot();
662 if (multiboot >= 0)
663 env_set_hex("multiboot", multiboot);
664
Michal Simek9c91e612020-04-08 11:04:41 +0200665 bootmode = zynqmp_get_bootmode();
Michal Simek04b7e622015-01-15 10:01:51 +0100666
Michal Simekc5d95232015-09-20 17:20:42 +0200667 puts("Bootmode: ");
Michal Simek04b7e622015-01-15 10:01:51 +0100668 switch (bootmode) {
Michal Simek12398ea2016-08-19 14:14:52 +0200669 case USB_MODE:
670 puts("USB_MODE\n");
T Karthik Reddy9eee8e32021-03-24 23:37:57 -0600671 mode = "usb_dfu0 usb_dfu1";
Michal Simek43380352017-12-01 15:18:24 +0100672 env_set("modeboot", "usb_dfu_spl");
Michal Simek12398ea2016-08-19 14:14:52 +0200673 break;
Siva Durga Prasad Paladugu30f0fc72015-03-13 11:10:26 +0530674 case JTAG_MODE:
Michal Simekc5d95232015-09-20 17:20:42 +0200675 puts("JTAG_MODE\n");
Siva Durga Prasad Paladugu9c441702019-06-25 17:41:09 +0530676 mode = "jtag pxe dhcp";
Michal Simek43380352017-12-01 15:18:24 +0100677 env_set("modeboot", "jtagboot");
Siva Durga Prasad Paladugu30f0fc72015-03-13 11:10:26 +0530678 break;
679 case QSPI_MODE_24BIT:
680 case QSPI_MODE_32BIT:
Michal Simekecfb6dc2016-04-22 14:28:54 +0200681 mode = "qspi0";
Michal Simekc5d95232015-09-20 17:20:42 +0200682 puts("QSPI_MODE\n");
Michal Simek43380352017-12-01 15:18:24 +0100683 env_set("modeboot", "qspiboot");
Siva Durga Prasad Paladugu30f0fc72015-03-13 11:10:26 +0530684 break;
Michal Simek02d66cd2015-04-15 15:02:28 +0200685 case EMMC_MODE:
Michal Simekdf7ff0a2015-10-05 15:59:38 +0200686 puts("EMMC_MODE\n");
T Karthik Reddy19735c32019-12-17 06:41:42 -0700687 if (uclass_get_device_by_name(UCLASS_MMC,
688 "mmc@ff160000", &dev) &&
689 uclass_get_device_by_name(UCLASS_MMC,
690 "sdhci@ff160000", &dev)) {
691 puts("Boot from EMMC but without SD0 enabled!\n");
692 return -1;
693 }
Simon Glass75e534b2020-12-16 21:20:07 -0700694 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
T Karthik Reddy19735c32019-12-17 06:41:42 -0700695
696 mode = "mmc";
Simon Glass75e534b2020-12-16 21:20:07 -0700697 bootseq = dev_seq(dev);
Ashok Reddy Somaa10be052021-09-15 08:52:17 +0200698 env_set("modeboot", "emmcboot");
Michal Simekdf7ff0a2015-10-05 15:59:38 +0200699 break;
700 case SD_MODE:
Michal Simekc5d95232015-09-20 17:20:42 +0200701 puts("SD_MODE\n");
Michal Simekf183a982018-04-25 11:20:43 +0200702 if (uclass_get_device_by_name(UCLASS_MMC,
Siva Durga Prasad Paladugue91778d2019-01-03 15:44:24 +0530703 "mmc@ff160000", &dev) &&
704 uclass_get_device_by_name(UCLASS_MMC,
Michal Simekf183a982018-04-25 11:20:43 +0200705 "sdhci@ff160000", &dev)) {
706 puts("Boot from SD0 but without SD0 enabled!\n");
707 return -1;
708 }
Simon Glass75e534b2020-12-16 21:20:07 -0700709 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
Michal Simekf183a982018-04-25 11:20:43 +0200710
711 mode = "mmc";
Simon Glass75e534b2020-12-16 21:20:07 -0700712 bootseq = dev_seq(dev);
Michal Simek43380352017-12-01 15:18:24 +0100713 env_set("modeboot", "sdboot");
Michal Simek04b7e622015-01-15 10:01:51 +0100714 break;
Siva Durga Prasad Paladugu29a77d22016-09-21 11:45:05 +0530715 case SD1_LSHFT_MODE:
716 puts("LVL_SHFT_");
Michal Simek293f47b2021-10-18 13:30:04 +0200717 fallthrough;
Michal Simek108e1842015-10-05 10:51:12 +0200718 case SD_MODE1:
Michal Simekc5d95232015-09-20 17:20:42 +0200719 puts("SD_MODE1\n");
Michal Simekf183a982018-04-25 11:20:43 +0200720 if (uclass_get_device_by_name(UCLASS_MMC,
Siva Durga Prasad Paladugue91778d2019-01-03 15:44:24 +0530721 "mmc@ff170000", &dev) &&
722 uclass_get_device_by_name(UCLASS_MMC,
Michal Simekf183a982018-04-25 11:20:43 +0200723 "sdhci@ff170000", &dev)) {
724 puts("Boot from SD1 but without SD1 enabled!\n");
725 return -1;
726 }
Simon Glass75e534b2020-12-16 21:20:07 -0700727 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
Michal Simekf183a982018-04-25 11:20:43 +0200728
729 mode = "mmc";
Simon Glass75e534b2020-12-16 21:20:07 -0700730 bootseq = dev_seq(dev);
Michal Simek43380352017-12-01 15:18:24 +0100731 env_set("modeboot", "sdboot");
Michal Simek108e1842015-10-05 10:51:12 +0200732 break;
733 case NAND_MODE:
Michal Simekc5d95232015-09-20 17:20:42 +0200734 puts("NAND_MODE\n");
Michal Simekecfb6dc2016-04-22 14:28:54 +0200735 mode = "nand0";
Michal Simek43380352017-12-01 15:18:24 +0100736 env_set("modeboot", "nandboot");
Michal Simek108e1842015-10-05 10:51:12 +0200737 break;
Michal Simek04b7e622015-01-15 10:01:51 +0100738 default:
Michal Simekecfb6dc2016-04-22 14:28:54 +0200739 mode = "";
Michal Simek04b7e622015-01-15 10:01:51 +0100740 printf("Invalid Boot Mode:0x%x\n", bootmode);
741 break;
742 }
743
Michal Simekf183a982018-04-25 11:20:43 +0200744 if (bootseq >= 0) {
745 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
746 debug("Bootseq len: %x\n", bootseq_len);
Michal Simek7a117c72021-01-11 13:46:58 +0100747 env_set_hex("bootseq", bootseq);
Michal Simekf183a982018-04-25 11:20:43 +0200748 }
749
Michal Simekecfb6dc2016-04-22 14:28:54 +0200750 /*
751 * One terminating char + one byte for space between mode
752 * and default boot_targets
753 */
Siva Durga Prasad Paladugu245c5562017-12-20 16:35:06 +0530754 env_targets = env_get("boot_targets");
Michal Simek7410b142018-04-25 11:10:34 +0200755 if (env_targets)
756 env_targets_len = strlen(env_targets);
757
Michal Simekf183a982018-04-25 11:20:43 +0200758 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
759 bootseq_len);
Michal Simek089b84d2018-06-13 09:42:41 +0200760 if (!new_targets)
761 return -ENOMEM;
Michal Simek7410b142018-04-25 11:10:34 +0200762
Michal Simekf183a982018-04-25 11:20:43 +0200763 if (bootseq >= 0)
764 sprintf(new_targets, "%s%x %s", mode, bootseq,
765 env_targets ? env_targets : "");
766 else
767 sprintf(new_targets, "%s %s", mode,
768 env_targets ? env_targets : "");
Michal Simekecfb6dc2016-04-22 14:28:54 +0200769
Simon Glass6a38e412017-08-03 12:22:09 -0600770 env_set("boot_targets", new_targets);
Michal Simek77488232021-07-28 12:46:39 +0200771 free(new_targets);
Michal Simekecfb6dc2016-04-22 14:28:54 +0200772
Michal Simek29b9b712018-05-17 14:06:06 +0200773 reset_reason();
774
Michal Simek705d44a2020-03-31 12:39:37 +0200775 return board_late_init_xilinx();
Michal Simek04b7e622015-01-15 10:01:51 +0100776}
Michal Simek342edfe2018-12-20 09:33:38 +0100777#endif
Siva Durga Prasad Paladugu650e0a32015-08-04 13:01:05 +0530778
779int checkboard(void)
780{
Michal Simek47ce9362016-01-25 11:04:21 +0100781 puts("Board: Xilinx ZynqMP\n");
Siva Durga Prasad Paladugu650e0a32015-08-04 13:01:05 +0530782 return 0;
783}
Michal Simek8d4a8d42020-07-30 13:37:49 +0200784
Michal Simeke0026bf2021-05-19 15:16:19 +0200785int mmc_get_env_dev(void)
786{
787 struct udevice *dev;
788 int bootseq = 0;
789
790 switch (zynqmp_get_bootmode()) {
791 case EMMC_MODE:
792 case SD_MODE:
793 if (uclass_get_device_by_name(UCLASS_MMC,
794 "mmc@ff160000", &dev) &&
795 uclass_get_device_by_name(UCLASS_MMC,
796 "sdhci@ff160000", &dev)) {
797 return -1;
798 }
799 bootseq = dev_seq(dev);
800 break;
801 case SD1_LSHFT_MODE:
802 case SD_MODE1:
803 if (uclass_get_device_by_name(UCLASS_MMC,
804 "mmc@ff170000", &dev) &&
805 uclass_get_device_by_name(UCLASS_MMC,
806 "sdhci@ff170000", &dev)) {
807 return -1;
808 }
809 bootseq = dev_seq(dev);
810 break;
811 default:
812 break;
813 }
814
815 debug("bootseq %d\n", bootseq);
816
817 return bootseq;
818}
819
Michal Simek8d4a8d42020-07-30 13:37:49 +0200820enum env_location env_get_location(enum env_operation op, int prio)
821{
822 u32 bootmode = zynqmp_get_bootmode();
823
824 if (prio)
825 return ENVL_UNKNOWN;
826
827 switch (bootmode) {
828 case EMMC_MODE:
829 case SD_MODE:
830 case SD1_LSHFT_MODE:
831 case SD_MODE1:
832 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
833 return ENVL_FAT;
834 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
835 return ENVL_EXT4;
Mike Looijmans682cf082021-07-02 10:28:36 +0200836 return ENVL_NOWHERE;
Michal Simek8d4a8d42020-07-30 13:37:49 +0200837 case NAND_MODE:
838 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
839 return ENVL_NAND;
840 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
841 return ENVL_UBI;
Mike Looijmans682cf082021-07-02 10:28:36 +0200842 return ENVL_NOWHERE;
Michal Simek8d4a8d42020-07-30 13:37:49 +0200843 case QSPI_MODE_24BIT:
844 case QSPI_MODE_32BIT:
845 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
846 return ENVL_SPI_FLASH;
Mike Looijmans682cf082021-07-02 10:28:36 +0200847 return ENVL_NOWHERE;
Michal Simek8d4a8d42020-07-30 13:37:49 +0200848 case JTAG_MODE:
849 default:
850 return ENVL_NOWHERE;
851 }
852}
Michal Simekcfb37602021-07-27 16:19:18 +0200853
854#if defined(CONFIG_SET_DFU_ALT_INFO)
855
856#define DFU_ALT_BUF_LEN SZ_1K
857
858void set_dfu_alt_info(char *interface, char *devstr)
859{
860 u8 multiboot;
861 int bootseq = 0;
862
863 ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
864
865 if (env_get("dfu_alt_info"))
866 return;
867
868 memset(buf, 0, sizeof(buf));
869
870 multiboot = multi_boot();
Michal Simek7cb4cca2021-10-25 10:10:52 +0200871 if (multiboot < 0)
872 multiboot = 0;
873
874 multiboot = env_get_hex("multiboot", multiboot);
Michal Simekcfb37602021-07-27 16:19:18 +0200875 debug("Multiboot: %d\n", multiboot);
876
877 switch (zynqmp_get_bootmode()) {
878 case EMMC_MODE:
879 case SD_MODE:
880 case SD1_LSHFT_MODE:
881 case SD_MODE1:
882 bootseq = mmc_get_env_dev();
883 if (!multiboot)
884 snprintf(buf, DFU_ALT_BUF_LEN,
885 "mmc %d:1=boot.bin fat %d 1;"
Michal Simek69103192021-10-18 14:02:15 +0200886 "%s fat %d 1",
887 bootseq, bootseq,
888 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
Michal Simekcfb37602021-07-27 16:19:18 +0200889 else
890 snprintf(buf, DFU_ALT_BUF_LEN,
891 "mmc %d:1=boot%04d.bin fat %d 1;"
Michal Simek69103192021-10-18 14:02:15 +0200892 "%s fat %d 1",
893 bootseq, multiboot, bootseq,
894 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
Michal Simekcfb37602021-07-27 16:19:18 +0200895 break;
896 case QSPI_MODE_24BIT:
897 case QSPI_MODE_32BIT:
898 snprintf(buf, DFU_ALT_BUF_LEN,
899 "sf 0:0=boot.bin raw %x 0x1500000;"
Michal Simek69103192021-10-18 14:02:15 +0200900 "%s raw 0x%x 0x500000",
901 multiboot * SZ_32K, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
902 CONFIG_SYS_SPI_U_BOOT_OFFS);
Michal Simekcfb37602021-07-27 16:19:18 +0200903 break;
904 default:
905 return;
906 }
907
908 env_set("dfu_alt_info", buf);
909 puts("DFU alt info setting: done\n");
910}
911#endif