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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Bin Meng2229c4c2015-05-07 21:34:08 +08002/*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
Bin Meng2229c4c2015-05-07 21:34:08 +08004 */
5
6#ifndef _ARCH_QEMU_H_
7#define _ARCH_QEMU_H_
8
Bin Menga8b70a12015-05-24 00:12:33 +08009/* Programmable Attribute Map (PAM) Registers */
10#define I440FX_PAM 0x59
11#define Q35_PAM 0x90
12#define PAM_NUM 7
13#define PAM_RW 0x33
14
Bin Meng8f71dc82015-07-22 01:21:11 -070015/* X-Bus Chip Select Register */
16#define XBCS 0x4e
17#define APIC_EN (1 << 8)
18
Bin Meng19c77392015-05-25 22:36:26 +080019/* IDE Timing Register */
20#define IDE0_TIM 0x40
21#define IDE1_TIM 0x42
Bin Meng8f71dc82015-07-22 01:21:11 -070022#define IDE_DECODE_EN (1 << 15)
Bin Meng19c77392015-05-25 22:36:26 +080023
Bin Meng33e140d2015-07-22 01:21:14 -070024/* PCIe ECAM Base Address Register */
25#define PCIEX_BAR 0x60
26#define BAR_EN (1 << 0)
27
Bin Meng2229c4c2015-05-07 21:34:08 +080028/* I/O Ports */
29#define CMOS_ADDR_PORT 0x70
30#define CMOS_DATA_PORT 0x71
31
32#define LOW_RAM_ADDR 0x34
33#define HIGH_RAM_ADDR 0x35
34
Bin Mengfc7f57f2019-08-29 02:53:05 -070035#define LOW_HIGHRAM_ADDR 0x5b
36#define MID_HIGHRAM_ADDR 0x5c
37#define HIGH_HIGHRAM_ADDR 0x5d
38
Miao Yan35603ff2016-01-20 01:57:05 -080039/* PM registers */
40#define PMBA 0x40
41#define PMREGMISC 0x80
42#define PMIOSE (1 << 0)
43
Bin Meng38502eb2019-08-29 02:53:04 -070044/**
45 * qemu_get_low_memory_size() - Get low memory size
46 *
47 * @return: size of memory below 4GiB
48 */
49u32 qemu_get_low_memory_size(void);
50
Bin Mengfc7f57f2019-08-29 02:53:05 -070051/**
52 * qemu_get_high_memory_size() - Get high memory size
53 *
54 * @return: size of memory above 4GiB
55 */
56u64 qemu_get_high_memory_size(void);
57
Bin Meng2229c4c2015-05-07 21:34:08 +080058#endif /* _ARCH_QEMU_H_ */