| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
| Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _ARCH_QEMU_H_ |
| 7 | #define _ARCH_QEMU_H_ |
| 8 | |
| Bin Meng | a8b70a1 | 2015-05-24 00:12:33 +0800 | [diff] [blame] | 9 | /* Programmable Attribute Map (PAM) Registers */ |
| 10 | #define I440FX_PAM 0x59 |
| 11 | #define Q35_PAM 0x90 |
| 12 | #define PAM_NUM 7 |
| 13 | #define PAM_RW 0x33 |
| 14 | |
| Bin Meng | 8f71dc8 | 2015-07-22 01:21:11 -0700 | [diff] [blame] | 15 | /* X-Bus Chip Select Register */ |
| 16 | #define XBCS 0x4e |
| 17 | #define APIC_EN (1 << 8) |
| 18 | |
| Bin Meng | 19c7739 | 2015-05-25 22:36:26 +0800 | [diff] [blame] | 19 | /* IDE Timing Register */ |
| 20 | #define IDE0_TIM 0x40 |
| 21 | #define IDE1_TIM 0x42 |
| Bin Meng | 8f71dc8 | 2015-07-22 01:21:11 -0700 | [diff] [blame] | 22 | #define IDE_DECODE_EN (1 << 15) |
| Bin Meng | 19c7739 | 2015-05-25 22:36:26 +0800 | [diff] [blame] | 23 | |
| Bin Meng | 33e140d | 2015-07-22 01:21:14 -0700 | [diff] [blame] | 24 | /* PCIe ECAM Base Address Register */ |
| 25 | #define PCIEX_BAR 0x60 |
| 26 | #define BAR_EN (1 << 0) |
| 27 | |
| Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 28 | /* I/O Ports */ |
| 29 | #define CMOS_ADDR_PORT 0x70 |
| 30 | #define CMOS_DATA_PORT 0x71 |
| 31 | |
| 32 | #define LOW_RAM_ADDR 0x34 |
| 33 | #define HIGH_RAM_ADDR 0x35 |
| 34 | |
| Miao Yan | 35603ff | 2016-01-20 01:57:05 -0800 | [diff] [blame] | 35 | /* PM registers */ |
| 36 | #define PMBA 0x40 |
| 37 | #define PMREGMISC 0x80 |
| 38 | #define PMIOSE (1 << 0) |
| 39 | |
| Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 40 | #endif /* _ARCH_QEMU_H_ */ |