Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 2 | /* |
Ley Foon Tan | b149f2b | 2017-04-26 02:44:36 +0800 | [diff] [blame] | 3 | * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> |
Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 7 | #include <cpu_func.h> |
Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 8 | #include <asm/io.h> |
Dinh Nguyen | 8ed6661 | 2015-08-01 03:42:10 +0200 | [diff] [blame] | 9 | #include <errno.h> |
Marek Vasut | f3f8fe2 | 2015-07-25 19:33:56 +0200 | [diff] [blame] | 10 | #include <fdtdec.h> |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 11 | #include <linux/libfdt.h> |
Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 12 | #include <altera.h> |
Pavel Machek | ce340e9 | 2014-07-14 14:14:17 +0200 | [diff] [blame] | 13 | #include <miiphy.h> |
| 14 | #include <netdev.h> |
Stefan Roese | 3bfb591 | 2014-12-19 13:49:10 +0100 | [diff] [blame] | 15 | #include <watchdog.h> |
Ley Foon Tan | b149f2b | 2017-04-26 02:44:36 +0800 | [diff] [blame] | 16 | #include <asm/arch/misc.h> |
Pavel Machek | 56a00ab | 2014-09-09 14:03:28 +0200 | [diff] [blame] | 17 | #include <asm/arch/reset_manager.h> |
Dinh Nguyen | 8ed6661 | 2015-08-01 03:42:10 +0200 | [diff] [blame] | 18 | #include <asm/arch/scan_manager.h> |
Pavel Machek | 57d75eb | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 19 | #include <asm/arch/system_manager.h> |
Marek Vasut | 56916e4 | 2014-09-15 03:58:22 +0200 | [diff] [blame] | 20 | #include <asm/arch/nic301.h> |
Pavel Machek | e918e33 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 21 | #include <asm/arch/scu.h> |
Marek Vasut | 56916e4 | 2014-09-15 03:58:22 +0200 | [diff] [blame] | 22 | #include <asm/pl310.h> |
Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 23 | |
| 24 | DECLARE_GLOBAL_DATA_PTR; |
| 25 | |
Ley Foon Tan | 2669591 | 2019-11-08 10:38:21 +0800 | [diff] [blame] | 26 | phys_addr_t socfpga_clkmgr_base __section(".data"); |
Ley Foon Tan | fed4c95 | 2019-11-08 10:38:19 +0800 | [diff] [blame] | 27 | phys_addr_t socfpga_rstmgr_base __section(".data"); |
Ley Foon Tan | 3d3a860 | 2019-11-08 10:38:20 +0800 | [diff] [blame] | 28 | phys_addr_t socfpga_sysmgr_base __section(".data"); |
Ley Foon Tan | fed4c95 | 2019-11-08 10:38:19 +0800 | [diff] [blame] | 29 | |
Ley Foon Tan | 6fa091d | 2018-05-18 22:05:25 +0800 | [diff] [blame] | 30 | #ifdef CONFIG_SYS_L2_PL310 |
Ley Foon Tan | b149f2b | 2017-04-26 02:44:36 +0800 | [diff] [blame] | 31 | static const struct pl310_regs *const pl310 = |
Marek Vasut | 56916e4 | 2014-09-15 03:58:22 +0200 | [diff] [blame] | 32 | (struct pl310_regs *)CONFIG_SYS_PL310_BASE; |
Ley Foon Tan | 6fa091d | 2018-05-18 22:05:25 +0800 | [diff] [blame] | 33 | #endif |
Ley Foon Tan | b149f2b | 2017-04-26 02:44:36 +0800 | [diff] [blame] | 34 | |
| 35 | struct bsel bsel_str[] = { |
| 36 | { "rsvd", "Reserved", }, |
| 37 | { "fpga", "FPGA (HPS2FPGA Bridge)", }, |
| 38 | { "nand", "NAND Flash (1.8V)", }, |
| 39 | { "nand", "NAND Flash (3.0V)", }, |
| 40 | { "sd", "SD/MMC External Transceiver (1.8V)", }, |
| 41 | { "sd", "SD/MMC Internal Transceiver (3.0V)", }, |
| 42 | { "qspi", "QSPI Flash (1.8V)", }, |
| 43 | { "qspi", "QSPI Flash (3.0V)", }, |
| 44 | }; |
Pavel Machek | 57d75eb | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 45 | |
Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 46 | int dram_init(void) |
| 47 | { |
Siva Durga Prasad Paladugu | b3d55ea | 2018-07-16 15:56:11 +0530 | [diff] [blame] | 48 | if (fdtdec_setup_mem_size_base() != 0) |
Marek Vasut | 1530317 | 2018-05-28 17:09:45 +0200 | [diff] [blame] | 49 | return -EINVAL; |
| 50 | |
Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 51 | return 0; |
| 52 | } |
Pavel Machek | 57d75eb | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 53 | |
Marek Vasut | d515794 | 2014-09-21 13:57:40 +0200 | [diff] [blame] | 54 | void enable_caches(void) |
| 55 | { |
Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 56 | #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) |
Marek Vasut | d515794 | 2014-09-21 13:57:40 +0200 | [diff] [blame] | 57 | icache_enable(); |
| 58 | #endif |
Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 59 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) |
Marek Vasut | d515794 | 2014-09-21 13:57:40 +0200 | [diff] [blame] | 60 | dcache_enable(); |
| 61 | #endif |
| 62 | } |
| 63 | |
Ley Foon Tan | 6fa091d | 2018-05-18 22:05:25 +0800 | [diff] [blame] | 64 | #ifdef CONFIG_SYS_L2_PL310 |
Dinh Nguyen | e89ff70 | 2015-10-15 10:13:36 -0500 | [diff] [blame] | 65 | void v7_outer_cache_enable(void) |
| 66 | { |
Dinh Nguyen | 86fbf9d | 2019-04-23 16:55:05 -0500 | [diff] [blame] | 67 | struct udevice *dev; |
Marek Vasut | 9f7b30d | 2015-12-20 04:00:09 +0100 | [diff] [blame] | 68 | |
Dinh Nguyen | 86fbf9d | 2019-04-23 16:55:05 -0500 | [diff] [blame] | 69 | if (uclass_get_device(UCLASS_CACHE, 0, &dev)) |
| 70 | pr_err("cache controller driver NOT found!\n"); |
Marek Vasut | 9f7b30d | 2015-12-20 04:00:09 +0100 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | void v7_outer_cache_disable(void) |
| 74 | { |
| 75 | /* Disable the L2 cache */ |
| 76 | clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); |
Dinh Nguyen | e89ff70 | 2015-10-15 10:13:36 -0500 | [diff] [blame] | 77 | } |
Marek Vasut | b6ba490 | 2019-03-21 23:05:38 +0100 | [diff] [blame] | 78 | |
| 79 | void socfpga_pl310_clear(void) |
| 80 | { |
| 81 | u32 mask = 0xff, ena = 0; |
| 82 | |
| 83 | icache_enable(); |
| 84 | |
| 85 | /* Disable the L2 cache */ |
| 86 | clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); |
| 87 | |
| 88 | writel(0x0, &pl310->pl310_tag_latency_ctrl); |
| 89 | writel(0x10, &pl310->pl310_data_latency_ctrl); |
| 90 | |
| 91 | /* enable BRESP, instruction and data prefetch, full line of zeroes */ |
| 92 | setbits_le32(&pl310->pl310_aux_ctrl, |
| 93 | L310_AUX_CTRL_DATA_PREFETCH_MASK | |
| 94 | L310_AUX_CTRL_INST_PREFETCH_MASK | |
| 95 | L310_SHARED_ATT_OVERRIDE_ENABLE); |
| 96 | |
| 97 | /* Enable the L2 cache */ |
| 98 | ena = readl(&pl310->pl310_ctrl); |
| 99 | ena |= L2X0_CTRL_EN; |
| 100 | |
| 101 | /* |
| 102 | * Invalidate the PL310 L2 cache. Keep the invalidation code |
| 103 | * entirely in L1 I-cache to avoid any bus traffic through |
| 104 | * the L2. |
| 105 | */ |
| 106 | asm volatile( |
| 107 | ".align 5 \n" |
| 108 | " b 3f \n" |
| 109 | "1: str %1, [%4] \n" |
| 110 | " dsb \n" |
| 111 | " isb \n" |
| 112 | " str %0, [%2] \n" |
| 113 | " dsb \n" |
| 114 | " isb \n" |
| 115 | "2: ldr %0, [%2] \n" |
| 116 | " cmp %0, #0 \n" |
| 117 | " bne 2b \n" |
| 118 | " str %0, [%3] \n" |
| 119 | " dsb \n" |
| 120 | " isb \n" |
| 121 | " b 4f \n" |
| 122 | "3: b 1b \n" |
| 123 | "4: nop \n" |
| 124 | : "+r"(mask), "+r"(ena) |
| 125 | : "r"(&pl310->pl310_inv_way), |
| 126 | "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) |
| 127 | : "memory", "cc"); |
| 128 | |
| 129 | /* Disable the L2 cache */ |
| 130 | clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); |
| 131 | } |
Ley Foon Tan | 6fa091d | 2018-05-18 22:05:25 +0800 | [diff] [blame] | 132 | #endif |
Dinh Nguyen | e89ff70 | 2015-10-15 10:13:36 -0500 | [diff] [blame] | 133 | |
Chin Liang See | bff262c | 2014-06-10 02:23:45 -0500 | [diff] [blame] | 134 | #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ |
| 135 | defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) |
| 136 | int overwrite_console(void) |
| 137 | { |
| 138 | return 0; |
| 139 | } |
| 140 | #endif |
| 141 | |
Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 142 | #ifdef CONFIG_FPGA |
Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 143 | /* add device descriptor to FPGA device table */ |
Ang, Chee Hong | ff14f16 | 2018-12-19 18:35:15 -0800 | [diff] [blame] | 144 | void socfpga_fpga_add(void *fpga_desc) |
Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 145 | { |
Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 146 | fpga_init(); |
Ang, Chee Hong | ff14f16 | 2018-12-19 18:35:15 -0800 | [diff] [blame] | 147 | fpga_add(fpga_altera, fpga_desc); |
Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 148 | } |
Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 149 | #endif |
| 150 | |
Pavel Machek | 56a00ab | 2014-09-09 14:03:28 +0200 | [diff] [blame] | 151 | int arch_cpu_init(void) |
| 152 | { |
Ley Foon Tan | fed4c95 | 2019-11-08 10:38:19 +0800 | [diff] [blame] | 153 | socfpga_get_managers_addr(); |
| 154 | |
Stefan Roese | 3bfb591 | 2014-12-19 13:49:10 +0100 | [diff] [blame] | 155 | #ifdef CONFIG_HW_WATCHDOG |
| 156 | /* |
| 157 | * In case the watchdog is enabled, make sure to (re-)configure it |
| 158 | * so that the defined timeout is valid. Otherwise the SPL (Perloader) |
| 159 | * timeout value is still active which might too short for Linux |
| 160 | * booting. |
| 161 | */ |
| 162 | hw_watchdog_init(); |
| 163 | #else |
Pavel Machek | 56a00ab | 2014-09-09 14:03:28 +0200 | [diff] [blame] | 164 | /* |
| 165 | * If the HW watchdog is NOT enabled, make sure it is not running, |
| 166 | * for example because it was enabled in the preloader. This might |
| 167 | * trigger a watchdog-triggered reboot of Linux kernel later. |
Marek Vasut | 75f6b5c | 2015-07-09 02:51:56 +0200 | [diff] [blame] | 168 | * Toggle watchdog reset, so watchdog in not running state. |
Pavel Machek | 56a00ab | 2014-09-09 14:03:28 +0200 | [diff] [blame] | 169 | */ |
Marek Vasut | 75f6b5c | 2015-07-09 02:51:56 +0200 | [diff] [blame] | 170 | socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); |
| 171 | socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); |
Pavel Machek | 56a00ab | 2014-09-09 14:03:28 +0200 | [diff] [blame] | 172 | #endif |
Stefan Roese | 3bfb591 | 2014-12-19 13:49:10 +0100 | [diff] [blame] | 173 | |
Pavel Machek | 56a00ab | 2014-09-09 14:03:28 +0200 | [diff] [blame] | 174 | return 0; |
| 175 | } |
Marek Vasut | 3386c85 | 2018-04-23 22:49:31 +0200 | [diff] [blame] | 176 | |
Ley Foon Tan | 4cc6b58 | 2018-05-24 00:17:23 +0800 | [diff] [blame] | 177 | #ifndef CONFIG_SPL_BUILD |
| 178 | static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
| 179 | { |
Marek Vasut | 713a8a2 | 2019-04-16 22:28:08 +0200 | [diff] [blame] | 180 | unsigned int mask = ~0; |
| 181 | |
| 182 | if (argc < 2 || argc > 3) |
Ley Foon Tan | 4cc6b58 | 2018-05-24 00:17:23 +0800 | [diff] [blame] | 183 | return CMD_RET_USAGE; |
| 184 | |
| 185 | argv++; |
| 186 | |
Marek Vasut | 713a8a2 | 2019-04-16 22:28:08 +0200 | [diff] [blame] | 187 | if (argc == 3) |
| 188 | mask = simple_strtoul(argv[1], NULL, 16); |
| 189 | |
Ley Foon Tan | 4cc6b58 | 2018-05-24 00:17:23 +0800 | [diff] [blame] | 190 | switch (*argv[0]) { |
| 191 | case 'e': /* Enable */ |
Marek Vasut | 713a8a2 | 2019-04-16 22:28:08 +0200 | [diff] [blame] | 192 | do_bridge_reset(1, mask); |
Ley Foon Tan | 4cc6b58 | 2018-05-24 00:17:23 +0800 | [diff] [blame] | 193 | break; |
| 194 | case 'd': /* Disable */ |
Marek Vasut | 713a8a2 | 2019-04-16 22:28:08 +0200 | [diff] [blame] | 195 | do_bridge_reset(0, mask); |
Ley Foon Tan | 4cc6b58 | 2018-05-24 00:17:23 +0800 | [diff] [blame] | 196 | break; |
| 197 | default: |
| 198 | return CMD_RET_USAGE; |
| 199 | } |
| 200 | |
| 201 | return 0; |
| 202 | } |
| 203 | |
Marek Vasut | 713a8a2 | 2019-04-16 22:28:08 +0200 | [diff] [blame] | 204 | U_BOOT_CMD(bridge, 3, 1, do_bridge, |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 205 | "SoCFPGA HPS FPGA bridge control", |
Marek Vasut | 713a8a2 | 2019-04-16 22:28:08 +0200 | [diff] [blame] | 206 | "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" |
| 207 | "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" |
Ley Foon Tan | f9c7f79 | 2018-05-24 00:17:30 +0800 | [diff] [blame] | 208 | "" |
Ley Foon Tan | 4cc6b58 | 2018-05-24 00:17:23 +0800 | [diff] [blame] | 209 | ); |
| 210 | |
| 211 | #endif |
Ley Foon Tan | fed4c95 | 2019-11-08 10:38:19 +0800 | [diff] [blame] | 212 | |
| 213 | static int socfpga_get_base_addr(const char *compat, phys_addr_t *base) |
| 214 | { |
| 215 | const void *blob = gd->fdt_blob; |
| 216 | struct fdt_resource r; |
| 217 | int node; |
| 218 | int ret; |
| 219 | |
| 220 | node = fdt_node_offset_by_compatible(blob, -1, compat); |
| 221 | if (node < 0) |
| 222 | return node; |
| 223 | |
| 224 | if (!fdtdec_get_is_enabled(blob, node)) |
| 225 | return -ENODEV; |
| 226 | |
| 227 | ret = fdt_get_resource(blob, node, "reg", 0, &r); |
| 228 | if (ret) |
| 229 | return ret; |
| 230 | |
| 231 | *base = (phys_addr_t)r.start; |
| 232 | |
| 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | void socfpga_get_managers_addr(void) |
| 237 | { |
| 238 | int ret; |
| 239 | |
| 240 | ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base); |
| 241 | if (ret) |
| 242 | hang(); |
Ley Foon Tan | 3d3a860 | 2019-11-08 10:38:20 +0800 | [diff] [blame] | 243 | |
| 244 | ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base); |
| 245 | if (ret) |
| 246 | hang(); |
Ley Foon Tan | 2669591 | 2019-11-08 10:38:21 +0800 | [diff] [blame] | 247 | |
Ley Foon Tan | ef5458f | 2019-11-27 15:55:22 +0800 | [diff] [blame] | 248 | #ifdef CONFIG_TARGET_SOCFPGA_AGILEX |
| 249 | ret = socfpga_get_base_addr("intel,agilex-clkmgr", |
| 250 | &socfpga_clkmgr_base); |
| 251 | #else |
Ley Foon Tan | 2669591 | 2019-11-08 10:38:21 +0800 | [diff] [blame] | 252 | ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); |
Ley Foon Tan | ef5458f | 2019-11-27 15:55:22 +0800 | [diff] [blame] | 253 | #endif |
Ley Foon Tan | 2669591 | 2019-11-08 10:38:21 +0800 | [diff] [blame] | 254 | if (ret) |
| 255 | hang(); |
Ley Foon Tan | fed4c95 | 2019-11-08 10:38:19 +0800 | [diff] [blame] | 256 | } |
| 257 | |
| 258 | phys_addr_t socfpga_get_rstmgr_addr(void) |
| 259 | { |
| 260 | return socfpga_rstmgr_base; |
| 261 | } |
Ley Foon Tan | 3d3a860 | 2019-11-08 10:38:20 +0800 | [diff] [blame] | 262 | |
| 263 | phys_addr_t socfpga_get_sysmgr_addr(void) |
| 264 | { |
| 265 | return socfpga_sysmgr_base; |
| 266 | } |
Ley Foon Tan | 2669591 | 2019-11-08 10:38:21 +0800 | [diff] [blame] | 267 | |
| 268 | phys_addr_t socfpga_get_clkmgr_addr(void) |
| 269 | { |
| 270 | return socfpga_clkmgr_base; |
| 271 | } |