| commit | 6fa091d7fbeac3ebd602aa197e581d072d91e7eb | [log] [tgz] |
|---|---|---|
| author | Ley Foon Tan <ley.foon.tan@intel.com> | Fri May 18 22:05:25 2018 +0800 |
| committer | Marek Vasut <marex@denx.de> | Fri May 18 10:30:48 2018 +0200 |
| tree | 0038d41b489c1f31ece1464f6dad29b0aeafa77c | |
| parent | 7cdb9122564c266fdcc3bcb744fd6e987c80be2f [diff] |
arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch conditional build in order this file can by shared across other SOCFPGAs. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>