Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | #include <common.h> |
| 19 | #include <asm/io.h> |
| 20 | #include <asm/arch/reset_manager.h> |
| 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
| 24 | static const struct socfpga_reset_manager *reset_manager_base = |
| 25 | (void *)SOCFPGA_RSTMGR_ADDRESS; |
| 26 | |
| 27 | /* |
| 28 | * Write the reset manager register to cause reset |
| 29 | */ |
| 30 | void reset_cpu(ulong addr) |
| 31 | { |
| 32 | /* request a warm reset */ |
| 33 | writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); |
| 34 | /* |
| 35 | * infinite loop here as watchdog will trigger and reset |
| 36 | * the processor |
| 37 | */ |
| 38 | while (1) |
| 39 | ; |
| 40 | } |
| 41 | |
| 42 | /* |
| 43 | * Release peripherals from reset based on handoff |
| 44 | */ |
| 45 | void reset_deassert_peripherals_handoff(void) |
| 46 | { |
| 47 | writel(0, &reset_manager_base->per_mod_reset); |
| 48 | } |
| 49 | |
| 50 | int dram_init(void) |
| 51 | { |
| 52 | gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); |
| 53 | return 0; |
| 54 | } |