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Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Choub1ed6862015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glass605931c2018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
Sean Anderson63c318f2022-04-22 16:11:37 -040019 default MISC
Simon Glass605931c2018-11-18 08:14:27 -070020 help
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
24 access the device.
25
26config TPL_MISC
27 bool "Enable Driver Model for Misc drivers in TPL"
28 depends on TPL_DM
Sean Anderson63c318f2022-04-22 16:11:37 -040029 default MISC
30 help
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
34 access the device.
35
36config VPL_MISC
37 bool "Enable Driver Model for Misc drivers in VPL"
38 depends on VPL_DM
39 default MISC
Simon Glass605931c2018-11-18 08:14:27 -070040 help
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
44 access the device.
45
Sean Anderson77c66292022-05-05 13:11:39 -040046config NVMEM
47 bool "NVMEM support"
48 help
49 This adds support for a common interface to different types of
50 non-volatile memory. Consumers can use nvmem-cells properties to look
51 up hardware configuration data such as MAC addresses and calibration
52 settings.
53
54config SPL_NVMEM
55 bool "NVMEM support in SPL"
56 help
57 This adds support for a common interface to different types of
58 non-volatile memory. Consumers can use nvmem-cells properties to look
59 up hardware configuration data such as MAC addresses and calibration
60 settings.
61
Thomas Chou36b9c9a2015-10-14 08:43:31 +080062config ALTERA_SYSID
63 bool "Altera Sysid support"
64 depends on MISC
65 help
66 Select this to enable a sysid for Altera devices. Please find
67 details on the "Embedded Peripherals IP User Guide" of Altera.
68
Marek Behúnef2b6b12017-06-09 19:28:44 +020069config ATSHA204A
70 bool "Support for Atmel ATSHA204A module"
Pali Rohár2e269302022-04-12 11:20:44 +020071 select BITREVERSE
Marek Behúnef2b6b12017-06-09 19:28:44 +020072 depends on MISC
73 help
74 Enable support for I2C connected Atmel's ATSHA204A
75 CryptoAuthentication module found for example on the Turris Omnia
76 board.
77
Tim Harveyb8204602022-03-07 16:24:04 -080078config GATEWORKS_SC
79 bool "Gateworks System Controller Support"
80 depends on MISC
81 help
82 Enable access for the Gateworks System Controller used on Gateworks
83 boards to provide a boot watchdog, power control, temperature monitor,
84 voltage ADCs, and EEPROM.
85
Philipp Tomsichfcc1d632017-05-05 19:21:38 +020086config ROCKCHIP_EFUSE
87 bool "Rockchip e-fuse support"
88 depends on MISC
89 help
90 Enable (read-only) access for the e-fuse block found in Rockchip
91 SoCs: accesses can either be made using byte addressing and a length
92 or through child-nodes that are generated based on the e-fuse map
93 retrieved from the DTS.
94
Finley Xiao20d52a02019-09-25 17:57:49 +020095config ROCKCHIP_OTP
96 bool "Rockchip OTP Support"
97 depends on MISC
98 help
99 Enable (read-only) access for the one-time-programmable memory block
100 found in Rockchip SoCs: accesses can either be made using byte
101 addressing and a length or through child-nodes that are generated
102 based on the e-fuse map retrieved from the DTS.
103
Jonas Karlmana937c3d2023-08-21 22:30:28 +0000104config ROCKCHIP_IODOMAIN
105 bool "Rockchip IO-domain driver support"
106 depends on DM_REGULATOR && ARCH_ROCKCHIP
Chen-Yu Tsaic1b7c852025-04-29 21:28:40 +0800107 default y if ROCKCHIP_PX30
108 default y if ROCKCHIP_RK3308
109 default y if ROCKCHIP_RK3328
110 default y if ROCKCHIP_RK3399
111 default y if ROCKCHIP_RK3568
Jonas Karlmana937c3d2023-08-21 22:30:28 +0000112 help
113 Enable support for IO-domains in Rockchip SoCs. It is necessary
114 for the IO-domain setting of the SoC to match the voltage supplied
115 by the regulators.
116
Pragnesh Patel6e9661f2020-05-29 11:33:21 +0530117config SIFIVE_OTP
118 bool "SiFive eMemory OTP driver"
119 depends on MISC
120 help
121 Enable support for reading and writing the eMemory OTP on the
122 SiFive SoCs.
123
Tom Rini035e8722022-11-19 18:45:33 -0500124config SMSC_LPC47M
125 bool "LPC47M SMSC driver"
126
127config SMSC_SIO1007
128 bool "SIO1007 SMSC driver"
129
Liviu Dudau688db7f2018-09-28 13:43:31 +0100130config VEXPRESS_CONFIG
131 bool "Enable support for Arm Versatile Express config bus"
132 depends on MISC
133 help
134 If you say Y here, you will get support for accessing the
135 configuration bus on the Arm Versatile Express boards via
136 a sysreg driver.
137
Simon Glass036ca142023-09-10 13:13:02 -0600138config CBMEM_CONSOLE
139 bool "Write console output to coreboot cbmem"
140 depends on X86
141 help
142 Enables console output to the cbmem console, which is a memory
143 region set up by coreboot to hold a record of all console output.
144 Enable this only if booting from coreboot.
145
Simon Glass5b79bb22015-02-13 12:20:47 -0700146config CMD_CROS_EC
147 bool "Enable crosec command"
148 depends on CROS_EC
149 help
150 Enable command-line access to the Chrome OS EC (Embedded
151 Controller). This provides the 'crosec' command which has
152 a number of sub-commands for performing EC tasks such as
153 updating its flash, accessing a small saved context area
154 and talking to the I2C bus behind the EC (if there is one).
155
156config CROS_EC
157 bool "Enable Chrome OS EC"
158 help
159 Enable access to the Chrome OS EC. This is a separate
160 microcontroller typically available on a SPI bus on Chromebooks. It
161 provides access to the keyboard, some internal storage and may
162 control access to the battery and main PMIC depending on the
163 device. You can use the 'crosec' command to access it.
164
Simon Glass605931c2018-11-18 08:14:27 -0700165config SPL_CROS_EC
166 bool "Enable Chrome OS EC in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400167 depends on SPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700168 help
169 Enable access to the Chrome OS EC in SPL. This is a separate
170 microcontroller typically available on a SPI bus on Chromebooks. It
171 provides access to the keyboard, some internal storage and may
172 control access to the battery and main PMIC depending on the
173 device. You can use the 'crosec' command to access it.
174
175config TPL_CROS_EC
176 bool "Enable Chrome OS EC in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400177 depends on TPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700178 help
179 Enable access to the Chrome OS EC in TPL. This is a separate
180 microcontroller typically available on a SPI bus on Chromebooks. It
181 provides access to the keyboard, some internal storage and may
182 control access to the battery and main PMIC depending on the
183 device. You can use the 'crosec' command to access it.
184
Simon Glasse7ca7da2022-04-30 00:56:53 -0600185config VPL_CROS_EC
186 bool "Enable Chrome OS EC in VPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400187 depends on VPL_MISC
Simon Glasse7ca7da2022-04-30 00:56:53 -0600188 help
189 Enable access to the Chrome OS EC in VPL. This is a separate
190 microcontroller typically available on a SPI bus on Chromebooks. It
191 provides access to the keyboard, some internal storage and may
192 control access to the battery and main PMIC depending on the
193 device. You can use the 'crosec' command to access it.
194
Simon Glass5b79bb22015-02-13 12:20:47 -0700195config CROS_EC_I2C
196 bool "Enable Chrome OS EC I2C driver"
197 depends on CROS_EC
198 help
199 Enable I2C access to the Chrome OS EC. This is used on older
200 ARM Chromebooks such as snow and spring before the standard bus
201 changed to SPI. The EC will accept commands across the I2C using
202 a special message protocol, and provide responses.
203
204config CROS_EC_LPC
205 bool "Enable Chrome OS EC LPC driver"
206 depends on CROS_EC
207 help
208 Enable I2C access to the Chrome OS EC. This is used on x86
209 Chromebooks such as link and falco. The keyboard is provided
210 through a legacy port interface, so on x86 machines the main
211 function of the EC is power and thermal management.
212
Simon Glass605931c2018-11-18 08:14:27 -0700213config SPL_CROS_EC_LPC
214 bool "Enable Chrome OS EC LPC driver in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400215 depends on CROS_EC && SPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700216 help
217 Enable I2C access to the Chrome OS EC. This is used on x86
218 Chromebooks such as link and falco. The keyboard is provided
219 through a legacy port interface, so on x86 machines the main
220 function of the EC is power and thermal management.
221
222config TPL_CROS_EC_LPC
223 bool "Enable Chrome OS EC LPC driver in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400224 depends on CROS_EC && TPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700225 help
226 Enable I2C access to the Chrome OS EC. This is used on x86
227 Chromebooks such as link and falco. The keyboard is provided
228 through a legacy port interface, so on x86 machines the main
229 function of the EC is power and thermal management.
230
Simon Glasse7ca7da2022-04-30 00:56:53 -0600231config VPL_CROS_EC_LPC
232 bool "Enable Chrome OS EC LPC driver in VPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400233 depends on CROS_EC && VPL_MISC
Simon Glasse7ca7da2022-04-30 00:56:53 -0600234 help
235 Enable I2C access to the Chrome OS EC. This is used on x86
236 Chromebooks such as link and falco. The keyboard is provided
237 through a legacy port interface, so on x86 machines the main
238 function of the EC is power and thermal management.
239
Simon Glassc6e06692015-03-26 09:29:40 -0600240config CROS_EC_SANDBOX
241 bool "Enable Chrome OS EC sandbox driver"
242 depends on CROS_EC && SANDBOX
243 help
244 Enable a sandbox emulation of the Chrome OS EC. This supports
245 keyboard (use the -l flag to enable the LCD), verified boot context,
246 EC flash read/write/erase support and a few other things. It is
247 enough to perform a Chrome OS verified boot on sandbox.
248
Simon Glass605931c2018-11-18 08:14:27 -0700249config SPL_CROS_EC_SANDBOX
250 bool "Enable Chrome OS EC sandbox driver in SPL"
251 depends on SPL_CROS_EC && SANDBOX
252 help
253 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
254 keyboard (use the -l flag to enable the LCD), verified boot context,
255 EC flash read/write/erase support and a few other things. It is
256 enough to perform a Chrome OS verified boot on sandbox.
257
258config TPL_CROS_EC_SANDBOX
259 bool "Enable Chrome OS EC sandbox driver in TPL"
260 depends on TPL_CROS_EC && SANDBOX
261 help
262 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
263 keyboard (use the -l flag to enable the LCD), verified boot context,
264 EC flash read/write/erase support and a few other things. It is
265 enough to perform a Chrome OS verified boot on sandbox.
266
Simon Glasse7ca7da2022-04-30 00:56:53 -0600267config VPL_CROS_EC_SANDBOX
268 bool "Enable Chrome OS EC sandbox driver in VPL"
269 depends on VPL_CROS_EC && SANDBOX
270 help
271 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
272 keyboard (use the -l flag to enable the LCD), verified boot context,
273 EC flash read/write/erase support and a few other things. It is
274 enough to perform a Chrome OS verified boot on sandbox.
275
Simon Glass5b79bb22015-02-13 12:20:47 -0700276config CROS_EC_SPI
277 bool "Enable Chrome OS EC SPI driver"
278 depends on CROS_EC
279 help
280 Enable SPI access to the Chrome OS EC. This is used on newer
281 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
282 provides a faster and more robust interface than I2C but the bugs
283 are less interesting.
284
Simon Glass58ed3222017-05-17 03:25:02 -0600285config DS4510
286 bool "Enable support for DS4510 CPU supervisor"
287 help
288 Enable support for the Maxim DS4510 CPU supervisor. It has an
289 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
290 and a configurable timer for the supervisor function. The device is
291 connected over I2C.
292
Tom Rini66fa77a2022-11-19 18:45:11 -0500293config FSL_IIM
294 bool "Enable FSL IC Identification Module (IIM) driver"
295 depends on ARCH_MX31 || ARCH_MX5
296
Peng Fanfb6166a2015-08-26 15:41:33 +0800297config FSL_SEC_MON
gaurav rana9aaea442015-02-27 09:44:22 +0530298 bool "Enable FSL SEC_MON Driver"
299 help
300 Freescale Security Monitor block is responsible for monitoring
301 system states.
302 Security Monitor can be transitioned on any security failures,
303 like software violations or hardware security violations.
Stefan Roese04b22752015-03-12 11:22:46 +0100304
Tom Rini0b58c2e2022-06-16 14:04:39 -0400305choice
306 prompt "Security monitor interaction endianess"
307 depends on FSL_SEC_MON
308 default SYS_FSL_SEC_MON_BE if PPC
309 default SYS_FSL_SEC_MON_LE
310
311config SYS_FSL_SEC_MON_LE
312 bool "Security monitor interactions are little endian"
313
314config SYS_FSL_SEC_MON_BE
315 bool "Security monitor interactions are big endian"
316
317endchoice
318
Simon Glassff418d92019-12-06 21:41:58 -0700319config IRQ
Wasim Khan55c9b9c2021-03-08 16:48:13 +0100320 bool "Interrupt controller"
Simon Glassff418d92019-12-06 21:41:58 -0700321 help
Wasim Khan55c9b9c2021-03-08 16:48:13 +0100322 This enables support for interrupt controllers, including ITSS.
Simon Glassff418d92019-12-06 21:41:58 -0700323 Some devices have extra features, such as Apollo Lake. The
324 device has its own uclass since there are several operations
325 involved.
326
Paul Burton738d8a82018-12-16 19:25:19 -0300327config JZ4780_EFUSE
328 bool "Ingenic JZ4780 eFUSE support"
329 depends on ARCH_JZ47XX
330 help
331 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
332
Sean Anderson6b39d352022-04-22 14:34:18 -0400333config LS2_SFP
334 bool "Layerscape Security Fuse Processor"
335 depends on FSL_LSCH2 || ARCH_LS1021A
336 depends on MISC
337 imply DM_REGULATOR
338 help
339 This adds support for the Security Fuse Processor found on Layerscape
340 SoCs. It contains various fuses related to secure boot, including the
341 Super Root Key hash, One-Time-Programmable Master Key, Debug
342 Challenge/Response values, and others. Fuses are numbered according
343 to their four-byte offset from the start of the bank.
344
345 If you don't need to read/program fuses, say 'n'.
346
Peng Fane1872252015-08-27 14:49:05 +0800347config MXC_OCOTP
348 bool "Enable MXC OCOTP Driver"
Peng Fanc45a81a2019-07-22 01:24:55 +0000349 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswilerf2213142019-03-25 17:24:57 +0100350 default y
Peng Fane1872252015-08-27 14:49:05 +0800351 help
352 If you say Y here, you will get support for the One Time
353 Programmable memory pages that are stored on the some
354 Freescale i.MX processors.
355
Tom Rini5a0f9d82022-11-19 18:45:28 -0500356config MXS_OCOTP
357 bool "Enable MXS OCOTP Driver"
358 depends on ARCH_MX23 || ARCH_MX28
359 help
360 If you say Y here, you will get support for the One Time
361 Programmable memory pages that are stored on the
362 Freescale i.MXS family of processors.
363
Jim Liucce4eed2022-06-24 16:24:37 +0800364config NPCM_HOST
365 bool "Enable support espi or LPC for Host"
366 depends on REGMAP && SYSCON
367 help
368 Enable NPCM BMC espi or LPC support for Host reading and writing.
369
Michael Scott92676142021-09-25 19:49:28 +0300370config SPL_MXC_OCOTP
371 bool "Enable MXC OCOTP driver in SPL"
Jean-Marie Lemetayerf17d43d2023-02-13 14:12:25 +0100372 depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
Michael Scott92676142021-09-25 19:49:28 +0300373 default y
374 help
375 If you say Y here, you will get support for the One Time
376 Programmable memory pages, that are stored on some
377 Freescale i.MX processors, in SPL.
378
Jim Liufab2eff2022-06-07 16:33:54 +0800379config NPCM_OTP
380 bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
381 depends on (ARM && ARCH_NPCM)
Jim Liufab2eff2022-06-07 16:33:54 +0800382 help
383 Support NPCM BMC OTP memory (fuse).
384 To compile this driver as a module, choose M here: the module
385 will be called npcm_otp.
386
Peng Fand5c31832023-06-15 18:09:05 +0800387config IMX_ELE
388 bool "Enable i.MX EdgeLock Enclave MU driver and API"
Ye Lic408ed32022-07-26 16:40:49 +0800389 depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
390 help
391 If you say Y here to enable Message Unit driver to work with
392 Sentinel core on some NXP i.MX processors.
393
Stefan Roese4a269f22016-07-19 07:45:46 +0200394config NUVOTON_NCT6102D
395 bool "Enable Nuvoton NCT6102D Super I/O driver"
396 help
397 If you say Y here, you will get support for the Nuvoton
398 NCT6102D Super I/O driver. This can be used to enable or
399 disable the legacy UART, the watchdog or other devices
400 in the Nuvoton Super IO chips on X86 platforms.
401
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700402config P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200403 bool "Intel Primary to Sideband Bridge"
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700404 depends on X86 || SANDBOX
405 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200406 This enables support for the Intel Primary to Sideband Bridge,
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700407 abbreviated to P2SB. The P2SB is used to access various peripherals
408 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
409 space. The space is segmented into different channels and peripherals
410 are accessed by device-specific means within those channels. Devices
411 should be added in the device tree as subnodes of the P2SB. A
412 Peripheral Channel Register? (PCR) API is provided to access those
413 devices - see pcr_readl(), etc.
414
415config SPL_P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200416 bool "Intel Primary to Sideband Bridge in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400417 depends on SPL_MISC && (X86 || SANDBOX)
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700418 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200419 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700420 through memory-mapped I/O in a large chunk of PCI space. The space is
421 segmented into different channels and peripherals are accessed by
422 device-specific means within those channels. Devices should be added
423 in the device tree as subnodes of the p2sb.
424
425config TPL_P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200426 bool "Intel Primary to Sideband Bridge in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400427 depends on TPL_MISC && (X86 || SANDBOX)
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700428 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200429 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700430 through memory-mapped I/O in a large chunk of PCI space. The space is
431 segmented into different channels and peripherals are accessed by
432 device-specific means within those channels. Devices should be added
433 in the device tree as subnodes of the p2sb.
434
Simon Glassc9795172016-01-21 19:43:31 -0700435config PWRSEQ
436 bool "Enable power-sequencing drivers"
437 depends on DM
438 help
439 Power-sequencing drivers provide support for controlling power for
440 devices. They are typically referenced by a phandle from another
441 device. When the device is started up, its power sequence can be
442 initiated.
443
444config SPL_PWRSEQ
445 bool "Enable power-sequencing drivers for SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400446 depends on SPL_MISC && PWRSEQ
Simon Glassc9795172016-01-21 19:43:31 -0700447 help
448 Power-sequencing drivers provide support for controlling power for
449 devices. They are typically referenced by a phandle from another
450 device. When the device is started up, its power sequence can be
451 initiated.
452
Stefan Roese04b22752015-03-12 11:22:46 +0100453config PCA9551_LED
454 bool "Enable PCA9551 LED driver"
455 help
456 Enable driver for PCA9551 LED controller. This controller
457 is connected via I2C. So I2C needs to be enabled.
458
459config PCA9551_I2C_ADDR
460 hex "I2C address of PCA9551 LED controller"
461 depends on PCA9551_LED
462 default 0x60
463 help
464 The I2C address of the PCA9551 LED controller.
Simon Glass14000862015-06-23 15:39:13 -0600465
Patrick Delaunay0c4656b2018-05-17 15:24:06 +0200466config STM32MP_FUSE
467 bool "Enable STM32MP fuse wrapper providing the fuse API"
468 depends on ARCH_STM32MP && MISC
469 default y if CMD_FUSE
470 help
471 If you say Y here, you will get support for the fuse API (OTP)
472 for STM32MP architecture.
473 This API is needed for CMD_FUSE.
474
Harsha Vardhan V Mcc7e7fd2025-03-19 14:17:13 +0530475config K3_FUSE
476 bool "Enable TI K3 fuse wrapper providing the fuse API"
477 depends on MISC && CMD_FUSE && CMD_FUSE_WRITEBUFF
478 help
479 If you say Y here, you will get support for the fuse API (OTP)
480 for TI K3 architecture.
481
Christophe Kerello275f7062017-09-13 18:00:08 +0200482config STM32_RCC
483 bool "Enable RCC driver for the STM32 SoC's family"
Trevor Woerner2bcc1ed2020-05-06 08:02:42 -0400484 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
Christophe Kerello275f7062017-09-13 18:00:08 +0200485 help
486 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
487 block) is responsible of the management of the clock and reset
488 generation.
489 This driver is similar to an MFD driver in the Linux kernel.
490
Stephen Warrenf6417002016-09-13 10:45:57 -0600491config TEGRA_CAR
492 bool "Enable support for the Tegra CAR driver"
493 depends on TEGRA_NO_BPMP
494 help
495 The Tegra CAR (Clock and Reset Controller) is a HW module that
496 controls almost all clocks and resets in a Tegra SoC.
497
Stephen Warrena2148922016-08-08 09:41:34 -0600498config TEGRA186_BPMP
499 bool "Enable support for the Tegra186 BPMP driver"
500 depends on TEGRA186
501 help
502 The Tegra BPMP (Boot and Power Management Processor) is a separate
503 auxiliary CPU embedded into Tegra to perform power management work,
504 and controls related features such as clocks, resets, power domains,
505 PMIC I2C bus, etc. This driver provides the core low-level
506 communication path by which feature-specific drivers (such as clock)
507 can make requests to the BPMP. This driver is similar to an MFD
508 driver in the Linux kernel.
509
Simon Glass4bf89722020-12-23 08:11:18 -0700510config TEST_DRV
511 bool "Enable support for test drivers"
512 default y if SANDBOX
513 help
514 This enables drivers and uclasses that provides a way of testing the
515 operations of memory allocation and driver/uclass methods in driver
516 model. This should only be enabled for testing as it is not useful for
517 anything else.
518
Marek Behúnea51ee52024-04-04 09:51:03 +0200519config TURRIS_OMNIA_MCU
520 bool "Enable Turris Omnia MCU driver"
521 depends on DM_I2C
522 depends on DM_GPIO
Marek Behún4f552fe2024-04-04 09:51:06 +0200523 depends on DM_RNG
Marek Behúnea51ee52024-04-04 09:51:03 +0200524 depends on SYSRESET
525 default y if TARGET_TURRIS_OMNIA
526 help
527 This enables support for Turris Omnia MCU connected GPIOs and
528 board power off.
529
Marek Vasut16637b42022-04-10 06:27:14 +0200530config USB_HUB_USB251XB
531 tristate "USB251XB Hub Controller Configuration Driver"
532 depends on I2C
533 help
534 This option enables support for configuration via SMBus of the
535 Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
536 parameters may be set in devicetree or platform data.
537 Say Y or M here if you need to configure such a device via SMBus.
538
Adam Fordc8cdce72018-08-06 14:26:50 -0500539config TWL4030_LED
540 bool "Enable TWL4030 LED controller"
541 help
542 Enable this to add support for the TWL4030 LED controller.
543
Stefan Roeseba019ed2016-01-19 14:05:10 +0100544config WINBOND_W83627
545 bool "Enable Winbond Super I/O driver"
546 help
547 If you say Y here, you will get support for the Winbond
548 W83627 Super I/O driver. This can be used to enable the
549 legacy UART or other devices in the Winbond Super IO chips
550 on X86 platforms.
551
Miao Yan4fcd7f22016-05-22 19:37:14 -0700552config QFW
553 bool
554 help
Asherah Connor4ffa95d2021-03-19 18:21:40 +1100555 Hidden option to enable QEMU fw_cfg interface and uclass. This will
556 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
557
Heinrich Schuchardt223605f2023-12-19 16:04:00 +0100558config QFW_ACPI
559 bool
560 default y
561 depends on QFW && GENERATE_ACPI_TABLE && !SANDBOX
562 help
563 Hidden option to read ACPI tables from QEMU.
564
Asherah Connor4ffa95d2021-03-19 18:21:40 +1100565config QFW_PIO
566 bool
567 depends on QFW
568 help
569 Hidden option to enable PIO QEMU fw_cfg interface. This will be
570 selected by the appropriate QEMU board.
Miao Yan4fcd7f22016-05-22 19:37:14 -0700571
Asherah Connorf0c0e542021-03-19 18:21:42 +1100572config QFW_MMIO
573 bool
574 depends on QFW
575 help
576 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
577 selected by the appropriate QEMU board.
578
Heinrich Schuchardt08d931a2023-12-23 02:03:34 +0100579config QFW_SMBIOS
580 bool
581 default y
Raymond Maoc83c3762024-12-06 14:54:27 -0800582 depends on QFW && SMBIOS && !SANDBOX && !SYSINFO_SMBIOS
Heinrich Schuchardte191ead2025-04-07 08:44:24 +0200583 select BLOBLIST
Heinrich Schuchardt08d931a2023-12-23 02:03:34 +0100584 help
585 Hidden option to read SMBIOS tables from QEMU.
586
mario.six@gdsys.cc7559ac42016-06-22 15:14:16 +0200587config I2C_EEPROM
588 bool "Enable driver for generic I2C-attached EEPROMs"
589 depends on MISC
590 help
591 Enable a generic driver for EEPROMs attached via I2C.
Adam Ford5664f832017-08-13 09:00:28 -0500592
Wenyou Yangf791d562017-09-06 13:08:14 +0800593
594config SPL_I2C_EEPROM
595 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400596 depends on SPL_MISC
Wenyou Yangf791d562017-09-06 13:08:14 +0800597 help
598 This option is an SPL-variant of the I2C_EEPROM option.
599 See the help of I2C_EEPROM for details.
600
Adam Ford5664f832017-08-13 09:00:28 -0500601config SYS_I2C_EEPROM_ADDR
602 hex "Chip address of the EEPROM device"
Tom Rinifaed5672021-08-17 17:59:45 -0400603 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
Tom Rinif18679c2023-08-02 11:09:43 -0400604 default 0x0
Adam Ford5664f832017-08-13 09:00:28 -0500605
Tom Rinifaed5672021-08-17 17:59:45 -0400606if I2C_EEPROM
Adam Ford5664f832017-08-13 09:00:28 -0500607
608config SYS_I2C_EEPROM_ADDR_OVERFLOW
609 hex "EEPROM Address Overflow"
Tom Rinif0599552021-12-11 14:55:47 -0500610 default 0x0
Adam Ford5664f832017-08-13 09:00:28 -0500611 help
612 EEPROM chips that implement "address overflow" are ones
613 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
614 address and the extra bits end up in the "chip address" bit
615 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
616 byte chips.
617
618endif
619
Mario Six7f504a02018-04-27 14:53:33 +0200620config GDSYS_RXAUI_CTRL
621 bool "Enable gdsys RXAUI control driver"
622 depends on MISC
623 help
624 Support gdsys FPGA's RXAUI control.
Mario Six0cafb652018-07-31 14:24:15 +0200625
626config GDSYS_IOEP
627 bool "Enable gdsys IOEP driver"
628 depends on MISC
629 help
630 Support gdsys FPGA's IO endpoint driver.
Mario Six7fdcf282018-08-06 10:23:46 +0200631
632config MPC83XX_SERDES
633 bool "Enable MPC83xx serdes driver"
634 depends on MISC
635 help
636 Support for serdes found on MPC83xx SoCs.
637
Tien Fong Chee5ca878b2018-07-06 16:28:03 +0800638config FS_LOADER
639 bool "Enable loader driver for file system"
640 help
641 This is file system generic loader which can be used to load
642 the file image from the storage into target such as memory.
643
644 The consumer driver would then use this loader to program whatever,
645 ie. the FPGA device.
646
Keerthyfe8f6092022-01-27 13:16:53 +0100647config SPL_FS_LOADER
Alexander Gendin1c1a8842023-11-20 20:21:51 +0000648 bool "Enable loader driver for file system in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400649 depends on SPL
Keerthyfe8f6092022-01-27 13:16:53 +0100650 help
651 This is file system generic loader which can be used to load
652 the file image from the storage into target such as memory.
653
654 The consumer driver would then use this loader to program whatever,
655 ie. the FPGA device.
656
Mario Six8862f452018-10-04 09:00:54 +0200657config GDSYS_SOC
658 bool "Enable gdsys SOC driver"
659 depends on MISC
660 help
661 Support for gdsys IHS SOC, a simple bus associated with each gdsys
662 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
663 register maps are contained within the FPGA's register map.
664
Mario Six1a9d43f2018-10-04 09:00:55 +0200665config IHS_FPGA
666 bool "Enable IHS FPGA driver"
667 depends on MISC
668 help
669 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
670 gdsys devices, which supply the majority of the functionality offered
671 by the devices. This driver supports both CON and CPU variants of the
672 devices, depending on the device tree entry.
Tero Kristof81f4cd2020-02-14 11:18:15 +0200673config ESM_K3
674 bool "Enable K3 ESM driver"
675 depends on ARCH_K3
676 help
677 Support ESM (Error Signaling Module) on TI K3 SoCs.
Mario Six1a9d43f2018-10-04 09:00:55 +0200678
Eugen Hristev3bd56102019-10-09 09:23:39 +0000679config MICROCHIP_FLEXCOM
680 bool "Enable Microchip Flexcom driver"
681 depends on MISC
682 help
683 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
684 an I2C controller and an USART.
685 Only one function can be used at a time and is chosen at boot time
686 according to the device tree.
687
Tero Kristo887dde52019-10-24 15:00:46 +0530688config K3_AVS0
689 depends on ARCH_K3 && SPL_DM_REGULATOR
690 bool "AVS class 0 support for K3 devices"
691 help
692 K3 devices have the optimized voltage values for the main voltage
693 domains stored in efuse within the VTM IP. This driver reads the
694 optimized voltage from the efuse, so that it can be programmed
695 to the PMIC on board.
696
Tero Kristo1444e112020-02-14 11:18:16 +0200697config ESM_PMIC
698 bool "Enable PMIC ESM driver"
699 depends on DM_PMIC
700 help
701 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
702 typically to reboot the board in error condition.
703
Tom Rini05b419e2021-12-11 14:55:49 -0500704config FSL_IFC
705 bool
706
Michael Walle2184cc62022-02-25 18:06:24 +0530707config SL28CPLD
708 bool "Enable Kontron sl28cpld multi-function driver"
709 depends on DM_I2C
710 help
711 Support for the Kontron sl28cpld management controller. This is
712 the base driver which provides common access methods for the
713 sub-drivers.
714
Wan Yee Laue249d542024-02-05 11:47:16 +0800715config SPL_SOCFPGA_DT_REG
716 bool "Enable register setting from device tree in SPL"
717 depends on SPL
718 help
719 Enable register setting from device tree. This also
720 provides user a clean interface and all register settings are
721 centralized in one place, device tree.
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900722endmenu