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Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Choub1ed6862015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glass605931c2018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
Sean Anderson63c318f2022-04-22 16:11:37 -040019 default MISC
Simon Glass605931c2018-11-18 08:14:27 -070020 help
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
24 access the device.
25
26config TPL_MISC
27 bool "Enable Driver Model for Misc drivers in TPL"
28 depends on TPL_DM
Sean Anderson63c318f2022-04-22 16:11:37 -040029 default MISC
30 help
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
34 access the device.
35
36config VPL_MISC
37 bool "Enable Driver Model for Misc drivers in VPL"
38 depends on VPL_DM
39 default MISC
Simon Glass605931c2018-11-18 08:14:27 -070040 help
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
44 access the device.
45
Sean Anderson77c66292022-05-05 13:11:39 -040046config NVMEM
47 bool "NVMEM support"
48 help
49 This adds support for a common interface to different types of
50 non-volatile memory. Consumers can use nvmem-cells properties to look
51 up hardware configuration data such as MAC addresses and calibration
52 settings.
53
54config SPL_NVMEM
55 bool "NVMEM support in SPL"
56 help
57 This adds support for a common interface to different types of
58 non-volatile memory. Consumers can use nvmem-cells properties to look
59 up hardware configuration data such as MAC addresses and calibration
60 settings.
61
Thomas Chou36b9c9a2015-10-14 08:43:31 +080062config ALTERA_SYSID
63 bool "Altera Sysid support"
64 depends on MISC
65 help
66 Select this to enable a sysid for Altera devices. Please find
67 details on the "Embedded Peripherals IP User Guide" of Altera.
68
Marek Behúnef2b6b12017-06-09 19:28:44 +020069config ATSHA204A
70 bool "Support for Atmel ATSHA204A module"
Pali Rohár2e269302022-04-12 11:20:44 +020071 select BITREVERSE
Marek Behúnef2b6b12017-06-09 19:28:44 +020072 depends on MISC
73 help
74 Enable support for I2C connected Atmel's ATSHA204A
75 CryptoAuthentication module found for example on the Turris Omnia
76 board.
77
Tim Harveyb8204602022-03-07 16:24:04 -080078config GATEWORKS_SC
79 bool "Gateworks System Controller Support"
80 depends on MISC
81 help
82 Enable access for the Gateworks System Controller used on Gateworks
83 boards to provide a boot watchdog, power control, temperature monitor,
84 voltage ADCs, and EEPROM.
85
Philipp Tomsichfcc1d632017-05-05 19:21:38 +020086config ROCKCHIP_EFUSE
87 bool "Rockchip e-fuse support"
88 depends on MISC
89 help
90 Enable (read-only) access for the e-fuse block found in Rockchip
91 SoCs: accesses can either be made using byte addressing and a length
92 or through child-nodes that are generated based on the e-fuse map
93 retrieved from the DTS.
94
95 This driver currently supports the RK3399 only, but can easily be
96 extended (by porting the read function from the Linux kernel sources)
97 to support other recent Rockchip devices.
98
Finley Xiao20d52a02019-09-25 17:57:49 +020099config ROCKCHIP_OTP
100 bool "Rockchip OTP Support"
101 depends on MISC
102 help
103 Enable (read-only) access for the one-time-programmable memory block
104 found in Rockchip SoCs: accesses can either be made using byte
105 addressing and a length or through child-nodes that are generated
106 based on the e-fuse map retrieved from the DTS.
107
Pragnesh Patel6e9661f2020-05-29 11:33:21 +0530108config SIFIVE_OTP
109 bool "SiFive eMemory OTP driver"
110 depends on MISC
111 help
112 Enable support for reading and writing the eMemory OTP on the
113 SiFive SoCs.
114
Liviu Dudau688db7f2018-09-28 13:43:31 +0100115config VEXPRESS_CONFIG
116 bool "Enable support for Arm Versatile Express config bus"
117 depends on MISC
118 help
119 If you say Y here, you will get support for accessing the
120 configuration bus on the Arm Versatile Express boards via
121 a sysreg driver.
122
Simon Glass5b79bb22015-02-13 12:20:47 -0700123config CMD_CROS_EC
124 bool "Enable crosec command"
125 depends on CROS_EC
126 help
127 Enable command-line access to the Chrome OS EC (Embedded
128 Controller). This provides the 'crosec' command which has
129 a number of sub-commands for performing EC tasks such as
130 updating its flash, accessing a small saved context area
131 and talking to the I2C bus behind the EC (if there is one).
132
133config CROS_EC
134 bool "Enable Chrome OS EC"
135 help
136 Enable access to the Chrome OS EC. This is a separate
137 microcontroller typically available on a SPI bus on Chromebooks. It
138 provides access to the keyboard, some internal storage and may
139 control access to the battery and main PMIC depending on the
140 device. You can use the 'crosec' command to access it.
141
Simon Glass605931c2018-11-18 08:14:27 -0700142config SPL_CROS_EC
143 bool "Enable Chrome OS EC in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400144 depends on SPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700145 help
146 Enable access to the Chrome OS EC in SPL. This is a separate
147 microcontroller typically available on a SPI bus on Chromebooks. It
148 provides access to the keyboard, some internal storage and may
149 control access to the battery and main PMIC depending on the
150 device. You can use the 'crosec' command to access it.
151
152config TPL_CROS_EC
153 bool "Enable Chrome OS EC in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400154 depends on TPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700155 help
156 Enable access to the Chrome OS EC in TPL. This is a separate
157 microcontroller typically available on a SPI bus on Chromebooks. It
158 provides access to the keyboard, some internal storage and may
159 control access to the battery and main PMIC depending on the
160 device. You can use the 'crosec' command to access it.
161
Simon Glasse7ca7da2022-04-30 00:56:53 -0600162config VPL_CROS_EC
163 bool "Enable Chrome OS EC in VPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400164 depends on VPL_MISC
Simon Glasse7ca7da2022-04-30 00:56:53 -0600165 help
166 Enable access to the Chrome OS EC in VPL. This is a separate
167 microcontroller typically available on a SPI bus on Chromebooks. It
168 provides access to the keyboard, some internal storage and may
169 control access to the battery and main PMIC depending on the
170 device. You can use the 'crosec' command to access it.
171
Simon Glass5b79bb22015-02-13 12:20:47 -0700172config CROS_EC_I2C
173 bool "Enable Chrome OS EC I2C driver"
174 depends on CROS_EC
175 help
176 Enable I2C access to the Chrome OS EC. This is used on older
177 ARM Chromebooks such as snow and spring before the standard bus
178 changed to SPI. The EC will accept commands across the I2C using
179 a special message protocol, and provide responses.
180
181config CROS_EC_LPC
182 bool "Enable Chrome OS EC LPC driver"
183 depends on CROS_EC
184 help
185 Enable I2C access to the Chrome OS EC. This is used on x86
186 Chromebooks such as link and falco. The keyboard is provided
187 through a legacy port interface, so on x86 machines the main
188 function of the EC is power and thermal management.
189
Simon Glass605931c2018-11-18 08:14:27 -0700190config SPL_CROS_EC_LPC
191 bool "Enable Chrome OS EC LPC driver in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400192 depends on CROS_EC && SPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700193 help
194 Enable I2C access to the Chrome OS EC. This is used on x86
195 Chromebooks such as link and falco. The keyboard is provided
196 through a legacy port interface, so on x86 machines the main
197 function of the EC is power and thermal management.
198
199config TPL_CROS_EC_LPC
200 bool "Enable Chrome OS EC LPC driver in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400201 depends on CROS_EC && TPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700202 help
203 Enable I2C access to the Chrome OS EC. This is used on x86
204 Chromebooks such as link and falco. The keyboard is provided
205 through a legacy port interface, so on x86 machines the main
206 function of the EC is power and thermal management.
207
Simon Glasse7ca7da2022-04-30 00:56:53 -0600208config VPL_CROS_EC_LPC
209 bool "Enable Chrome OS EC LPC driver in VPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400210 depends on CROS_EC && VPL_MISC
Simon Glasse7ca7da2022-04-30 00:56:53 -0600211 help
212 Enable I2C access to the Chrome OS EC. This is used on x86
213 Chromebooks such as link and falco. The keyboard is provided
214 through a legacy port interface, so on x86 machines the main
215 function of the EC is power and thermal management.
216
Simon Glassc6e06692015-03-26 09:29:40 -0600217config CROS_EC_SANDBOX
218 bool "Enable Chrome OS EC sandbox driver"
219 depends on CROS_EC && SANDBOX
220 help
221 Enable a sandbox emulation of the Chrome OS EC. This supports
222 keyboard (use the -l flag to enable the LCD), verified boot context,
223 EC flash read/write/erase support and a few other things. It is
224 enough to perform a Chrome OS verified boot on sandbox.
225
Simon Glass605931c2018-11-18 08:14:27 -0700226config SPL_CROS_EC_SANDBOX
227 bool "Enable Chrome OS EC sandbox driver in SPL"
228 depends on SPL_CROS_EC && SANDBOX
229 help
230 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
231 keyboard (use the -l flag to enable the LCD), verified boot context,
232 EC flash read/write/erase support and a few other things. It is
233 enough to perform a Chrome OS verified boot on sandbox.
234
235config TPL_CROS_EC_SANDBOX
236 bool "Enable Chrome OS EC sandbox driver in TPL"
237 depends on TPL_CROS_EC && SANDBOX
238 help
239 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
240 keyboard (use the -l flag to enable the LCD), verified boot context,
241 EC flash read/write/erase support and a few other things. It is
242 enough to perform a Chrome OS verified boot on sandbox.
243
Simon Glasse7ca7da2022-04-30 00:56:53 -0600244config VPL_CROS_EC_SANDBOX
245 bool "Enable Chrome OS EC sandbox driver in VPL"
246 depends on VPL_CROS_EC && SANDBOX
247 help
248 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
249 keyboard (use the -l flag to enable the LCD), verified boot context,
250 EC flash read/write/erase support and a few other things. It is
251 enough to perform a Chrome OS verified boot on sandbox.
252
Simon Glass5b79bb22015-02-13 12:20:47 -0700253config CROS_EC_SPI
254 bool "Enable Chrome OS EC SPI driver"
255 depends on CROS_EC
256 help
257 Enable SPI access to the Chrome OS EC. This is used on newer
258 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
259 provides a faster and more robust interface than I2C but the bugs
260 are less interesting.
261
Simon Glass58ed3222017-05-17 03:25:02 -0600262config DS4510
263 bool "Enable support for DS4510 CPU supervisor"
264 help
265 Enable support for the Maxim DS4510 CPU supervisor. It has an
266 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
267 and a configurable timer for the supervisor function. The device is
268 connected over I2C.
269
Tom Rini66fa77a2022-11-19 18:45:11 -0500270config FSL_IIM
271 bool "Enable FSL IC Identification Module (IIM) driver"
272 depends on ARCH_MX31 || ARCH_MX5
273
Peng Fanfb6166a2015-08-26 15:41:33 +0800274config FSL_SEC_MON
gaurav rana9aaea442015-02-27 09:44:22 +0530275 bool "Enable FSL SEC_MON Driver"
276 help
277 Freescale Security Monitor block is responsible for monitoring
278 system states.
279 Security Monitor can be transitioned on any security failures,
280 like software violations or hardware security violations.
Stefan Roese04b22752015-03-12 11:22:46 +0100281
Tom Rini0b58c2e2022-06-16 14:04:39 -0400282choice
283 prompt "Security monitor interaction endianess"
284 depends on FSL_SEC_MON
285 default SYS_FSL_SEC_MON_BE if PPC
286 default SYS_FSL_SEC_MON_LE
287
288config SYS_FSL_SEC_MON_LE
289 bool "Security monitor interactions are little endian"
290
291config SYS_FSL_SEC_MON_BE
292 bool "Security monitor interactions are big endian"
293
294endchoice
295
Simon Glassff418d92019-12-06 21:41:58 -0700296config IRQ
Wasim Khan55c9b9c2021-03-08 16:48:13 +0100297 bool "Interrupt controller"
Simon Glassff418d92019-12-06 21:41:58 -0700298 help
Wasim Khan55c9b9c2021-03-08 16:48:13 +0100299 This enables support for interrupt controllers, including ITSS.
Simon Glassff418d92019-12-06 21:41:58 -0700300 Some devices have extra features, such as Apollo Lake. The
301 device has its own uclass since there are several operations
302 involved.
303
Paul Burton738d8a82018-12-16 19:25:19 -0300304config JZ4780_EFUSE
305 bool "Ingenic JZ4780 eFUSE support"
306 depends on ARCH_JZ47XX
307 help
308 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
309
Sean Anderson6b39d352022-04-22 14:34:18 -0400310config LS2_SFP
311 bool "Layerscape Security Fuse Processor"
312 depends on FSL_LSCH2 || ARCH_LS1021A
313 depends on MISC
314 imply DM_REGULATOR
315 help
316 This adds support for the Security Fuse Processor found on Layerscape
317 SoCs. It contains various fuses related to secure boot, including the
318 Super Root Key hash, One-Time-Programmable Master Key, Debug
319 Challenge/Response values, and others. Fuses are numbered according
320 to their four-byte offset from the start of the bank.
321
322 If you don't need to read/program fuses, say 'n'.
323
Peng Fane1872252015-08-27 14:49:05 +0800324config MXC_OCOTP
325 bool "Enable MXC OCOTP Driver"
Peng Fanc45a81a2019-07-22 01:24:55 +0000326 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswilerf2213142019-03-25 17:24:57 +0100327 default y
Peng Fane1872252015-08-27 14:49:05 +0800328 help
329 If you say Y here, you will get support for the One Time
330 Programmable memory pages that are stored on the some
331 Freescale i.MX processors.
332
Tom Rini5a0f9d82022-11-19 18:45:28 -0500333config MXS_OCOTP
334 bool "Enable MXS OCOTP Driver"
335 depends on ARCH_MX23 || ARCH_MX28
336 help
337 If you say Y here, you will get support for the One Time
338 Programmable memory pages that are stored on the
339 Freescale i.MXS family of processors.
340
Jim Liucce4eed2022-06-24 16:24:37 +0800341config NPCM_HOST
342 bool "Enable support espi or LPC for Host"
343 depends on REGMAP && SYSCON
344 help
345 Enable NPCM BMC espi or LPC support for Host reading and writing.
346
Michael Scott92676142021-09-25 19:49:28 +0300347config SPL_MXC_OCOTP
348 bool "Enable MXC OCOTP driver in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400349 depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
Michael Scott92676142021-09-25 19:49:28 +0300350 default y
351 help
352 If you say Y here, you will get support for the One Time
353 Programmable memory pages, that are stored on some
354 Freescale i.MX processors, in SPL.
355
Jim Liufab2eff2022-06-07 16:33:54 +0800356config NPCM_OTP
357 bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
358 depends on (ARM && ARCH_NPCM)
359 default n
360 help
361 Support NPCM BMC OTP memory (fuse).
362 To compile this driver as a module, choose M here: the module
363 will be called npcm_otp.
364
Ye Lic408ed32022-07-26 16:40:49 +0800365config IMX_SENTINEL
366 bool "Enable i.MX Sentinel MU driver and API"
367 depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
368 help
369 If you say Y here to enable Message Unit driver to work with
370 Sentinel core on some NXP i.MX processors.
371
Stefan Roese4a269f22016-07-19 07:45:46 +0200372config NUVOTON_NCT6102D
373 bool "Enable Nuvoton NCT6102D Super I/O driver"
374 help
375 If you say Y here, you will get support for the Nuvoton
376 NCT6102D Super I/O driver. This can be used to enable or
377 disable the legacy UART, the watchdog or other devices
378 in the Nuvoton Super IO chips on X86 platforms.
379
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700380config P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200381 bool "Intel Primary to Sideband Bridge"
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700382 depends on X86 || SANDBOX
383 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200384 This enables support for the Intel Primary to Sideband Bridge,
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700385 abbreviated to P2SB. The P2SB is used to access various peripherals
386 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
387 space. The space is segmented into different channels and peripherals
388 are accessed by device-specific means within those channels. Devices
389 should be added in the device tree as subnodes of the P2SB. A
390 Peripheral Channel Register? (PCR) API is provided to access those
391 devices - see pcr_readl(), etc.
392
393config SPL_P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200394 bool "Intel Primary to Sideband Bridge in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400395 depends on SPL_MISC && (X86 || SANDBOX)
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700396 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200397 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700398 through memory-mapped I/O in a large chunk of PCI space. The space is
399 segmented into different channels and peripherals are accessed by
400 device-specific means within those channels. Devices should be added
401 in the device tree as subnodes of the p2sb.
402
403config TPL_P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200404 bool "Intel Primary to Sideband Bridge in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400405 depends on TPL_MISC && (X86 || SANDBOX)
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700406 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200407 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700408 through memory-mapped I/O in a large chunk of PCI space. The space is
409 segmented into different channels and peripherals are accessed by
410 device-specific means within those channels. Devices should be added
411 in the device tree as subnodes of the p2sb.
412
Simon Glassc9795172016-01-21 19:43:31 -0700413config PWRSEQ
414 bool "Enable power-sequencing drivers"
415 depends on DM
416 help
417 Power-sequencing drivers provide support for controlling power for
418 devices. They are typically referenced by a phandle from another
419 device. When the device is started up, its power sequence can be
420 initiated.
421
422config SPL_PWRSEQ
423 bool "Enable power-sequencing drivers for SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400424 depends on SPL_MISC && PWRSEQ
Simon Glassc9795172016-01-21 19:43:31 -0700425 help
426 Power-sequencing drivers provide support for controlling power for
427 devices. They are typically referenced by a phandle from another
428 device. When the device is started up, its power sequence can be
429 initiated.
430
Stefan Roese04b22752015-03-12 11:22:46 +0100431config PCA9551_LED
432 bool "Enable PCA9551 LED driver"
433 help
434 Enable driver for PCA9551 LED controller. This controller
435 is connected via I2C. So I2C needs to be enabled.
436
437config PCA9551_I2C_ADDR
438 hex "I2C address of PCA9551 LED controller"
439 depends on PCA9551_LED
440 default 0x60
441 help
442 The I2C address of the PCA9551 LED controller.
Simon Glass14000862015-06-23 15:39:13 -0600443
Patrick Delaunay0c4656b2018-05-17 15:24:06 +0200444config STM32MP_FUSE
445 bool "Enable STM32MP fuse wrapper providing the fuse API"
446 depends on ARCH_STM32MP && MISC
447 default y if CMD_FUSE
448 help
449 If you say Y here, you will get support for the fuse API (OTP)
450 for STM32MP architecture.
451 This API is needed for CMD_FUSE.
452
Christophe Kerello275f7062017-09-13 18:00:08 +0200453config STM32_RCC
454 bool "Enable RCC driver for the STM32 SoC's family"
Trevor Woerner2bcc1ed2020-05-06 08:02:42 -0400455 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
Christophe Kerello275f7062017-09-13 18:00:08 +0200456 help
457 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
458 block) is responsible of the management of the clock and reset
459 generation.
460 This driver is similar to an MFD driver in the Linux kernel.
461
Stephen Warrenf6417002016-09-13 10:45:57 -0600462config TEGRA_CAR
463 bool "Enable support for the Tegra CAR driver"
464 depends on TEGRA_NO_BPMP
465 help
466 The Tegra CAR (Clock and Reset Controller) is a HW module that
467 controls almost all clocks and resets in a Tegra SoC.
468
Stephen Warrena2148922016-08-08 09:41:34 -0600469config TEGRA186_BPMP
470 bool "Enable support for the Tegra186 BPMP driver"
471 depends on TEGRA186
472 help
473 The Tegra BPMP (Boot and Power Management Processor) is a separate
474 auxiliary CPU embedded into Tegra to perform power management work,
475 and controls related features such as clocks, resets, power domains,
476 PMIC I2C bus, etc. This driver provides the core low-level
477 communication path by which feature-specific drivers (such as clock)
478 can make requests to the BPMP. This driver is similar to an MFD
479 driver in the Linux kernel.
480
Simon Glass4bf89722020-12-23 08:11:18 -0700481config TEST_DRV
482 bool "Enable support for test drivers"
483 default y if SANDBOX
484 help
485 This enables drivers and uclasses that provides a way of testing the
486 operations of memory allocation and driver/uclass methods in driver
487 model. This should only be enabled for testing as it is not useful for
488 anything else.
489
Marek Vasut16637b42022-04-10 06:27:14 +0200490config USB_HUB_USB251XB
491 tristate "USB251XB Hub Controller Configuration Driver"
492 depends on I2C
493 help
494 This option enables support for configuration via SMBus of the
495 Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
496 parameters may be set in devicetree or platform data.
497 Say Y or M here if you need to configure such a device via SMBus.
498
Adam Fordc8cdce72018-08-06 14:26:50 -0500499config TWL4030_LED
500 bool "Enable TWL4030 LED controller"
501 help
502 Enable this to add support for the TWL4030 LED controller.
503
Stefan Roeseba019ed2016-01-19 14:05:10 +0100504config WINBOND_W83627
505 bool "Enable Winbond Super I/O driver"
506 help
507 If you say Y here, you will get support for the Winbond
508 W83627 Super I/O driver. This can be used to enable the
509 legacy UART or other devices in the Winbond Super IO chips
510 on X86 platforms.
511
Miao Yan4fcd7f22016-05-22 19:37:14 -0700512config QFW
513 bool
514 help
Asherah Connor4ffa95d2021-03-19 18:21:40 +1100515 Hidden option to enable QEMU fw_cfg interface and uclass. This will
516 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
517
518config QFW_PIO
519 bool
520 depends on QFW
521 help
522 Hidden option to enable PIO QEMU fw_cfg interface. This will be
523 selected by the appropriate QEMU board.
Miao Yan4fcd7f22016-05-22 19:37:14 -0700524
Asherah Connorf0c0e542021-03-19 18:21:42 +1100525config QFW_MMIO
526 bool
527 depends on QFW
528 help
529 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
530 selected by the appropriate QEMU board.
531
mario.six@gdsys.cc7559ac42016-06-22 15:14:16 +0200532config I2C_EEPROM
533 bool "Enable driver for generic I2C-attached EEPROMs"
534 depends on MISC
535 help
536 Enable a generic driver for EEPROMs attached via I2C.
Adam Ford5664f832017-08-13 09:00:28 -0500537
Wenyou Yangf791d562017-09-06 13:08:14 +0800538
539config SPL_I2C_EEPROM
540 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400541 depends on SPL_MISC
Wenyou Yangf791d562017-09-06 13:08:14 +0800542 help
543 This option is an SPL-variant of the I2C_EEPROM option.
544 See the help of I2C_EEPROM for details.
545
Adam Ford5664f832017-08-13 09:00:28 -0500546config SYS_I2C_EEPROM_ADDR
547 hex "Chip address of the EEPROM device"
Tom Rinifaed5672021-08-17 17:59:45 -0400548 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
Adam Ford5664f832017-08-13 09:00:28 -0500549 default 0
Adam Ford5664f832017-08-13 09:00:28 -0500550
Tom Rinifaed5672021-08-17 17:59:45 -0400551if I2C_EEPROM
Adam Ford5664f832017-08-13 09:00:28 -0500552
553config SYS_I2C_EEPROM_ADDR_OVERFLOW
554 hex "EEPROM Address Overflow"
Tom Rinif0599552021-12-11 14:55:47 -0500555 default 0x0
Adam Ford5664f832017-08-13 09:00:28 -0500556 help
557 EEPROM chips that implement "address overflow" are ones
558 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
559 address and the extra bits end up in the "chip address" bit
560 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
561 byte chips.
562
563endif
564
Mario Six7f504a02018-04-27 14:53:33 +0200565config GDSYS_RXAUI_CTRL
566 bool "Enable gdsys RXAUI control driver"
567 depends on MISC
568 help
569 Support gdsys FPGA's RXAUI control.
Mario Six0cafb652018-07-31 14:24:15 +0200570
571config GDSYS_IOEP
572 bool "Enable gdsys IOEP driver"
573 depends on MISC
574 help
575 Support gdsys FPGA's IO endpoint driver.
Mario Six7fdcf282018-08-06 10:23:46 +0200576
577config MPC83XX_SERDES
578 bool "Enable MPC83xx serdes driver"
579 depends on MISC
580 help
581 Support for serdes found on MPC83xx SoCs.
582
Tien Fong Chee5ca878b2018-07-06 16:28:03 +0800583config FS_LOADER
584 bool "Enable loader driver for file system"
585 help
586 This is file system generic loader which can be used to load
587 the file image from the storage into target such as memory.
588
589 The consumer driver would then use this loader to program whatever,
590 ie. the FPGA device.
591
Keerthyfe8f6092022-01-27 13:16:53 +0100592config SPL_FS_LOADER
593 bool "Enable loader driver for file system"
Tom Rini0f311f22022-05-10 12:51:47 -0400594 depends on SPL
Keerthyfe8f6092022-01-27 13:16:53 +0100595 help
596 This is file system generic loader which can be used to load
597 the file image from the storage into target such as memory.
598
599 The consumer driver would then use this loader to program whatever,
600 ie. the FPGA device.
601
Mario Six8862f452018-10-04 09:00:54 +0200602config GDSYS_SOC
603 bool "Enable gdsys SOC driver"
604 depends on MISC
605 help
606 Support for gdsys IHS SOC, a simple bus associated with each gdsys
607 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
608 register maps are contained within the FPGA's register map.
609
Mario Six1a9d43f2018-10-04 09:00:55 +0200610config IHS_FPGA
611 bool "Enable IHS FPGA driver"
612 depends on MISC
613 help
614 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
615 gdsys devices, which supply the majority of the functionality offered
616 by the devices. This driver supports both CON and CPU variants of the
617 devices, depending on the device tree entry.
Tero Kristof81f4cd2020-02-14 11:18:15 +0200618config ESM_K3
619 bool "Enable K3 ESM driver"
620 depends on ARCH_K3
621 help
622 Support ESM (Error Signaling Module) on TI K3 SoCs.
Mario Six1a9d43f2018-10-04 09:00:55 +0200623
Eugen Hristev3bd56102019-10-09 09:23:39 +0000624config MICROCHIP_FLEXCOM
625 bool "Enable Microchip Flexcom driver"
626 depends on MISC
627 help
628 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
629 an I2C controller and an USART.
630 Only one function can be used at a time and is chosen at boot time
631 according to the device tree.
632
Tero Kristo887dde52019-10-24 15:00:46 +0530633config K3_AVS0
634 depends on ARCH_K3 && SPL_DM_REGULATOR
635 bool "AVS class 0 support for K3 devices"
636 help
637 K3 devices have the optimized voltage values for the main voltage
638 domains stored in efuse within the VTM IP. This driver reads the
639 optimized voltage from the efuse, so that it can be programmed
640 to the PMIC on board.
641
Tero Kristo1444e112020-02-14 11:18:16 +0200642config ESM_PMIC
643 bool "Enable PMIC ESM driver"
644 depends on DM_PMIC
645 help
646 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
647 typically to reboot the board in error condition.
648
Tom Rini05b419e2021-12-11 14:55:49 -0500649config FSL_IFC
650 bool
651
Michael Walle2184cc62022-02-25 18:06:24 +0530652config SL28CPLD
653 bool "Enable Kontron sl28cpld multi-function driver"
654 depends on DM_I2C
655 help
656 Support for the Kontron sl28cpld management controller. This is
657 the base driver which provides common access methods for the
658 sub-drivers.
659
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900660endmenu