blob: 041de538fac4b2371c50c359d2f8970bbc3babf9 [file] [log] [blame]
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Choub1ed6862015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glass605931c2018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
Sean Anderson63c318f2022-04-22 16:11:37 -040019 default MISC
Simon Glass605931c2018-11-18 08:14:27 -070020 help
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
24 access the device.
25
26config TPL_MISC
27 bool "Enable Driver Model for Misc drivers in TPL"
28 depends on TPL_DM
Sean Anderson63c318f2022-04-22 16:11:37 -040029 default MISC
30 help
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
34 access the device.
35
36config VPL_MISC
37 bool "Enable Driver Model for Misc drivers in VPL"
38 depends on VPL_DM
39 default MISC
Simon Glass605931c2018-11-18 08:14:27 -070040 help
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
44 access the device.
45
Sean Anderson77c66292022-05-05 13:11:39 -040046config NVMEM
47 bool "NVMEM support"
48 help
49 This adds support for a common interface to different types of
50 non-volatile memory. Consumers can use nvmem-cells properties to look
51 up hardware configuration data such as MAC addresses and calibration
52 settings.
53
54config SPL_NVMEM
55 bool "NVMEM support in SPL"
56 help
57 This adds support for a common interface to different types of
58 non-volatile memory. Consumers can use nvmem-cells properties to look
59 up hardware configuration data such as MAC addresses and calibration
60 settings.
61
Thomas Chou36b9c9a2015-10-14 08:43:31 +080062config ALTERA_SYSID
63 bool "Altera Sysid support"
64 depends on MISC
65 help
66 Select this to enable a sysid for Altera devices. Please find
67 details on the "Embedded Peripherals IP User Guide" of Altera.
68
Marek Behúnef2b6b12017-06-09 19:28:44 +020069config ATSHA204A
70 bool "Support for Atmel ATSHA204A module"
Pali Rohár2e269302022-04-12 11:20:44 +020071 select BITREVERSE
Marek Behúnef2b6b12017-06-09 19:28:44 +020072 depends on MISC
73 help
74 Enable support for I2C connected Atmel's ATSHA204A
75 CryptoAuthentication module found for example on the Turris Omnia
76 board.
77
Tim Harveyb8204602022-03-07 16:24:04 -080078config GATEWORKS_SC
79 bool "Gateworks System Controller Support"
80 depends on MISC
81 help
82 Enable access for the Gateworks System Controller used on Gateworks
83 boards to provide a boot watchdog, power control, temperature monitor,
84 voltage ADCs, and EEPROM.
85
Philipp Tomsichfcc1d632017-05-05 19:21:38 +020086config ROCKCHIP_EFUSE
87 bool "Rockchip e-fuse support"
88 depends on MISC
89 help
90 Enable (read-only) access for the e-fuse block found in Rockchip
91 SoCs: accesses can either be made using byte addressing and a length
92 or through child-nodes that are generated based on the e-fuse map
93 retrieved from the DTS.
94
Finley Xiao20d52a02019-09-25 17:57:49 +020095config ROCKCHIP_OTP
96 bool "Rockchip OTP Support"
97 depends on MISC
98 help
99 Enable (read-only) access for the one-time-programmable memory block
100 found in Rockchip SoCs: accesses can either be made using byte
101 addressing and a length or through child-nodes that are generated
102 based on the e-fuse map retrieved from the DTS.
103
Jonas Karlmana937c3d2023-08-21 22:30:28 +0000104config ROCKCHIP_IODOMAIN
105 bool "Rockchip IO-domain driver support"
106 depends on DM_REGULATOR && ARCH_ROCKCHIP
107 default y if ROCKCHIP_RK3568
108 help
109 Enable support for IO-domains in Rockchip SoCs. It is necessary
110 for the IO-domain setting of the SoC to match the voltage supplied
111 by the regulators.
112
Pragnesh Patel6e9661f2020-05-29 11:33:21 +0530113config SIFIVE_OTP
114 bool "SiFive eMemory OTP driver"
115 depends on MISC
116 help
117 Enable support for reading and writing the eMemory OTP on the
118 SiFive SoCs.
119
Tom Rini035e8722022-11-19 18:45:33 -0500120config SMSC_LPC47M
121 bool "LPC47M SMSC driver"
122
123config SMSC_SIO1007
124 bool "SIO1007 SMSC driver"
125
Liviu Dudau688db7f2018-09-28 13:43:31 +0100126config VEXPRESS_CONFIG
127 bool "Enable support for Arm Versatile Express config bus"
128 depends on MISC
129 help
130 If you say Y here, you will get support for accessing the
131 configuration bus on the Arm Versatile Express boards via
132 a sysreg driver.
133
Simon Glass036ca142023-09-10 13:13:02 -0600134config CBMEM_CONSOLE
135 bool "Write console output to coreboot cbmem"
136 depends on X86
137 help
138 Enables console output to the cbmem console, which is a memory
139 region set up by coreboot to hold a record of all console output.
140 Enable this only if booting from coreboot.
141
Simon Glass5b79bb22015-02-13 12:20:47 -0700142config CMD_CROS_EC
143 bool "Enable crosec command"
144 depends on CROS_EC
145 help
146 Enable command-line access to the Chrome OS EC (Embedded
147 Controller). This provides the 'crosec' command which has
148 a number of sub-commands for performing EC tasks such as
149 updating its flash, accessing a small saved context area
150 and talking to the I2C bus behind the EC (if there is one).
151
152config CROS_EC
153 bool "Enable Chrome OS EC"
154 help
155 Enable access to the Chrome OS EC. This is a separate
156 microcontroller typically available on a SPI bus on Chromebooks. It
157 provides access to the keyboard, some internal storage and may
158 control access to the battery and main PMIC depending on the
159 device. You can use the 'crosec' command to access it.
160
Simon Glass605931c2018-11-18 08:14:27 -0700161config SPL_CROS_EC
162 bool "Enable Chrome OS EC in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400163 depends on SPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700164 help
165 Enable access to the Chrome OS EC in SPL. This is a separate
166 microcontroller typically available on a SPI bus on Chromebooks. It
167 provides access to the keyboard, some internal storage and may
168 control access to the battery and main PMIC depending on the
169 device. You can use the 'crosec' command to access it.
170
171config TPL_CROS_EC
172 bool "Enable Chrome OS EC in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400173 depends on TPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700174 help
175 Enable access to the Chrome OS EC in TPL. This is a separate
176 microcontroller typically available on a SPI bus on Chromebooks. It
177 provides access to the keyboard, some internal storage and may
178 control access to the battery and main PMIC depending on the
179 device. You can use the 'crosec' command to access it.
180
Simon Glasse7ca7da2022-04-30 00:56:53 -0600181config VPL_CROS_EC
182 bool "Enable Chrome OS EC in VPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400183 depends on VPL_MISC
Simon Glasse7ca7da2022-04-30 00:56:53 -0600184 help
185 Enable access to the Chrome OS EC in VPL. This is a separate
186 microcontroller typically available on a SPI bus on Chromebooks. It
187 provides access to the keyboard, some internal storage and may
188 control access to the battery and main PMIC depending on the
189 device. You can use the 'crosec' command to access it.
190
Simon Glass5b79bb22015-02-13 12:20:47 -0700191config CROS_EC_I2C
192 bool "Enable Chrome OS EC I2C driver"
193 depends on CROS_EC
194 help
195 Enable I2C access to the Chrome OS EC. This is used on older
196 ARM Chromebooks such as snow and spring before the standard bus
197 changed to SPI. The EC will accept commands across the I2C using
198 a special message protocol, and provide responses.
199
200config CROS_EC_LPC
201 bool "Enable Chrome OS EC LPC driver"
202 depends on CROS_EC
203 help
204 Enable I2C access to the Chrome OS EC. This is used on x86
205 Chromebooks such as link and falco. The keyboard is provided
206 through a legacy port interface, so on x86 machines the main
207 function of the EC is power and thermal management.
208
Simon Glass605931c2018-11-18 08:14:27 -0700209config SPL_CROS_EC_LPC
210 bool "Enable Chrome OS EC LPC driver in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400211 depends on CROS_EC && SPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700212 help
213 Enable I2C access to the Chrome OS EC. This is used on x86
214 Chromebooks such as link and falco. The keyboard is provided
215 through a legacy port interface, so on x86 machines the main
216 function of the EC is power and thermal management.
217
218config TPL_CROS_EC_LPC
219 bool "Enable Chrome OS EC LPC driver in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400220 depends on CROS_EC && TPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700221 help
222 Enable I2C access to the Chrome OS EC. This is used on x86
223 Chromebooks such as link and falco. The keyboard is provided
224 through a legacy port interface, so on x86 machines the main
225 function of the EC is power and thermal management.
226
Simon Glasse7ca7da2022-04-30 00:56:53 -0600227config VPL_CROS_EC_LPC
228 bool "Enable Chrome OS EC LPC driver in VPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400229 depends on CROS_EC && VPL_MISC
Simon Glasse7ca7da2022-04-30 00:56:53 -0600230 help
231 Enable I2C access to the Chrome OS EC. This is used on x86
232 Chromebooks such as link and falco. The keyboard is provided
233 through a legacy port interface, so on x86 machines the main
234 function of the EC is power and thermal management.
235
Simon Glassc6e06692015-03-26 09:29:40 -0600236config CROS_EC_SANDBOX
237 bool "Enable Chrome OS EC sandbox driver"
238 depends on CROS_EC && SANDBOX
239 help
240 Enable a sandbox emulation of the Chrome OS EC. This supports
241 keyboard (use the -l flag to enable the LCD), verified boot context,
242 EC flash read/write/erase support and a few other things. It is
243 enough to perform a Chrome OS verified boot on sandbox.
244
Simon Glass605931c2018-11-18 08:14:27 -0700245config SPL_CROS_EC_SANDBOX
246 bool "Enable Chrome OS EC sandbox driver in SPL"
247 depends on SPL_CROS_EC && SANDBOX
248 help
249 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
250 keyboard (use the -l flag to enable the LCD), verified boot context,
251 EC flash read/write/erase support and a few other things. It is
252 enough to perform a Chrome OS verified boot on sandbox.
253
254config TPL_CROS_EC_SANDBOX
255 bool "Enable Chrome OS EC sandbox driver in TPL"
256 depends on TPL_CROS_EC && SANDBOX
257 help
258 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
259 keyboard (use the -l flag to enable the LCD), verified boot context,
260 EC flash read/write/erase support and a few other things. It is
261 enough to perform a Chrome OS verified boot on sandbox.
262
Simon Glasse7ca7da2022-04-30 00:56:53 -0600263config VPL_CROS_EC_SANDBOX
264 bool "Enable Chrome OS EC sandbox driver in VPL"
265 depends on VPL_CROS_EC && SANDBOX
266 help
267 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
268 keyboard (use the -l flag to enable the LCD), verified boot context,
269 EC flash read/write/erase support and a few other things. It is
270 enough to perform a Chrome OS verified boot on sandbox.
271
Simon Glass5b79bb22015-02-13 12:20:47 -0700272config CROS_EC_SPI
273 bool "Enable Chrome OS EC SPI driver"
274 depends on CROS_EC
275 help
276 Enable SPI access to the Chrome OS EC. This is used on newer
277 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
278 provides a faster and more robust interface than I2C but the bugs
279 are less interesting.
280
Simon Glass58ed3222017-05-17 03:25:02 -0600281config DS4510
282 bool "Enable support for DS4510 CPU supervisor"
283 help
284 Enable support for the Maxim DS4510 CPU supervisor. It has an
285 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
286 and a configurable timer for the supervisor function. The device is
287 connected over I2C.
288
Tom Rini66fa77a2022-11-19 18:45:11 -0500289config FSL_IIM
290 bool "Enable FSL IC Identification Module (IIM) driver"
291 depends on ARCH_MX31 || ARCH_MX5
292
Peng Fanfb6166a2015-08-26 15:41:33 +0800293config FSL_SEC_MON
gaurav rana9aaea442015-02-27 09:44:22 +0530294 bool "Enable FSL SEC_MON Driver"
295 help
296 Freescale Security Monitor block is responsible for monitoring
297 system states.
298 Security Monitor can be transitioned on any security failures,
299 like software violations or hardware security violations.
Stefan Roese04b22752015-03-12 11:22:46 +0100300
Tom Rini0b58c2e2022-06-16 14:04:39 -0400301choice
302 prompt "Security monitor interaction endianess"
303 depends on FSL_SEC_MON
304 default SYS_FSL_SEC_MON_BE if PPC
305 default SYS_FSL_SEC_MON_LE
306
307config SYS_FSL_SEC_MON_LE
308 bool "Security monitor interactions are little endian"
309
310config SYS_FSL_SEC_MON_BE
311 bool "Security monitor interactions are big endian"
312
313endchoice
314
Simon Glassff418d92019-12-06 21:41:58 -0700315config IRQ
Wasim Khan55c9b9c2021-03-08 16:48:13 +0100316 bool "Interrupt controller"
Simon Glassff418d92019-12-06 21:41:58 -0700317 help
Wasim Khan55c9b9c2021-03-08 16:48:13 +0100318 This enables support for interrupt controllers, including ITSS.
Simon Glassff418d92019-12-06 21:41:58 -0700319 Some devices have extra features, such as Apollo Lake. The
320 device has its own uclass since there are several operations
321 involved.
322
Paul Burton738d8a82018-12-16 19:25:19 -0300323config JZ4780_EFUSE
324 bool "Ingenic JZ4780 eFUSE support"
325 depends on ARCH_JZ47XX
326 help
327 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
328
Sean Anderson6b39d352022-04-22 14:34:18 -0400329config LS2_SFP
330 bool "Layerscape Security Fuse Processor"
331 depends on FSL_LSCH2 || ARCH_LS1021A
332 depends on MISC
333 imply DM_REGULATOR
334 help
335 This adds support for the Security Fuse Processor found on Layerscape
336 SoCs. It contains various fuses related to secure boot, including the
337 Super Root Key hash, One-Time-Programmable Master Key, Debug
338 Challenge/Response values, and others. Fuses are numbered according
339 to their four-byte offset from the start of the bank.
340
341 If you don't need to read/program fuses, say 'n'.
342
Peng Fane1872252015-08-27 14:49:05 +0800343config MXC_OCOTP
344 bool "Enable MXC OCOTP Driver"
Peng Fanc45a81a2019-07-22 01:24:55 +0000345 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswilerf2213142019-03-25 17:24:57 +0100346 default y
Peng Fane1872252015-08-27 14:49:05 +0800347 help
348 If you say Y here, you will get support for the One Time
349 Programmable memory pages that are stored on the some
350 Freescale i.MX processors.
351
Tom Rini5a0f9d82022-11-19 18:45:28 -0500352config MXS_OCOTP
353 bool "Enable MXS OCOTP Driver"
354 depends on ARCH_MX23 || ARCH_MX28
355 help
356 If you say Y here, you will get support for the One Time
357 Programmable memory pages that are stored on the
358 Freescale i.MXS family of processors.
359
Jim Liucce4eed2022-06-24 16:24:37 +0800360config NPCM_HOST
361 bool "Enable support espi or LPC for Host"
362 depends on REGMAP && SYSCON
363 help
364 Enable NPCM BMC espi or LPC support for Host reading and writing.
365
Michael Scott92676142021-09-25 19:49:28 +0300366config SPL_MXC_OCOTP
367 bool "Enable MXC OCOTP driver in SPL"
Jean-Marie Lemetayerf17d43d2023-02-13 14:12:25 +0100368 depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
Michael Scott92676142021-09-25 19:49:28 +0300369 default y
370 help
371 If you say Y here, you will get support for the One Time
372 Programmable memory pages, that are stored on some
373 Freescale i.MX processors, in SPL.
374
Jim Liufab2eff2022-06-07 16:33:54 +0800375config NPCM_OTP
376 bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
377 depends on (ARM && ARCH_NPCM)
Jim Liufab2eff2022-06-07 16:33:54 +0800378 help
379 Support NPCM BMC OTP memory (fuse).
380 To compile this driver as a module, choose M here: the module
381 will be called npcm_otp.
382
Peng Fand5c31832023-06-15 18:09:05 +0800383config IMX_ELE
384 bool "Enable i.MX EdgeLock Enclave MU driver and API"
Ye Lic408ed32022-07-26 16:40:49 +0800385 depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
386 help
387 If you say Y here to enable Message Unit driver to work with
388 Sentinel core on some NXP i.MX processors.
389
Stefan Roese4a269f22016-07-19 07:45:46 +0200390config NUVOTON_NCT6102D
391 bool "Enable Nuvoton NCT6102D Super I/O driver"
392 help
393 If you say Y here, you will get support for the Nuvoton
394 NCT6102D Super I/O driver. This can be used to enable or
395 disable the legacy UART, the watchdog or other devices
396 in the Nuvoton Super IO chips on X86 platforms.
397
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700398config P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200399 bool "Intel Primary to Sideband Bridge"
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700400 depends on X86 || SANDBOX
401 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200402 This enables support for the Intel Primary to Sideband Bridge,
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700403 abbreviated to P2SB. The P2SB is used to access various peripherals
404 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
405 space. The space is segmented into different channels and peripherals
406 are accessed by device-specific means within those channels. Devices
407 should be added in the device tree as subnodes of the P2SB. A
408 Peripheral Channel Register? (PCR) API is provided to access those
409 devices - see pcr_readl(), etc.
410
411config SPL_P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200412 bool "Intel Primary to Sideband Bridge in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400413 depends on SPL_MISC && (X86 || SANDBOX)
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700414 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200415 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700416 through memory-mapped I/O in a large chunk of PCI space. The space is
417 segmented into different channels and peripherals are accessed by
418 device-specific means within those channels. Devices should be added
419 in the device tree as subnodes of the p2sb.
420
421config TPL_P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200422 bool "Intel Primary to Sideband Bridge in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400423 depends on TPL_MISC && (X86 || SANDBOX)
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700424 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200425 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700426 through memory-mapped I/O in a large chunk of PCI space. The space is
427 segmented into different channels and peripherals are accessed by
428 device-specific means within those channels. Devices should be added
429 in the device tree as subnodes of the p2sb.
430
Simon Glassc9795172016-01-21 19:43:31 -0700431config PWRSEQ
432 bool "Enable power-sequencing drivers"
433 depends on DM
434 help
435 Power-sequencing drivers provide support for controlling power for
436 devices. They are typically referenced by a phandle from another
437 device. When the device is started up, its power sequence can be
438 initiated.
439
440config SPL_PWRSEQ
441 bool "Enable power-sequencing drivers for SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400442 depends on SPL_MISC && PWRSEQ
Simon Glassc9795172016-01-21 19:43:31 -0700443 help
444 Power-sequencing drivers provide support for controlling power for
445 devices. They are typically referenced by a phandle from another
446 device. When the device is started up, its power sequence can be
447 initiated.
448
Stefan Roese04b22752015-03-12 11:22:46 +0100449config PCA9551_LED
450 bool "Enable PCA9551 LED driver"
451 help
452 Enable driver for PCA9551 LED controller. This controller
453 is connected via I2C. So I2C needs to be enabled.
454
455config PCA9551_I2C_ADDR
456 hex "I2C address of PCA9551 LED controller"
457 depends on PCA9551_LED
458 default 0x60
459 help
460 The I2C address of the PCA9551 LED controller.
Simon Glass14000862015-06-23 15:39:13 -0600461
Patrick Delaunay0c4656b2018-05-17 15:24:06 +0200462config STM32MP_FUSE
463 bool "Enable STM32MP fuse wrapper providing the fuse API"
464 depends on ARCH_STM32MP && MISC
465 default y if CMD_FUSE
466 help
467 If you say Y here, you will get support for the fuse API (OTP)
468 for STM32MP architecture.
469 This API is needed for CMD_FUSE.
470
Christophe Kerello275f7062017-09-13 18:00:08 +0200471config STM32_RCC
472 bool "Enable RCC driver for the STM32 SoC's family"
Trevor Woerner2bcc1ed2020-05-06 08:02:42 -0400473 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
Christophe Kerello275f7062017-09-13 18:00:08 +0200474 help
475 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
476 block) is responsible of the management of the clock and reset
477 generation.
478 This driver is similar to an MFD driver in the Linux kernel.
479
Stephen Warrenf6417002016-09-13 10:45:57 -0600480config TEGRA_CAR
481 bool "Enable support for the Tegra CAR driver"
482 depends on TEGRA_NO_BPMP
483 help
484 The Tegra CAR (Clock and Reset Controller) is a HW module that
485 controls almost all clocks and resets in a Tegra SoC.
486
Stephen Warrena2148922016-08-08 09:41:34 -0600487config TEGRA186_BPMP
488 bool "Enable support for the Tegra186 BPMP driver"
489 depends on TEGRA186
490 help
491 The Tegra BPMP (Boot and Power Management Processor) is a separate
492 auxiliary CPU embedded into Tegra to perform power management work,
493 and controls related features such as clocks, resets, power domains,
494 PMIC I2C bus, etc. This driver provides the core low-level
495 communication path by which feature-specific drivers (such as clock)
496 can make requests to the BPMP. This driver is similar to an MFD
497 driver in the Linux kernel.
498
Simon Glass4bf89722020-12-23 08:11:18 -0700499config TEST_DRV
500 bool "Enable support for test drivers"
501 default y if SANDBOX
502 help
503 This enables drivers and uclasses that provides a way of testing the
504 operations of memory allocation and driver/uclass methods in driver
505 model. This should only be enabled for testing as it is not useful for
506 anything else.
507
Marek Behúnea51ee52024-04-04 09:51:03 +0200508config TURRIS_OMNIA_MCU
509 bool "Enable Turris Omnia MCU driver"
510 depends on DM_I2C
511 depends on DM_GPIO
512 depends on SYSRESET
513 default y if TARGET_TURRIS_OMNIA
514 help
515 This enables support for Turris Omnia MCU connected GPIOs and
516 board power off.
517
Marek Vasut16637b42022-04-10 06:27:14 +0200518config USB_HUB_USB251XB
519 tristate "USB251XB Hub Controller Configuration Driver"
520 depends on I2C
521 help
522 This option enables support for configuration via SMBus of the
523 Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
524 parameters may be set in devicetree or platform data.
525 Say Y or M here if you need to configure such a device via SMBus.
526
Adam Fordc8cdce72018-08-06 14:26:50 -0500527config TWL4030_LED
528 bool "Enable TWL4030 LED controller"
529 help
530 Enable this to add support for the TWL4030 LED controller.
531
Stefan Roeseba019ed2016-01-19 14:05:10 +0100532config WINBOND_W83627
533 bool "Enable Winbond Super I/O driver"
534 help
535 If you say Y here, you will get support for the Winbond
536 W83627 Super I/O driver. This can be used to enable the
537 legacy UART or other devices in the Winbond Super IO chips
538 on X86 platforms.
539
Miao Yan4fcd7f22016-05-22 19:37:14 -0700540config QFW
541 bool
542 help
Asherah Connor4ffa95d2021-03-19 18:21:40 +1100543 Hidden option to enable QEMU fw_cfg interface and uclass. This will
544 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
545
Heinrich Schuchardt223605f2023-12-19 16:04:00 +0100546config QFW_ACPI
547 bool
548 default y
549 depends on QFW && GENERATE_ACPI_TABLE && !SANDBOX
550 help
551 Hidden option to read ACPI tables from QEMU.
552
Asherah Connor4ffa95d2021-03-19 18:21:40 +1100553config QFW_PIO
554 bool
555 depends on QFW
556 help
557 Hidden option to enable PIO QEMU fw_cfg interface. This will be
558 selected by the appropriate QEMU board.
Miao Yan4fcd7f22016-05-22 19:37:14 -0700559
Asherah Connorf0c0e542021-03-19 18:21:42 +1100560config QFW_MMIO
561 bool
562 depends on QFW
563 help
564 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
565 selected by the appropriate QEMU board.
566
Heinrich Schuchardt08d931a2023-12-23 02:03:34 +0100567config QFW_SMBIOS
568 bool
569 default y
570 depends on QFW && SMBIOS && !SANDBOX
571 help
572 Hidden option to read SMBIOS tables from QEMU.
573
mario.six@gdsys.cc7559ac42016-06-22 15:14:16 +0200574config I2C_EEPROM
575 bool "Enable driver for generic I2C-attached EEPROMs"
576 depends on MISC
577 help
578 Enable a generic driver for EEPROMs attached via I2C.
Adam Ford5664f832017-08-13 09:00:28 -0500579
Wenyou Yangf791d562017-09-06 13:08:14 +0800580
581config SPL_I2C_EEPROM
582 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400583 depends on SPL_MISC
Wenyou Yangf791d562017-09-06 13:08:14 +0800584 help
585 This option is an SPL-variant of the I2C_EEPROM option.
586 See the help of I2C_EEPROM for details.
587
Adam Ford5664f832017-08-13 09:00:28 -0500588config SYS_I2C_EEPROM_ADDR
589 hex "Chip address of the EEPROM device"
Tom Rinifaed5672021-08-17 17:59:45 -0400590 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
Tom Rinif18679c2023-08-02 11:09:43 -0400591 default 0x0
Adam Ford5664f832017-08-13 09:00:28 -0500592
Tom Rinifaed5672021-08-17 17:59:45 -0400593if I2C_EEPROM
Adam Ford5664f832017-08-13 09:00:28 -0500594
595config SYS_I2C_EEPROM_ADDR_OVERFLOW
596 hex "EEPROM Address Overflow"
Tom Rinif0599552021-12-11 14:55:47 -0500597 default 0x0
Adam Ford5664f832017-08-13 09:00:28 -0500598 help
599 EEPROM chips that implement "address overflow" are ones
600 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
601 address and the extra bits end up in the "chip address" bit
602 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
603 byte chips.
604
605endif
606
Mario Six7f504a02018-04-27 14:53:33 +0200607config GDSYS_RXAUI_CTRL
608 bool "Enable gdsys RXAUI control driver"
609 depends on MISC
610 help
611 Support gdsys FPGA's RXAUI control.
Mario Six0cafb652018-07-31 14:24:15 +0200612
613config GDSYS_IOEP
614 bool "Enable gdsys IOEP driver"
615 depends on MISC
616 help
617 Support gdsys FPGA's IO endpoint driver.
Mario Six7fdcf282018-08-06 10:23:46 +0200618
619config MPC83XX_SERDES
620 bool "Enable MPC83xx serdes driver"
621 depends on MISC
622 help
623 Support for serdes found on MPC83xx SoCs.
624
Tien Fong Chee5ca878b2018-07-06 16:28:03 +0800625config FS_LOADER
626 bool "Enable loader driver for file system"
627 help
628 This is file system generic loader which can be used to load
629 the file image from the storage into target such as memory.
630
631 The consumer driver would then use this loader to program whatever,
632 ie. the FPGA device.
633
Keerthyfe8f6092022-01-27 13:16:53 +0100634config SPL_FS_LOADER
Alexander Gendin1c1a8842023-11-20 20:21:51 +0000635 bool "Enable loader driver for file system in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400636 depends on SPL
Keerthyfe8f6092022-01-27 13:16:53 +0100637 help
638 This is file system generic loader which can be used to load
639 the file image from the storage into target such as memory.
640
641 The consumer driver would then use this loader to program whatever,
642 ie. the FPGA device.
643
Mario Six8862f452018-10-04 09:00:54 +0200644config GDSYS_SOC
645 bool "Enable gdsys SOC driver"
646 depends on MISC
647 help
648 Support for gdsys IHS SOC, a simple bus associated with each gdsys
649 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
650 register maps are contained within the FPGA's register map.
651
Mario Six1a9d43f2018-10-04 09:00:55 +0200652config IHS_FPGA
653 bool "Enable IHS FPGA driver"
654 depends on MISC
655 help
656 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
657 gdsys devices, which supply the majority of the functionality offered
658 by the devices. This driver supports both CON and CPU variants of the
659 devices, depending on the device tree entry.
Tero Kristof81f4cd2020-02-14 11:18:15 +0200660config ESM_K3
661 bool "Enable K3 ESM driver"
662 depends on ARCH_K3
663 help
664 Support ESM (Error Signaling Module) on TI K3 SoCs.
Mario Six1a9d43f2018-10-04 09:00:55 +0200665
Eugen Hristev3bd56102019-10-09 09:23:39 +0000666config MICROCHIP_FLEXCOM
667 bool "Enable Microchip Flexcom driver"
668 depends on MISC
669 help
670 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
671 an I2C controller and an USART.
672 Only one function can be used at a time and is chosen at boot time
673 according to the device tree.
674
Tero Kristo887dde52019-10-24 15:00:46 +0530675config K3_AVS0
676 depends on ARCH_K3 && SPL_DM_REGULATOR
677 bool "AVS class 0 support for K3 devices"
678 help
679 K3 devices have the optimized voltage values for the main voltage
680 domains stored in efuse within the VTM IP. This driver reads the
681 optimized voltage from the efuse, so that it can be programmed
682 to the PMIC on board.
683
Tero Kristo1444e112020-02-14 11:18:16 +0200684config ESM_PMIC
685 bool "Enable PMIC ESM driver"
686 depends on DM_PMIC
687 help
688 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
689 typically to reboot the board in error condition.
690
Tom Rini05b419e2021-12-11 14:55:49 -0500691config FSL_IFC
692 bool
693
Michael Walle2184cc62022-02-25 18:06:24 +0530694config SL28CPLD
695 bool "Enable Kontron sl28cpld multi-function driver"
696 depends on DM_I2C
697 help
698 Support for the Kontron sl28cpld management controller. This is
699 the base driver which provides common access methods for the
700 sub-drivers.
701
Wan Yee Laue249d542024-02-05 11:47:16 +0800702config SPL_SOCFPGA_DT_REG
703 bool "Enable register setting from device tree in SPL"
704 depends on SPL
705 help
706 Enable register setting from device tree. This also
707 provides user a clean interface and all register settings are
708 centralized in one place, device tree.
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900709endmenu