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Siva Durga Prasad Paladugu650fb402015-06-10 15:50:57 +05301if ARCH_ZYNQMP
2
Michal Simek04b7e622015-01-15 10:01:51 +01003config SYS_BOARD
Liam Beguindda9e212021-10-20 11:25:18 -04004 string "Board name"
Michal Simek04b7e622015-01-15 10:01:51 +01005 default "zynqmp"
6
7config SYS_VENDOR
Mike Looijmans61d245c2017-01-03 09:47:52 +01008 string "Vendor name"
Michal Simek04b7e622015-01-15 10:01:51 +01009 default "xilinx"
10
11config SYS_SOC
12 default "zynqmp"
13
Siva Durga Prasad Paladugu4628c502017-07-13 19:01:11 +053014config SYS_MEM_RSVD_FOR_MMU
15 bool "Reserve memory for MMU Table"
16 help
17 If defined this option is used to setup different space for
18 MMU table than the one which will be allocated during
19 relocation.
20
Mike Looijmans96e706f2016-09-20 11:37:24 +020021config BOOT_INIT_FILE
22 string "boot.bin init register filename"
Michal Simek5d359092016-12-16 13:00:26 +010023 depends on SPL
Mike Looijmans96e706f2016-09-20 11:37:24 +020024 default ""
25 help
26 Add register writes to boot.bin format (max 256 pairs).
27 Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
28
Michal Simekdde5a882016-10-21 12:58:17 +020029config PMUFW_INIT_FILE
30 string "PMU firmware"
31 depends on SPL
32 default ""
33 help
34 Include external PMUFW (Platform Management Unit FirmWare) to
35 a Xilinx bootable image (boot.bin).
36
Luca Ceresoli23e65002019-05-21 18:06:43 +020037config ZYNQMP_SPL_PM_CFG_OBJ_FILE
38 string "PMU firmware configuration object to load at runtime by SPL"
39 depends on SPL
40 help
41 Path to a binary PMU firmware configuration object to be linked
42 into U-Boot SPL and loaded at runtime into the PMU firmware.
43
44 The ZynqMP Power Management Unit (PMU) needs a configuration
45 object for most SoC peripherals to work. To have it loaded by
46 U-Boot SPL set here the file name (absolute path or relative to
47 the top source tree) of your configuration, which must be a
48 binary blob. It will be linked in the SPL binary and loaded
49 into the PMU firmware by U-Boot SPL during board
50 initialization.
51
52 Leave this option empty if your PMU firmware has a hard-coded
53 configuration object or you are loading it by any other means.
54
Siva Durga Prasad Paladugucafb6312018-01-12 15:35:46 +053055config ZYNQMP_NO_DDR
56 bool "Disable DDR MMU mapping"
57 help
58 This option configures MMU with no DDR to avoid speculative
59 access to DDR memory where DDR is not present.
60
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020061config SPL_ZYNQMP_DRAM_ECC_INIT
62 bool "Initialize DRAM ECC"
63 depends on SPL
64 help
65 This option initializes all memory to 0xdeadbeef. Must be set if your
66 memory is of ECC type.
67
68config SPL_ZYNQMP_DRAM_BANK1_BASE
69 depends on SPL_ZYNQMP_DRAM_ECC_INIT
70 hex "DRAM Bank1 address"
Michal Simek70597f82023-10-26 08:34:31 +020071 default 0x00000000
72 help
73 Start address of DRAM ECC bank1
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020074
75config SPL_ZYNQMP_DRAM_BANK1_LEN
76 depends on SPL_ZYNQMP_DRAM_ECC_INIT
77 hex "DRAM Bank1 size"
Michal Simek70597f82023-10-26 08:34:31 +020078 default 0x80000000
79 help
80 Size in bytes of the DRAM ECC bank1
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020081
82config SPL_ZYNQMP_DRAM_BANK2_BASE
83 depends on SPL_ZYNQMP_DRAM_ECC_INIT
84 hex "DRAM Bank2 address"
Michal Simek70597f82023-10-26 08:34:31 +020085 default 0x800000000
86 help
87 Start address of DRAM ECC bank2
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020088
89config SPL_ZYNQMP_DRAM_BANK2_LEN
90 depends on SPL_ZYNQMP_DRAM_ECC_INIT
91 hex "DRAM Bank2 size"
Michal Simek70597f82023-10-26 08:34:31 +020092 default 0x0
93 help
94 Size in bytes of the DRAM ECC bank2. A null size takes no action.
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020095
Siva Durga Prasad Paladugu9ed4e812017-07-13 19:01:10 +053096config DEFINE_TCM_OCM_MMAP
97 bool "Define TCM and OCM memory in MMU Table"
Siva Durga Prasad Paladuguc3dfac92017-08-01 16:24:50 +053098 default y if MP
Siva Durga Prasad Paladugu9ed4e812017-07-13 19:01:10 +053099 help
100 This option if enabled defines the TCM and OCM memory and its
101 memory attributes in MMU table entry.
102
Michal Simekd8218792017-07-12 13:21:27 +0200103config ZYNQMP_PSU_INIT_ENABLED
104 bool "Include psu_init"
Michal Simekba6fb832022-02-17 14:28:40 +0100105 select BOARD_EARLY_INIT_F
Michal Simekd8218792017-07-12 13:21:27 +0200106 help
Michal Simek461b9312022-12-02 09:18:06 +0100107 Include psu_init to full u-boot.
108
109config SPL_ZYNQMP_PSU_INIT_ENABLED
110 bool "Include psu_init in SPL"
Michal Simek1bae5ec2024-03-12 16:51:21 +0100111 depends on SPL
112 default y
Michal Simek461b9312022-12-02 09:18:06 +0100113 select BOARD_EARLY_INIT_F
114 help
115 Include psu_init by default in SPL.
Michal Simekd8218792017-07-12 13:21:27 +0200116
Michal Simek94ddcaa2016-08-30 16:17:27 +0200117config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
118 bool "Overwrite SPL bootmode"
119 depends on SPL
120 help
121 Overwrite bootmode selected via boot mode pins to tell SPL what should
122 be the next boot device.
123
Jorge Ramirez-Ortiz34deca52021-10-13 15:48:00 +0200124config SPL_ZYNQMP_RESTORE_JTAG
125 bool "Restore JTAG"
126 depends on SPL
127 help
128 Booting SPL in secure mode causes the CSU to disable the JTAG interface
129 even if no eFuses were burnt. This option restores the interface if
130 possible.
131
Michal Simeke62fabd2024-11-01 10:17:57 +0100132config BL31_LOAD_ADDR
133 hex "Load address of BL31 image (mostly TF-A)"
134 default 0xfffea000
135 help
136 The load address for the BL31 image. This value is used to build the
137 FIT image header that places BL31 in memory where it will run.
138
139config BL32_LOAD_ADDR
140 hex "Load address of BL32 image (mostly secure OS)"
141 default 0
142 help
143 The load address for the BL32 image. This value is used to build the
144 FIT image header that places BL32 in memory where it will run.
145
Vipul Kumar62548002018-02-28 15:53:28 +0530146config ZYNQ_SDHCI_MAX_FREQ
147 default 200000000
148
Michal Simek94ddcaa2016-08-30 16:17:27 +0200149config SPL_ZYNQMP_ALT_BOOTMODE
150 hex
151 default 0x0 if JTAG_MODE
152 default 0x1 if QSPI_MODE_24BIT
153 default 0x2 if QSPI_MODE_32BIT
154 default 0x3 if SD_MODE
155 default 0x4 if NAND_MODE
156 default 0x5 if SD_MODE1
157 default 0x6 if EMMC_MODE
158 default 0x7 if USB_MODE
Michal Simek2740d372016-10-26 09:24:32 +0200159 default 0xa if SW_USBHOST_MODE
160 default 0xb if SW_SATA_MODE
Michal Simeke1c4d392017-02-15 09:41:53 +0100161 default 0xe if SD1_LSHFT_MODE
Michal Simek94ddcaa2016-08-30 16:17:27 +0200162
163choice
164 prompt "Boot mode"
Michal Simek8ffddc32016-08-30 16:17:27 +0200165 depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
Ulf Magnusson3e3b16a2018-01-30 14:02:01 +0100166 default JTAG_MODE
Michal Simek94ddcaa2016-08-30 16:17:27 +0200167
168config JTAG_MODE
169 bool "JTAG_MODE"
170
171config QSPI_MODE_24BIT
172 bool "QSPI_MODE_24BIT"
173
174config QSPI_MODE_32BIT
175 bool "QSPI_MODE_32BIT"
176
177config SD_MODE
178 bool "SD_MODE"
179
180config SD_MODE1
181 bool "SD_MODE1"
182
183config NAND_MODE
184 bool "NAND_MODE"
185
186config EMMC_MODE
187 bool "EMMC_MODE"
188
189config USB_MODE
190 bool "USB"
191
Michal Simek2740d372016-10-26 09:24:32 +0200192config SW_USBHOST_MODE
193 bool "SW USBHOST_MODE"
194
195config SW_SATA_MODE
196 bool "SW SATA_MODE"
197
Michal Simeke1c4d392017-02-15 09:41:53 +0100198config SD1_LSHFT_MODE
199 bool "SD1_LSHFT_MODE"
200
Michal Simek94ddcaa2016-08-30 16:17:27 +0200201endchoice
Simon Glasscb3e4892016-07-05 17:10:13 -0600202
Charlie Johnstonb864c2e2024-04-10 12:50:08 -0700203config CMD_ZYNQMP
204 bool "Enable ZynqMP specific commands"
205 depends on ZYNQMP_FIRMWARE
206 default y
207 help
208 Enable ZynqMP specific commands like "zynqmp secure"
209 which is used for zynqmp secure image verification.
210 The secure image is a xilinx specific BOOT.BIN with
211 either authentication or encryption or both encryption
212 and authentication feature enabled while generating
213 BOOT.BIN using Xilinx bootgen tool.
214
Michal Simek5f884852020-08-27 15:34:11 +0200215source "board/xilinx/Kconfig"
Michal Simek5f884852020-08-27 15:34:11 +0200216
Michal Simek04b7e622015-01-15 10:01:51 +0100217endif