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Siva Durga Prasad Paladugu650fb402015-06-10 15:50:57 +05301if ARCH_ZYNQMP
2
Michal Simek04b7e622015-01-15 10:01:51 +01003config SYS_BOARD
Liam Beguindda9e212021-10-20 11:25:18 -04004 string "Board name"
Michal Simek04b7e622015-01-15 10:01:51 +01005 default "zynqmp"
6
7config SYS_VENDOR
Mike Looijmans61d245c2017-01-03 09:47:52 +01008 string "Vendor name"
Michal Simek04b7e622015-01-15 10:01:51 +01009 default "xilinx"
10
11config SYS_SOC
12 default "zynqmp"
13
Siva Durga Prasad Paladugu4628c502017-07-13 19:01:11 +053014config SYS_MEM_RSVD_FOR_MMU
15 bool "Reserve memory for MMU Table"
16 help
17 If defined this option is used to setup different space for
18 MMU table than the one which will be allocated during
19 relocation.
20
Mike Looijmans96e706f2016-09-20 11:37:24 +020021config BOOT_INIT_FILE
22 string "boot.bin init register filename"
Michal Simek5d359092016-12-16 13:00:26 +010023 depends on SPL
Mike Looijmans96e706f2016-09-20 11:37:24 +020024 default ""
25 help
26 Add register writes to boot.bin format (max 256 pairs).
27 Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
28
Michal Simekdde5a882016-10-21 12:58:17 +020029config PMUFW_INIT_FILE
30 string "PMU firmware"
31 depends on SPL
32 default ""
33 help
34 Include external PMUFW (Platform Management Unit FirmWare) to
35 a Xilinx bootable image (boot.bin).
36
Luca Ceresoli23e65002019-05-21 18:06:43 +020037config ZYNQMP_SPL_PM_CFG_OBJ_FILE
38 string "PMU firmware configuration object to load at runtime by SPL"
39 depends on SPL
40 help
41 Path to a binary PMU firmware configuration object to be linked
42 into U-Boot SPL and loaded at runtime into the PMU firmware.
43
44 The ZynqMP Power Management Unit (PMU) needs a configuration
45 object for most SoC peripherals to work. To have it loaded by
46 U-Boot SPL set here the file name (absolute path or relative to
47 the top source tree) of your configuration, which must be a
48 binary blob. It will be linked in the SPL binary and loaded
49 into the PMU firmware by U-Boot SPL during board
50 initialization.
51
52 Leave this option empty if your PMU firmware has a hard-coded
53 configuration object or you are loading it by any other means.
54
Siva Durga Prasad Paladugucafb6312018-01-12 15:35:46 +053055config ZYNQMP_NO_DDR
56 bool "Disable DDR MMU mapping"
57 help
58 This option configures MMU with no DDR to avoid speculative
59 access to DDR memory where DDR is not present.
60
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020061config SPL_ZYNQMP_DRAM_ECC_INIT
62 bool "Initialize DRAM ECC"
63 depends on SPL
64 help
65 This option initializes all memory to 0xdeadbeef. Must be set if your
66 memory is of ECC type.
67
68config SPL_ZYNQMP_DRAM_BANK1_BASE
69 depends on SPL_ZYNQMP_DRAM_ECC_INIT
70 hex "DRAM Bank1 address"
Michal Simek70597f82023-10-26 08:34:31 +020071 default 0x00000000
72 help
73 Start address of DRAM ECC bank1
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020074
75config SPL_ZYNQMP_DRAM_BANK1_LEN
76 depends on SPL_ZYNQMP_DRAM_ECC_INIT
77 hex "DRAM Bank1 size"
Michal Simek70597f82023-10-26 08:34:31 +020078 default 0x80000000
79 help
80 Size in bytes of the DRAM ECC bank1
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020081
82config SPL_ZYNQMP_DRAM_BANK2_BASE
83 depends on SPL_ZYNQMP_DRAM_ECC_INIT
84 hex "DRAM Bank2 address"
Michal Simek70597f82023-10-26 08:34:31 +020085 default 0x800000000
86 help
87 Start address of DRAM ECC bank2
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020088
89config SPL_ZYNQMP_DRAM_BANK2_LEN
90 depends on SPL_ZYNQMP_DRAM_ECC_INIT
91 hex "DRAM Bank2 size"
Michal Simek70597f82023-10-26 08:34:31 +020092 default 0x0
93 help
94 Size in bytes of the DRAM ECC bank2. A null size takes no action.
Jorge Ramirez-Ortiz35456962021-06-13 20:55:53 +020095
Simon Glasscb3e4892016-07-05 17:10:13 -060096config SYS_MALLOC_F_LEN
97 default 0x600
98
Siva Durga Prasad Paladugu9ed4e812017-07-13 19:01:10 +053099config DEFINE_TCM_OCM_MMAP
100 bool "Define TCM and OCM memory in MMU Table"
Siva Durga Prasad Paladuguc3dfac92017-08-01 16:24:50 +0530101 default y if MP
Siva Durga Prasad Paladugu9ed4e812017-07-13 19:01:10 +0530102 help
103 This option if enabled defines the TCM and OCM memory and its
104 memory attributes in MMU table entry.
105
Michal Simekd8218792017-07-12 13:21:27 +0200106config ZYNQMP_PSU_INIT_ENABLED
107 bool "Include psu_init"
Michal Simekba6fb832022-02-17 14:28:40 +0100108 select BOARD_EARLY_INIT_F
Michal Simekd8218792017-07-12 13:21:27 +0200109 help
Michal Simek461b9312022-12-02 09:18:06 +0100110 Include psu_init to full u-boot.
111
112config SPL_ZYNQMP_PSU_INIT_ENABLED
113 bool "Include psu_init in SPL"
Michal Simek1bae5ec2024-03-12 16:51:21 +0100114 depends on SPL
115 default y
Michal Simek461b9312022-12-02 09:18:06 +0100116 select BOARD_EARLY_INIT_F
117 help
118 Include psu_init by default in SPL.
Michal Simekd8218792017-07-12 13:21:27 +0200119
Michal Simek94ddcaa2016-08-30 16:17:27 +0200120config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
121 bool "Overwrite SPL bootmode"
122 depends on SPL
123 help
124 Overwrite bootmode selected via boot mode pins to tell SPL what should
125 be the next boot device.
126
Jorge Ramirez-Ortiz34deca52021-10-13 15:48:00 +0200127config SPL_ZYNQMP_RESTORE_JTAG
128 bool "Restore JTAG"
129 depends on SPL
130 help
131 Booting SPL in secure mode causes the CSU to disable the JTAG interface
132 even if no eFuses were burnt. This option restores the interface if
133 possible.
134
Michal Simeke62fabd2024-11-01 10:17:57 +0100135config BL31_LOAD_ADDR
136 hex "Load address of BL31 image (mostly TF-A)"
137 default 0xfffea000
138 help
139 The load address for the BL31 image. This value is used to build the
140 FIT image header that places BL31 in memory where it will run.
141
142config BL32_LOAD_ADDR
143 hex "Load address of BL32 image (mostly secure OS)"
144 default 0
145 help
146 The load address for the BL32 image. This value is used to build the
147 FIT image header that places BL32 in memory where it will run.
148
Vipul Kumar62548002018-02-28 15:53:28 +0530149config ZYNQ_SDHCI_MAX_FREQ
150 default 200000000
151
Michal Simek94ddcaa2016-08-30 16:17:27 +0200152config SPL_ZYNQMP_ALT_BOOTMODE
153 hex
154 default 0x0 if JTAG_MODE
155 default 0x1 if QSPI_MODE_24BIT
156 default 0x2 if QSPI_MODE_32BIT
157 default 0x3 if SD_MODE
158 default 0x4 if NAND_MODE
159 default 0x5 if SD_MODE1
160 default 0x6 if EMMC_MODE
161 default 0x7 if USB_MODE
Michal Simek2740d372016-10-26 09:24:32 +0200162 default 0xa if SW_USBHOST_MODE
163 default 0xb if SW_SATA_MODE
Michal Simeke1c4d392017-02-15 09:41:53 +0100164 default 0xe if SD1_LSHFT_MODE
Michal Simek94ddcaa2016-08-30 16:17:27 +0200165
166choice
167 prompt "Boot mode"
Michal Simek8ffddc32016-08-30 16:17:27 +0200168 depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
Ulf Magnusson3e3b16a2018-01-30 14:02:01 +0100169 default JTAG_MODE
Michal Simek94ddcaa2016-08-30 16:17:27 +0200170
171config JTAG_MODE
172 bool "JTAG_MODE"
173
174config QSPI_MODE_24BIT
175 bool "QSPI_MODE_24BIT"
176
177config QSPI_MODE_32BIT
178 bool "QSPI_MODE_32BIT"
179
180config SD_MODE
181 bool "SD_MODE"
182
183config SD_MODE1
184 bool "SD_MODE1"
185
186config NAND_MODE
187 bool "NAND_MODE"
188
189config EMMC_MODE
190 bool "EMMC_MODE"
191
192config USB_MODE
193 bool "USB"
194
Michal Simek2740d372016-10-26 09:24:32 +0200195config SW_USBHOST_MODE
196 bool "SW USBHOST_MODE"
197
198config SW_SATA_MODE
199 bool "SW SATA_MODE"
200
Michal Simeke1c4d392017-02-15 09:41:53 +0100201config SD1_LSHFT_MODE
202 bool "SD1_LSHFT_MODE"
203
Michal Simek94ddcaa2016-08-30 16:17:27 +0200204endchoice
Simon Glasscb3e4892016-07-05 17:10:13 -0600205
Charlie Johnstonb864c2e2024-04-10 12:50:08 -0700206config CMD_ZYNQMP
207 bool "Enable ZynqMP specific commands"
208 depends on ZYNQMP_FIRMWARE
209 default y
210 help
211 Enable ZynqMP specific commands like "zynqmp secure"
212 which is used for zynqmp secure image verification.
213 The secure image is a xilinx specific BOOT.BIN with
214 either authentication or encryption or both encryption
215 and authentication feature enabled while generating
216 BOOT.BIN using Xilinx bootgen tool.
217
Michal Simek5f884852020-08-27 15:34:11 +0200218source "board/xilinx/Kconfig"
Michal Simek5f884852020-08-27 15:34:11 +0200219
Michal Simek04b7e622015-01-15 10:01:51 +0100220endif