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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / arch / arm / dts / rk3399-u-boot.dtsi
blob: 587eef9504eccc7a1ea365b5f8aed24756692dcb [file] [log] [blame]
Jagan Teki208badd2019-03-11 13:50:03 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
4 */
Simon Glass8251e032020-07-19 13:55:58 -0600[diff] [blame]5#include "rockchip-u-boot.dtsi"
6
Peter Robinson94fb4c42020-01-20 09:17:00 +0000[diff] [blame]7/ {
8 aliases {
9 mmc0 = &sdhci;
10 mmc1 = &sdmmc;
Jagan Teki77c31a82020-05-09 22:26:23 +0530[diff] [blame]11 pci0 = &pcie0;
Simon Glass8251e032020-07-19 13:55:58 -0600[diff] [blame]12 spi1 = &spi1;
Peter Robinson94fb4c42020-01-20 09:17:00 +0000[diff] [blame]13 };
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]14
Jonas Karlman747c9572024-04-30 15:30:18 +0000[diff] [blame]15 chosen {
16 u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
17 };
18
Jonas Karlman47f7e5f2024-04-30 15:30:20 +0000[diff] [blame]19 pmusgrf: syscon@ff330000 {
20 compatible = "rockchip,rk3399-pmusgrf", "syscon";
21 reg = <0x0 0xff330000 0x0 0xe3d4>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-all;
Jonas Karlman47f7e5f2024-04-30 15:30:20 +0000[diff] [blame]23 };
24
25 cic: syscon@ff620000 {
Peter Robinson94fb4c42020-01-20 09:17:00 +0000[diff] [blame]26 compatible = "rockchip,rk3399-cic", "syscon";
27 reg = <0x0 0xff620000 0x0 0x100>;
Jonas Karlman47f7e5f2024-04-30 15:30:20 +0000[diff] [blame]28 bootph-all;
Peter Robinson94fb4c42020-01-20 09:17:00 +0000[diff] [blame]29 };
Simon Glass8251e032020-07-19 13:55:58 -0600[diff] [blame]30};
31
Peter Robinson94fb4c42020-01-20 09:17:00 +0000[diff] [blame]32&cru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-all;
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]34};
35
Jonas Karlmane872ddc2024-05-01 16:22:22 +0000[diff] [blame]36&dfi {
37 bootph-all;
38};
39
40&dmc {
41 reg = <0x0 0xffa80000 0x0 0x0800
42 0x0 0xffa80800 0x0 0x1800
43 0x0 0xffa82000 0x0 0x2000
44 0x0 0xffa84000 0x0 0x1000
45 0x0 0xffa88000 0x0 0x0800
46 0x0 0xffa88800 0x0 0x1800
47 0x0 0xffa8a000 0x0 0x2000
48 0x0 0xffa8c000 0x0 0x1000>;
49 bootph-all;
50 status = "okay";
51};
52
Yifeng Zhaod7e4c322021-11-01 12:43:47 +0800[diff] [blame]53&emmc_phy {
Jonas Karlman6a6b4f52024-04-30 15:30:24 +0000[diff] [blame]54 bootph-pre-ram;
55 bootph-some-ram;
Yifeng Zhaod7e4c322021-11-01 12:43:47 +0800[diff] [blame]56};
57
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]58&grf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-all;
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]60};
61
Jonas Karlman6a6b4f52024-04-30 15:30:24 +0000[diff] [blame]62&pcfg_pull_none {
63 bootph-all;
64};
65
66&pcfg_pull_up {
67 bootph-all;
68};
69
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]70&pinctrl {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-all;
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]72};
73
Jagan Teki9b545852019-07-16 17:27:34 +0530[diff] [blame]74&pmu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-all;
Jagan Teki9b545852019-07-16 17:27:34 +0530[diff] [blame]76};
77
Jonas Karlman47f7e5f2024-04-30 15:30:20 +0000[diff] [blame]78&pmucru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-all;
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]80};
81
Jonas Karlman47f7e5f2024-04-30 15:30:20 +0000[diff] [blame]82&pmugrf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-all;
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]84};
85
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]86&sdhci {
Jonas Karlman6a6b4f52024-04-30 15:30:24 +0000[diff] [blame]87 bootph-pre-ram;
88 bootph-some-ram;
Jonas Karlman47f7e5f2024-04-30 15:30:20 +0000[diff] [blame]89 max-frequency = <200000000>;
90
91 /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
Jonas Karlmanf79c5372023-05-06 17:41:11 +0000[diff] [blame]92 u-boot,spl-fifo-mode;
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]93};
94
Jagan Teki208badd2019-03-11 13:50:03 +0530[diff] [blame]95&sdmmc {
Jonas Karlman6a6b4f52024-04-30 15:30:24 +0000[diff] [blame]96 bootph-pre-ram;
97 bootph-some-ram;
Deepak Das4ef2ded2020-04-15 08:55:24 +0530[diff] [blame]98
99 /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
100 u-boot,spl-fifo-mode;
Jagan Teki208badd2019-03-11 13:50:03 +0530[diff] [blame]101};
Jagan Teki60c5fed2019-05-07 23:51:51 +0530[diff] [blame]102
Jonas Karlman6a6b4f52024-04-30 15:30:24 +0000[diff] [blame]103&sdmmc_bus4 {
104 bootph-pre-ram;
105 bootph-some-ram;
106};
107
108&sdmmc_cd {
109 bootph-pre-ram;
110 bootph-some-ram;
111};
112
113&sdmmc_clk {
114 bootph-pre-ram;
115 bootph-some-ram;
116};
117
118&sdmmc_cmd {
119 bootph-pre-ram;
120 bootph-some-ram;
121};
122
Quentin Schulz419beef2024-06-17 15:10:08 +0200[diff] [blame]123&spi1 {
124 bootph-pre-ram;
125 bootph-some-ram;
126};
127
Jonas Karlman6a6b4f52024-04-30 15:30:24 +0000[diff] [blame]128&spi1_clk {
129 bootph-pre-ram;
130 bootph-some-ram;
131};
132
133&spi1_cs0 {
134 bootph-pre-ram;
135 bootph-some-ram;
136};
137
138&spi1_rx {
139 bootph-pre-ram;
140 bootph-some-ram;
141};
142
143&spi1_tx {
144 bootph-pre-ram;
145 bootph-some-ram;
Jagan Teki60c5fed2019-05-07 23:51:51 +0530[diff] [blame]146};
Jagan Teki2ff51fd2019-06-21 00:25:02 +0530[diff] [blame]147
Jagan Teki2ff51fd2019-06-21 00:25:02 +0530[diff] [blame]148&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]149 bootph-all;
Jonas Karlmanfab0bd32024-04-30 15:30:23 +0000[diff] [blame]150 clock-frequency = <24000000>;
151};
152
153&uart2c_xfer {
154 bootph-pre-sram;
155 bootph-pre-ram;
Jagan Teki2ff51fd2019-06-21 00:25:02 +0530[diff] [blame]156};
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]157
158&vopb {
Jonas Karlman98519912024-04-30 15:30:21 +0000[diff] [blame]159 bootph-some-ram;
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]160};
161
162&vopl {
Jonas Karlman98519912024-04-30 15:30:21 +0000[diff] [blame]163 bootph-some-ram;
Peter Robinsondd44a152019-11-09 20:30:05 +0000[diff] [blame]164};
Jonas Karlmane872ddc2024-05-01 16:22:22 +0000[diff] [blame]165
166&xin24m {
167 bootph-all;
168};