blob: d283ef6275abb06cac0a4986c9cf51c17159ebaa [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chander Kashyap0d2f2772013-08-21 10:38:56 +05302/*
3 * Copyright (C) 2013 Samsung Electronics
Chander Kashyap0d2f2772013-08-21 10:38:56 +05304 */
5
6#include <common.h>
Simon Glass370382c2019-11-14 12:57:35 -07007#include <cpu_func.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -07008#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Inderpal Singh3260bc82014-01-08 09:19:57 +053010#include <usb.h>
Simon Glass37f11622014-10-20 19:48:37 -060011#include <asm/gpio.h>
Chander Kashyap0d2f2772013-08-21 10:38:56 +053012#include <asm/arch/pinmux.h>
Inderpal Singh04bb7372013-08-21 10:38:57 +053013#include <asm/arch/dwmmc.h>
Chander Kashyap0d2f2772013-08-21 10:38:56 +053014#include <asm/arch/power.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
Inderpal Singh3260bc82014-01-08 09:19:57 +053018#ifdef CONFIG_USB_EHCI_EXYNOS
19int board_usb_init(int index, enum usb_init_type init)
20{
Inderpal Singh3260bc82014-01-08 09:19:57 +053021 /* Configure gpios for usb 3503 hub:
22 * disconnect, toggle reset and connect
23 */
Simon Glass4f83d3d2014-10-20 19:48:39 -060024 gpio_request(EXYNOS5_GPIO_D17, "usb_connect");
25 gpio_request(EXYNOS5_GPIO_X35, "usb_reset");
Akshay Saraswat1376cdd2014-05-13 10:30:14 +053026 gpio_direction_output(EXYNOS5_GPIO_D17, 0);
27 gpio_direction_output(EXYNOS5_GPIO_X35, 0);
Inderpal Singh3260bc82014-01-08 09:19:57 +053028
Akshay Saraswat1376cdd2014-05-13 10:30:14 +053029 gpio_direction_output(EXYNOS5_GPIO_X35, 1);
30 gpio_direction_output(EXYNOS5_GPIO_D17, 1);
Inderpal Singh3260bc82014-01-08 09:19:57 +053031
32 return 0;
33}
34#endif
35
Chander Kashyap0d2f2772013-08-21 10:38:56 +053036int board_init(void)
37{
38 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
39 return 0;
40}
41
42int dram_init(void)
43{
44 int i;
45 u32 addr;
46
47 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
48 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
49 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
50 }
51 return 0;
52}
53
54int power_init_board(void)
55{
56 set_ps_hold_ctrl();
57 return 0;
58}
59
Simon Glass2f949c32017-03-31 08:40:32 -060060int dram_init_banksize(void)
Chander Kashyap0d2f2772013-08-21 10:38:56 +053061{
62 int i;
63 u32 addr, size;
64
65 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
66 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
67 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
68
69 gd->bd->bi_dram[i].start = addr;
70 gd->bd->bi_dram[i].size = size;
71 }
Simon Glass2f949c32017-03-31 08:40:32 -060072
73 return 0;
Chander Kashyap0d2f2772013-08-21 10:38:56 +053074}
75
Chander Kashyap0d2f2772013-08-21 10:38:56 +053076static int board_uart_init(void)
77{
78 int err = 0, uart_id;
79
80 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
81 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
82 if (err) {
83 debug("UART%d not configured\n",
84 (uart_id - PERIPH_ID_UART0));
85 return err;
86 }
87 }
88 return err;
89}
90
91#ifdef CONFIG_BOARD_EARLY_INIT_F
92int board_early_init_f(void)
93{
94 int err;
95
96 err = board_uart_init();
97 if (err) {
98 debug("UART init failed\n");
99 return err;
100 }
101 return err;
102}
103#endif
104
105#ifdef CONFIG_DISPLAY_BOARDINFO
106int checkboard(void)
107{
108 printf("\nBoard: Arndale\n");
109
110 return 0;
111}
112#endif
Andre Przywara64d4c222014-08-01 13:35:44 +0200113
114#ifdef CONFIG_S5P_PA_SYSRAM
115void smp_set_core_boot_addr(unsigned long addr, int corenr)
116{
117 writel(addr, CONFIG_S5P_PA_SYSRAM);
118
119 /* make sure this write is really executed */
120 __asm__ volatile ("dsb\n");
121}
122#endif