wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 1 | /* |
Graeme Russ | 45fc1d8 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 2 | * (C) Copyright 2008-2011 |
| 3 | * Graeme Russ, <graeme.russ@gmail.com> |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 4 | * |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 5 | * (C) Copyright 2002 |
Albert ARIBAUD | 60fbc8d | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 6 | * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 7 | * |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 8 | * Portions of this file are derived from the Linux kernel source |
| 9 | * Copyright (C) 1991, 1992 Linus Torvalds |
| 10 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 11 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #include <common.h> |
Stefan Reinauer | 2acf848 | 2012-12-02 04:49:50 +0000 | [diff] [blame] | 15 | #include <asm/cache.h> |
| 16 | #include <asm/control_regs.h> |
Graeme Russ | 0c8c62e | 2008-12-07 10:29:01 +1100 | [diff] [blame] | 17 | #include <asm/interrupt.h> |
Graeme Russ | 6869980 | 2011-02-12 15:11:28 +1100 | [diff] [blame] | 18 | #include <asm/io.h> |
Graeme Russ | 93efcb2 | 2011-02-12 15:11:32 +1100 | [diff] [blame] | 19 | #include <asm/processor-flags.h> |
Graeme Russ | fdee8b1 | 2011-11-08 02:33:13 +0000 | [diff] [blame] | 20 | #include <linux/compiler.h> |
Vadim Bendebury | 6ab0258 | 2012-12-03 13:59:20 +0000 | [diff] [blame] | 21 | #include <asm/msr.h> |
| 22 | #include <asm/u-boot-x86.h> |
Bin Meng | cb9d9cb | 2014-11-20 16:11:16 +0800 | [diff] [blame] | 23 | #include <asm/i8259.h> |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 24 | |
Simon Glass | bb6306c | 2013-04-17 16:13:33 +0000 | [diff] [blame] | 25 | DECLARE_GLOBAL_DATA_PTR; |
| 26 | |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 27 | #define DECLARE_INTERRUPT(x) \ |
| 28 | ".globl irq_"#x"\n" \ |
Graeme Russ | 1aafcc9 | 2009-11-24 20:04:19 +1100 | [diff] [blame] | 29 | ".hidden irq_"#x"\n" \ |
| 30 | ".type irq_"#x", @function\n" \ |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 31 | "irq_"#x":\n" \ |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 32 | "pushl $"#x"\n" \ |
| 33 | "jmp irq_common_entry\n" |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 34 | |
Simon Glass | 8337433 | 2014-11-06 13:20:08 -0700 | [diff] [blame] | 35 | static void dump_regs(struct irq_regs *regs) |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 36 | { |
| 37 | unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; |
| 38 | unsigned long d0, d1, d2, d3, d6, d7; |
Graeme Russ | 6869980 | 2011-02-12 15:11:28 +1100 | [diff] [blame] | 39 | unsigned long sp; |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 40 | |
| 41 | printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n", |
| 42 | (u16)regs->xcs, regs->eip, regs->eflags); |
| 43 | |
| 44 | printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n", |
| 45 | regs->eax, regs->ebx, regs->ecx, regs->edx); |
| 46 | printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n", |
| 47 | regs->esi, regs->edi, regs->ebp, regs->esp); |
| 48 | printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n", |
Graeme Russ | fdee8b1 | 2011-11-08 02:33:13 +0000 | [diff] [blame] | 49 | (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, |
| 50 | (u16)regs->xgs, (u16)regs->xss); |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 51 | |
| 52 | cr0 = read_cr0(); |
| 53 | cr2 = read_cr2(); |
| 54 | cr3 = read_cr3(); |
| 55 | cr4 = read_cr4(); |
| 56 | |
| 57 | printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n", |
| 58 | cr0, cr2, cr3, cr4); |
| 59 | |
| 60 | d0 = get_debugreg(0); |
| 61 | d1 = get_debugreg(1); |
| 62 | d2 = get_debugreg(2); |
| 63 | d3 = get_debugreg(3); |
| 64 | |
| 65 | printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n", |
| 66 | d0, d1, d2, d3); |
| 67 | |
| 68 | d6 = get_debugreg(6); |
| 69 | d7 = get_debugreg(7); |
| 70 | printf("DR6: %08lx DR7: %08lx\n", |
| 71 | d6, d7); |
Graeme Russ | 6869980 | 2011-02-12 15:11:28 +1100 | [diff] [blame] | 72 | |
| 73 | printf("Stack:\n"); |
| 74 | sp = regs->esp; |
| 75 | |
| 76 | sp += 64; |
| 77 | |
| 78 | while (sp > (regs->esp - 16)) { |
| 79 | if (sp == regs->esp) |
| 80 | printf("--->"); |
| 81 | else |
| 82 | printf(" "); |
| 83 | printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp)); |
| 84 | sp -= 4; |
| 85 | } |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 86 | } |
| 87 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 88 | struct idt_entry { |
| 89 | u16 base_low; |
| 90 | u16 selector; |
| 91 | u8 res; |
| 92 | u8 access; |
| 93 | u16 base_high; |
Graeme Russ | fdee8b1 | 2011-11-08 02:33:13 +0000 | [diff] [blame] | 94 | } __packed; |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 95 | |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 96 | struct desc_ptr { |
| 97 | unsigned short size; |
| 98 | unsigned long address; |
| 99 | unsigned short segment; |
Graeme Russ | fdee8b1 | 2011-11-08 02:33:13 +0000 | [diff] [blame] | 100 | } __packed; |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 101 | |
Graeme Russ | af3f2c8 | 2011-12-19 14:26:18 +1100 | [diff] [blame] | 102 | struct idt_entry idt[256] __aligned(16); |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 103 | |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 104 | struct desc_ptr idt_ptr; |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 105 | |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 106 | static inline void load_idt(const struct desc_ptr *dtr) |
| 107 | { |
Graeme Russ | fdee8b1 | 2011-11-08 02:33:13 +0000 | [diff] [blame] | 108 | asm volatile("cs lidt %0" : : "m" (*dtr)); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 109 | } |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 110 | |
Graeme Russ | 77290ee | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 111 | void set_vector(u8 intnum, void *routine) |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 112 | { |
Graeme Russ | 078395c | 2009-11-24 20:04:21 +1100 | [diff] [blame] | 113 | idt[intnum].base_high = (u16)((u32)(routine) >> 16); |
| 114 | idt[intnum].base_low = (u16)((u32)(routine) & 0xffff); |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 115 | } |
| 116 | |
Graeme Russ | fdee8b1 | 2011-11-08 02:33:13 +0000 | [diff] [blame] | 117 | /* |
| 118 | * Ideally these would be defined static to avoid a checkpatch warning, but |
| 119 | * the compiler cannot see them in the inline asm and complains that they |
| 120 | * aren't defined |
| 121 | */ |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 122 | void irq_0(void); |
| 123 | void irq_1(void); |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 124 | |
Graeme Russ | 77290ee | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 125 | int cpu_init_interrupts(void) |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 126 | { |
| 127 | int i; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 128 | |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 129 | int irq_entry_size = irq_1 - irq_0; |
| 130 | void *irq_entry = (void *)irq_0; |
| 131 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 132 | /* Setup the IDT */ |
Graeme Russ | fdee8b1 | 2011-11-08 02:33:13 +0000 | [diff] [blame] | 133 | for (i = 0; i < 256; i++) { |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 134 | idt[i].access = 0x8e; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 135 | idt[i].res = 0; |
| 136 | idt[i].selector = 0x10; |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 137 | set_vector(i, irq_entry); |
| 138 | irq_entry += irq_entry_size; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 139 | } |
| 140 | |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 141 | idt_ptr.size = 256 * 8; |
| 142 | idt_ptr.address = (unsigned long) idt; |
| 143 | idt_ptr.segment = 0x18; |
| 144 | |
| 145 | load_idt(&idt_ptr); |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 146 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 147 | return 0; |
| 148 | } |
| 149 | |
Simon Glass | 98d7e98 | 2015-04-28 20:25:16 -0600 | [diff] [blame] | 150 | void *x86_get_idt(void) |
| 151 | { |
| 152 | return &idt_ptr; |
| 153 | } |
| 154 | |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 155 | void __do_irq(int irq) |
| 156 | { |
| 157 | printf("Unhandled IRQ : %d\n", irq); |
| 158 | } |
| 159 | void do_irq(int irq) __attribute__((weak, alias("__do_irq"))); |
| 160 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 161 | void enable_interrupts(void) |
| 162 | { |
| 163 | asm("sti\n"); |
| 164 | } |
| 165 | |
| 166 | int disable_interrupts(void) |
| 167 | { |
| 168 | long flags; |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 169 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 170 | asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : ); |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 171 | |
Graeme Russ | fdee8b1 | 2011-11-08 02:33:13 +0000 | [diff] [blame] | 172 | return flags & X86_EFLAGS_IF; |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 173 | } |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 174 | |
Bin Meng | cb9d9cb | 2014-11-20 16:11:16 +0800 | [diff] [blame] | 175 | int interrupt_init(void) |
| 176 | { |
| 177 | /* Just in case... */ |
| 178 | disable_interrupts(); |
| 179 | |
| 180 | #ifdef CONFIG_SYS_PCAT_INTERRUPTS |
| 181 | /* Initialize the master/slave i8259 pic */ |
| 182 | i8259_init(); |
| 183 | #endif |
| 184 | |
| 185 | /* Initialize core interrupt and exception functionality of CPU */ |
| 186 | cpu_init_interrupts(); |
| 187 | |
| 188 | /* It is now safe to enable interrupts */ |
| 189 | enable_interrupts(); |
| 190 | |
| 191 | return 0; |
| 192 | } |
| 193 | |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 194 | /* IRQ Low-Level Service Routine */ |
Graeme Russ | 4326153 | 2010-10-07 20:03:23 +1100 | [diff] [blame] | 195 | void irq_llsr(struct irq_regs *regs) |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 196 | { |
| 197 | /* |
| 198 | * For detailed description of each exception, refer to: |
Albert ARIBAUD | 60fbc8d | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 199 | * Intel® 64 and IA-32 Architectures Software Developer's Manual |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 200 | * Volume 1: Basic Architecture |
| 201 | * Order Number: 253665-029US, November 2008 |
| 202 | * Table 6-1. Exceptions and Interrupts |
| 203 | */ |
Graeme Russ | 4326153 | 2010-10-07 20:03:23 +1100 | [diff] [blame] | 204 | switch (regs->irq_id) { |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 205 | case 0x00: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 206 | printf("Divide Error (Division by zero)\n"); |
| 207 | dump_regs(regs); |
Graeme Russ | 5e0e287 | 2011-11-08 02:33:12 +0000 | [diff] [blame] | 208 | hang(); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 209 | break; |
| 210 | case 0x01: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 211 | printf("Debug Interrupt (Single step)\n"); |
| 212 | dump_regs(regs); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 213 | break; |
| 214 | case 0x02: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 215 | printf("NMI Interrupt\n"); |
| 216 | dump_regs(regs); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 217 | break; |
| 218 | case 0x03: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 219 | printf("Breakpoint\n"); |
| 220 | dump_regs(regs); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 221 | break; |
| 222 | case 0x04: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 223 | printf("Overflow\n"); |
| 224 | dump_regs(regs); |
Graeme Russ | 5e0e287 | 2011-11-08 02:33:12 +0000 | [diff] [blame] | 225 | hang(); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 226 | break; |
| 227 | case 0x05: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 228 | printf("BOUND Range Exceeded\n"); |
| 229 | dump_regs(regs); |
Graeme Russ | 5e0e287 | 2011-11-08 02:33:12 +0000 | [diff] [blame] | 230 | hang(); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 231 | break; |
| 232 | case 0x06: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 233 | printf("Invalid Opcode (UnDefined Opcode)\n"); |
| 234 | dump_regs(regs); |
Graeme Russ | 5e0e287 | 2011-11-08 02:33:12 +0000 | [diff] [blame] | 235 | hang(); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 236 | break; |
| 237 | case 0x07: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 238 | printf("Device Not Available (No Math Coprocessor)\n"); |
| 239 | dump_regs(regs); |
Graeme Russ | 5e0e287 | 2011-11-08 02:33:12 +0000 | [diff] [blame] | 240 | hang(); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 241 | break; |
| 242 | case 0x08: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 243 | printf("Double fault\n"); |
| 244 | dump_regs(regs); |
Graeme Russ | 5e0e287 | 2011-11-08 02:33:12 +0000 | [diff] [blame] | 245 | hang(); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 246 | break; |
| 247 | case 0x09: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 248 | printf("Co-processor segment overrun\n"); |
| 249 | dump_regs(regs); |
Graeme Russ | 5e0e287 | 2011-11-08 02:33:12 +0000 | [diff] [blame] | 250 | hang(); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 251 | break; |
| 252 | case 0x0a: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 253 | printf("Invalid TSS\n"); |
| 254 | dump_regs(regs); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 255 | break; |
| 256 | case 0x0b: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 257 | printf("Segment Not Present\n"); |
| 258 | dump_regs(regs); |
Graeme Russ | 5e0e287 | 2011-11-08 02:33:12 +0000 | [diff] [blame] | 259 | hang(); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 260 | break; |
| 261 | case 0x0c: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 262 | printf("Stack Segment Fault\n"); |
| 263 | dump_regs(regs); |
Graeme Russ | 5e0e287 | 2011-11-08 02:33:12 +0000 | [diff] [blame] | 264 | hang(); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 265 | break; |
| 266 | case 0x0d: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 267 | printf("General Protection\n"); |
| 268 | dump_regs(regs); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 269 | break; |
| 270 | case 0x0e: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 271 | printf("Page fault\n"); |
| 272 | dump_regs(regs); |
Graeme Russ | 5e0e287 | 2011-11-08 02:33:12 +0000 | [diff] [blame] | 273 | hang(); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 274 | break; |
| 275 | case 0x0f: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 276 | printf("Floating-Point Error (Math Fault)\n"); |
| 277 | dump_regs(regs); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 278 | break; |
| 279 | case 0x10: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 280 | printf("Alignment check\n"); |
| 281 | dump_regs(regs); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 282 | break; |
| 283 | case 0x11: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 284 | printf("Machine Check\n"); |
| 285 | dump_regs(regs); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 286 | break; |
| 287 | case 0x12: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 288 | printf("SIMD Floating-Point Exception\n"); |
| 289 | dump_regs(regs); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 290 | break; |
| 291 | case 0x13: |
| 292 | case 0x14: |
| 293 | case 0x15: |
| 294 | case 0x16: |
| 295 | case 0x17: |
| 296 | case 0x18: |
| 297 | case 0x19: |
| 298 | case 0x1a: |
| 299 | case 0x1b: |
| 300 | case 0x1c: |
| 301 | case 0x1d: |
| 302 | case 0x1e: |
| 303 | case 0x1f: |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 304 | printf("Reserved Exception\n"); |
| 305 | dump_regs(regs); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 306 | break; |
| 307 | |
| 308 | default: |
| 309 | /* Hardware or User IRQ */ |
Graeme Russ | 4326153 | 2010-10-07 20:03:23 +1100 | [diff] [blame] | 310 | do_irq(regs->irq_id); |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 311 | } |
| 312 | } |
| 313 | |
| 314 | /* |
| 315 | * OK - This looks really horrible, but it serves a purpose - It helps create |
| 316 | * fully relocatable code. |
| 317 | * - The call to irq_llsr will be a relative jump |
| 318 | * - The IRQ entries will be guaranteed to be in order |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 319 | * Interrupt entries are now very small (a push and a jump) but they are |
| 320 | * now slower (all registers pushed on stack which provides complete |
| 321 | * crash dumps in the low level handlers |
Graeme Russ | 4326153 | 2010-10-07 20:03:23 +1100 | [diff] [blame] | 322 | * |
| 323 | * Interrupt Entry Point: |
| 324 | * - Interrupt has caused eflags, CS and EIP to be pushed |
| 325 | * - Interrupt Vector Handler has pushed orig_eax |
| 326 | * - pt_regs.esp needs to be adjusted by 40 bytes: |
| 327 | * 12 bytes pushed by CPU (EFLAGSF, CS, EIP) |
| 328 | * 4 bytes pushed by vector handler (irq_id) |
| 329 | * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX) |
| 330 | * NOTE: Only longs are pushed on/popped off the stack! |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 331 | */ |
| 332 | asm(".globl irq_common_entry\n" \ |
Graeme Russ | 1aafcc9 | 2009-11-24 20:04:19 +1100 | [diff] [blame] | 333 | ".hidden irq_common_entry\n" \ |
| 334 | ".type irq_common_entry, @function\n" \ |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 335 | "irq_common_entry:\n" \ |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 336 | "cld\n" \ |
Graeme Russ | 4326153 | 2010-10-07 20:03:23 +1100 | [diff] [blame] | 337 | "pushl %ss\n" \ |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 338 | "pushl %gs\n" \ |
| 339 | "pushl %fs\n" \ |
| 340 | "pushl %es\n" \ |
| 341 | "pushl %ds\n" \ |
| 342 | "pushl %eax\n" \ |
Graeme Russ | 4326153 | 2010-10-07 20:03:23 +1100 | [diff] [blame] | 343 | "movl %esp, %eax\n" \ |
| 344 | "addl $40, %eax\n" \ |
| 345 | "pushl %eax\n" \ |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 346 | "pushl %ebp\n" \ |
| 347 | "pushl %edi\n" \ |
| 348 | "pushl %esi\n" \ |
| 349 | "pushl %edx\n" \ |
| 350 | "pushl %ecx\n" \ |
| 351 | "pushl %ebx\n" \ |
| 352 | "mov %esp, %eax\n" \ |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 353 | "call irq_llsr\n" \ |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 354 | "popl %ebx\n" \ |
| 355 | "popl %ecx\n" \ |
| 356 | "popl %edx\n" \ |
| 357 | "popl %esi\n" \ |
| 358 | "popl %edi\n" \ |
| 359 | "popl %ebp\n" \ |
| 360 | "popl %eax\n" \ |
Graeme Russ | 4326153 | 2010-10-07 20:03:23 +1100 | [diff] [blame] | 361 | "popl %eax\n" \ |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 362 | "popl %ds\n" \ |
| 363 | "popl %es\n" \ |
| 364 | "popl %fs\n" \ |
| 365 | "popl %gs\n" \ |
Graeme Russ | 4326153 | 2010-10-07 20:03:23 +1100 | [diff] [blame] | 366 | "popl %ss\n" \ |
Graeme Russ | c39acb4 | 2010-04-24 00:05:38 +1000 | [diff] [blame] | 367 | "add $4, %esp\n" \ |
Graeme Russ | d11b085 | 2009-11-24 20:04:18 +1100 | [diff] [blame] | 368 | "iret\n" \ |
| 369 | DECLARE_INTERRUPT(0) \ |
| 370 | DECLARE_INTERRUPT(1) \ |
| 371 | DECLARE_INTERRUPT(2) \ |
| 372 | DECLARE_INTERRUPT(3) \ |
| 373 | DECLARE_INTERRUPT(4) \ |
| 374 | DECLARE_INTERRUPT(5) \ |
| 375 | DECLARE_INTERRUPT(6) \ |
| 376 | DECLARE_INTERRUPT(7) \ |
| 377 | DECLARE_INTERRUPT(8) \ |
| 378 | DECLARE_INTERRUPT(9) \ |
| 379 | DECLARE_INTERRUPT(10) \ |
| 380 | DECLARE_INTERRUPT(11) \ |
| 381 | DECLARE_INTERRUPT(12) \ |
| 382 | DECLARE_INTERRUPT(13) \ |
| 383 | DECLARE_INTERRUPT(14) \ |
| 384 | DECLARE_INTERRUPT(15) \ |
| 385 | DECLARE_INTERRUPT(16) \ |
| 386 | DECLARE_INTERRUPT(17) \ |
| 387 | DECLARE_INTERRUPT(18) \ |
| 388 | DECLARE_INTERRUPT(19) \ |
| 389 | DECLARE_INTERRUPT(20) \ |
| 390 | DECLARE_INTERRUPT(21) \ |
| 391 | DECLARE_INTERRUPT(22) \ |
| 392 | DECLARE_INTERRUPT(23) \ |
| 393 | DECLARE_INTERRUPT(24) \ |
| 394 | DECLARE_INTERRUPT(25) \ |
| 395 | DECLARE_INTERRUPT(26) \ |
| 396 | DECLARE_INTERRUPT(27) \ |
| 397 | DECLARE_INTERRUPT(28) \ |
| 398 | DECLARE_INTERRUPT(29) \ |
| 399 | DECLARE_INTERRUPT(30) \ |
| 400 | DECLARE_INTERRUPT(31) \ |
| 401 | DECLARE_INTERRUPT(32) \ |
| 402 | DECLARE_INTERRUPT(33) \ |
| 403 | DECLARE_INTERRUPT(34) \ |
| 404 | DECLARE_INTERRUPT(35) \ |
| 405 | DECLARE_INTERRUPT(36) \ |
| 406 | DECLARE_INTERRUPT(37) \ |
| 407 | DECLARE_INTERRUPT(38) \ |
| 408 | DECLARE_INTERRUPT(39) \ |
| 409 | DECLARE_INTERRUPT(40) \ |
| 410 | DECLARE_INTERRUPT(41) \ |
| 411 | DECLARE_INTERRUPT(42) \ |
| 412 | DECLARE_INTERRUPT(43) \ |
| 413 | DECLARE_INTERRUPT(44) \ |
| 414 | DECLARE_INTERRUPT(45) \ |
| 415 | DECLARE_INTERRUPT(46) \ |
| 416 | DECLARE_INTERRUPT(47) \ |
| 417 | DECLARE_INTERRUPT(48) \ |
| 418 | DECLARE_INTERRUPT(49) \ |
| 419 | DECLARE_INTERRUPT(50) \ |
| 420 | DECLARE_INTERRUPT(51) \ |
| 421 | DECLARE_INTERRUPT(52) \ |
| 422 | DECLARE_INTERRUPT(53) \ |
| 423 | DECLARE_INTERRUPT(54) \ |
| 424 | DECLARE_INTERRUPT(55) \ |
| 425 | DECLARE_INTERRUPT(56) \ |
| 426 | DECLARE_INTERRUPT(57) \ |
| 427 | DECLARE_INTERRUPT(58) \ |
| 428 | DECLARE_INTERRUPT(59) \ |
| 429 | DECLARE_INTERRUPT(60) \ |
| 430 | DECLARE_INTERRUPT(61) \ |
| 431 | DECLARE_INTERRUPT(62) \ |
| 432 | DECLARE_INTERRUPT(63) \ |
| 433 | DECLARE_INTERRUPT(64) \ |
| 434 | DECLARE_INTERRUPT(65) \ |
| 435 | DECLARE_INTERRUPT(66) \ |
| 436 | DECLARE_INTERRUPT(67) \ |
| 437 | DECLARE_INTERRUPT(68) \ |
| 438 | DECLARE_INTERRUPT(69) \ |
| 439 | DECLARE_INTERRUPT(70) \ |
| 440 | DECLARE_INTERRUPT(71) \ |
| 441 | DECLARE_INTERRUPT(72) \ |
| 442 | DECLARE_INTERRUPT(73) \ |
| 443 | DECLARE_INTERRUPT(74) \ |
| 444 | DECLARE_INTERRUPT(75) \ |
| 445 | DECLARE_INTERRUPT(76) \ |
| 446 | DECLARE_INTERRUPT(77) \ |
| 447 | DECLARE_INTERRUPT(78) \ |
| 448 | DECLARE_INTERRUPT(79) \ |
| 449 | DECLARE_INTERRUPT(80) \ |
| 450 | DECLARE_INTERRUPT(81) \ |
| 451 | DECLARE_INTERRUPT(82) \ |
| 452 | DECLARE_INTERRUPT(83) \ |
| 453 | DECLARE_INTERRUPT(84) \ |
| 454 | DECLARE_INTERRUPT(85) \ |
| 455 | DECLARE_INTERRUPT(86) \ |
| 456 | DECLARE_INTERRUPT(87) \ |
| 457 | DECLARE_INTERRUPT(88) \ |
| 458 | DECLARE_INTERRUPT(89) \ |
| 459 | DECLARE_INTERRUPT(90) \ |
| 460 | DECLARE_INTERRUPT(91) \ |
| 461 | DECLARE_INTERRUPT(92) \ |
| 462 | DECLARE_INTERRUPT(93) \ |
| 463 | DECLARE_INTERRUPT(94) \ |
| 464 | DECLARE_INTERRUPT(95) \ |
| 465 | DECLARE_INTERRUPT(97) \ |
| 466 | DECLARE_INTERRUPT(96) \ |
| 467 | DECLARE_INTERRUPT(98) \ |
| 468 | DECLARE_INTERRUPT(99) \ |
| 469 | DECLARE_INTERRUPT(100) \ |
| 470 | DECLARE_INTERRUPT(101) \ |
| 471 | DECLARE_INTERRUPT(102) \ |
| 472 | DECLARE_INTERRUPT(103) \ |
| 473 | DECLARE_INTERRUPT(104) \ |
| 474 | DECLARE_INTERRUPT(105) \ |
| 475 | DECLARE_INTERRUPT(106) \ |
| 476 | DECLARE_INTERRUPT(107) \ |
| 477 | DECLARE_INTERRUPT(108) \ |
| 478 | DECLARE_INTERRUPT(109) \ |
| 479 | DECLARE_INTERRUPT(110) \ |
| 480 | DECLARE_INTERRUPT(111) \ |
| 481 | DECLARE_INTERRUPT(112) \ |
| 482 | DECLARE_INTERRUPT(113) \ |
| 483 | DECLARE_INTERRUPT(114) \ |
| 484 | DECLARE_INTERRUPT(115) \ |
| 485 | DECLARE_INTERRUPT(116) \ |
| 486 | DECLARE_INTERRUPT(117) \ |
| 487 | DECLARE_INTERRUPT(118) \ |
| 488 | DECLARE_INTERRUPT(119) \ |
| 489 | DECLARE_INTERRUPT(120) \ |
| 490 | DECLARE_INTERRUPT(121) \ |
| 491 | DECLARE_INTERRUPT(122) \ |
| 492 | DECLARE_INTERRUPT(123) \ |
| 493 | DECLARE_INTERRUPT(124) \ |
| 494 | DECLARE_INTERRUPT(125) \ |
| 495 | DECLARE_INTERRUPT(126) \ |
| 496 | DECLARE_INTERRUPT(127) \ |
| 497 | DECLARE_INTERRUPT(128) \ |
| 498 | DECLARE_INTERRUPT(129) \ |
| 499 | DECLARE_INTERRUPT(130) \ |
| 500 | DECLARE_INTERRUPT(131) \ |
| 501 | DECLARE_INTERRUPT(132) \ |
| 502 | DECLARE_INTERRUPT(133) \ |
| 503 | DECLARE_INTERRUPT(134) \ |
| 504 | DECLARE_INTERRUPT(135) \ |
| 505 | DECLARE_INTERRUPT(136) \ |
| 506 | DECLARE_INTERRUPT(137) \ |
| 507 | DECLARE_INTERRUPT(138) \ |
| 508 | DECLARE_INTERRUPT(139) \ |
| 509 | DECLARE_INTERRUPT(140) \ |
| 510 | DECLARE_INTERRUPT(141) \ |
| 511 | DECLARE_INTERRUPT(142) \ |
| 512 | DECLARE_INTERRUPT(143) \ |
| 513 | DECLARE_INTERRUPT(144) \ |
| 514 | DECLARE_INTERRUPT(145) \ |
| 515 | DECLARE_INTERRUPT(146) \ |
| 516 | DECLARE_INTERRUPT(147) \ |
| 517 | DECLARE_INTERRUPT(148) \ |
| 518 | DECLARE_INTERRUPT(149) \ |
| 519 | DECLARE_INTERRUPT(150) \ |
| 520 | DECLARE_INTERRUPT(151) \ |
| 521 | DECLARE_INTERRUPT(152) \ |
| 522 | DECLARE_INTERRUPT(153) \ |
| 523 | DECLARE_INTERRUPT(154) \ |
| 524 | DECLARE_INTERRUPT(155) \ |
| 525 | DECLARE_INTERRUPT(156) \ |
| 526 | DECLARE_INTERRUPT(157) \ |
| 527 | DECLARE_INTERRUPT(158) \ |
| 528 | DECLARE_INTERRUPT(159) \ |
| 529 | DECLARE_INTERRUPT(160) \ |
| 530 | DECLARE_INTERRUPT(161) \ |
| 531 | DECLARE_INTERRUPT(162) \ |
| 532 | DECLARE_INTERRUPT(163) \ |
| 533 | DECLARE_INTERRUPT(164) \ |
| 534 | DECLARE_INTERRUPT(165) \ |
| 535 | DECLARE_INTERRUPT(166) \ |
| 536 | DECLARE_INTERRUPT(167) \ |
| 537 | DECLARE_INTERRUPT(168) \ |
| 538 | DECLARE_INTERRUPT(169) \ |
| 539 | DECLARE_INTERRUPT(170) \ |
| 540 | DECLARE_INTERRUPT(171) \ |
| 541 | DECLARE_INTERRUPT(172) \ |
| 542 | DECLARE_INTERRUPT(173) \ |
| 543 | DECLARE_INTERRUPT(174) \ |
| 544 | DECLARE_INTERRUPT(175) \ |
| 545 | DECLARE_INTERRUPT(176) \ |
| 546 | DECLARE_INTERRUPT(177) \ |
| 547 | DECLARE_INTERRUPT(178) \ |
| 548 | DECLARE_INTERRUPT(179) \ |
| 549 | DECLARE_INTERRUPT(180) \ |
| 550 | DECLARE_INTERRUPT(181) \ |
| 551 | DECLARE_INTERRUPT(182) \ |
| 552 | DECLARE_INTERRUPT(183) \ |
| 553 | DECLARE_INTERRUPT(184) \ |
| 554 | DECLARE_INTERRUPT(185) \ |
| 555 | DECLARE_INTERRUPT(186) \ |
| 556 | DECLARE_INTERRUPT(187) \ |
| 557 | DECLARE_INTERRUPT(188) \ |
| 558 | DECLARE_INTERRUPT(189) \ |
| 559 | DECLARE_INTERRUPT(190) \ |
| 560 | DECLARE_INTERRUPT(191) \ |
| 561 | DECLARE_INTERRUPT(192) \ |
| 562 | DECLARE_INTERRUPT(193) \ |
| 563 | DECLARE_INTERRUPT(194) \ |
| 564 | DECLARE_INTERRUPT(195) \ |
| 565 | DECLARE_INTERRUPT(196) \ |
| 566 | DECLARE_INTERRUPT(197) \ |
| 567 | DECLARE_INTERRUPT(198) \ |
| 568 | DECLARE_INTERRUPT(199) \ |
| 569 | DECLARE_INTERRUPT(200) \ |
| 570 | DECLARE_INTERRUPT(201) \ |
| 571 | DECLARE_INTERRUPT(202) \ |
| 572 | DECLARE_INTERRUPT(203) \ |
| 573 | DECLARE_INTERRUPT(204) \ |
| 574 | DECLARE_INTERRUPT(205) \ |
| 575 | DECLARE_INTERRUPT(206) \ |
| 576 | DECLARE_INTERRUPT(207) \ |
| 577 | DECLARE_INTERRUPT(208) \ |
| 578 | DECLARE_INTERRUPT(209) \ |
| 579 | DECLARE_INTERRUPT(210) \ |
| 580 | DECLARE_INTERRUPT(211) \ |
| 581 | DECLARE_INTERRUPT(212) \ |
| 582 | DECLARE_INTERRUPT(213) \ |
| 583 | DECLARE_INTERRUPT(214) \ |
| 584 | DECLARE_INTERRUPT(215) \ |
| 585 | DECLARE_INTERRUPT(216) \ |
| 586 | DECLARE_INTERRUPT(217) \ |
| 587 | DECLARE_INTERRUPT(218) \ |
| 588 | DECLARE_INTERRUPT(219) \ |
| 589 | DECLARE_INTERRUPT(220) \ |
| 590 | DECLARE_INTERRUPT(221) \ |
| 591 | DECLARE_INTERRUPT(222) \ |
| 592 | DECLARE_INTERRUPT(223) \ |
| 593 | DECLARE_INTERRUPT(224) \ |
| 594 | DECLARE_INTERRUPT(225) \ |
| 595 | DECLARE_INTERRUPT(226) \ |
| 596 | DECLARE_INTERRUPT(227) \ |
| 597 | DECLARE_INTERRUPT(228) \ |
| 598 | DECLARE_INTERRUPT(229) \ |
| 599 | DECLARE_INTERRUPT(230) \ |
| 600 | DECLARE_INTERRUPT(231) \ |
| 601 | DECLARE_INTERRUPT(232) \ |
| 602 | DECLARE_INTERRUPT(233) \ |
| 603 | DECLARE_INTERRUPT(234) \ |
| 604 | DECLARE_INTERRUPT(235) \ |
| 605 | DECLARE_INTERRUPT(236) \ |
| 606 | DECLARE_INTERRUPT(237) \ |
| 607 | DECLARE_INTERRUPT(238) \ |
| 608 | DECLARE_INTERRUPT(239) \ |
| 609 | DECLARE_INTERRUPT(240) \ |
| 610 | DECLARE_INTERRUPT(241) \ |
| 611 | DECLARE_INTERRUPT(242) \ |
| 612 | DECLARE_INTERRUPT(243) \ |
| 613 | DECLARE_INTERRUPT(244) \ |
| 614 | DECLARE_INTERRUPT(245) \ |
| 615 | DECLARE_INTERRUPT(246) \ |
| 616 | DECLARE_INTERRUPT(247) \ |
| 617 | DECLARE_INTERRUPT(248) \ |
| 618 | DECLARE_INTERRUPT(249) \ |
| 619 | DECLARE_INTERRUPT(250) \ |
| 620 | DECLARE_INTERRUPT(251) \ |
| 621 | DECLARE_INTERRUPT(252) \ |
| 622 | DECLARE_INTERRUPT(253) \ |
| 623 | DECLARE_INTERRUPT(254) \ |
| 624 | DECLARE_INTERRUPT(255)); |