wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * This provides a bit-banged interface to the ethernet MII management |
| 26 | * channel. |
| 27 | */ |
| 28 | |
| 29 | #include <common.h> |
| 30 | #include <miiphy.h> |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 31 | #include <phy.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 32 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 33 | #include <asm/types.h> |
| 34 | #include <linux/list.h> |
| 35 | #include <malloc.h> |
| 36 | #include <net.h> |
| 37 | |
| 38 | /* local debug macro */ |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 39 | #undef MII_DEBUG |
| 40 | |
| 41 | #undef debug |
| 42 | #ifdef MII_DEBUG |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 43 | #define debug(fmt, args...) printf(fmt, ##args) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 44 | #else |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 45 | #define debug(fmt, args...) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 46 | #endif /* MII_DEBUG */ |
| 47 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 48 | static struct list_head mii_devs; |
| 49 | static struct mii_dev *current_mii; |
| 50 | |
Mike Frysinger | 24a9008 | 2010-07-27 18:35:09 -0400 | [diff] [blame] | 51 | /* |
| 52 | * Lookup the mii_dev struct by the registered device name. |
| 53 | */ |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 54 | struct mii_dev *miiphy_get_dev_by_name(const char *devname) |
Mike Frysinger | 24a9008 | 2010-07-27 18:35:09 -0400 | [diff] [blame] | 55 | { |
| 56 | struct list_head *entry; |
| 57 | struct mii_dev *dev; |
| 58 | |
| 59 | if (!devname) { |
| 60 | printf("NULL device name!\n"); |
| 61 | return NULL; |
| 62 | } |
| 63 | |
| 64 | list_for_each(entry, &mii_devs) { |
| 65 | dev = list_entry(entry, struct mii_dev, link); |
| 66 | if (strcmp(dev->name, devname) == 0) |
| 67 | return dev; |
| 68 | } |
| 69 | |
Mike Frysinger | 24a9008 | 2010-07-27 18:35:09 -0400 | [diff] [blame] | 70 | return NULL; |
| 71 | } |
| 72 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 73 | /***************************************************************************** |
| 74 | * |
Marian Balakowicz | cbdd1c8 | 2005-11-30 18:06:04 +0100 | [diff] [blame] | 75 | * Initialize global data. Need to be called before any other miiphy routine. |
| 76 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 77 | void miiphy_init(void) |
Marian Balakowicz | cbdd1c8 | 2005-11-30 18:06:04 +0100 | [diff] [blame] | 78 | { |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 79 | INIT_LIST_HEAD(&mii_devs); |
Larry Johnson | 81b974b | 2007-10-31 11:21:29 -0500 | [diff] [blame] | 80 | current_mii = NULL; |
Marian Balakowicz | cbdd1c8 | 2005-11-30 18:06:04 +0100 | [diff] [blame] | 81 | } |
| 82 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 83 | static int legacy_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) |
| 84 | { |
| 85 | unsigned short val; |
| 86 | int ret; |
| 87 | struct legacy_mii_dev *ldev = bus->priv; |
| 88 | |
| 89 | ret = ldev->read(bus->name, addr, reg, &val); |
| 90 | |
| 91 | return ret ? -1 : (int)val; |
| 92 | } |
| 93 | |
| 94 | static int legacy_miiphy_write(struct mii_dev *bus, int addr, int devad, |
| 95 | int reg, u16 val) |
| 96 | { |
| 97 | struct legacy_mii_dev *ldev = bus->priv; |
| 98 | |
| 99 | return ldev->write(bus->name, addr, reg, val); |
| 100 | } |
| 101 | |
Marian Balakowicz | cbdd1c8 | 2005-11-30 18:06:04 +0100 | [diff] [blame] | 102 | /***************************************************************************** |
| 103 | * |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 104 | * Register read and write MII access routines for the device <name>. |
| 105 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 106 | void miiphy_register(const char *name, |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 107 | int (*read)(const char *devname, unsigned char addr, |
Larry Johnson | 81b974b | 2007-10-31 11:21:29 -0500 | [diff] [blame] | 108 | unsigned char reg, unsigned short *value), |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 109 | int (*write)(const char *devname, unsigned char addr, |
Larry Johnson | 81b974b | 2007-10-31 11:21:29 -0500 | [diff] [blame] | 110 | unsigned char reg, unsigned short value)) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 111 | { |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 112 | struct mii_dev *new_dev; |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 113 | struct legacy_mii_dev *ldev; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 114 | unsigned int name_len; |
| 115 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 116 | /* check if we have unique name */ |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 117 | new_dev = miiphy_get_dev_by_name(name); |
Mike Frysinger | 24a9008 | 2010-07-27 18:35:09 -0400 | [diff] [blame] | 118 | if (new_dev) { |
| 119 | printf("miiphy_register: non unique device name '%s'\n", name); |
| 120 | return; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | /* allocate memory */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 124 | name_len = strlen(name); |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 125 | if (name_len > MDIO_NAME_LEN - 1) { |
| 126 | /* Hopefully this won't happen, but if it does, we'll know */ |
| 127 | printf("miiphy_register: MDIO name was longer than %d\n", |
| 128 | MDIO_NAME_LEN); |
| 129 | return; |
| 130 | } |
| 131 | |
| 132 | new_dev = mdio_alloc(); |
| 133 | ldev = malloc(sizeof(*ldev)); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 134 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 135 | if (new_dev == NULL || ldev == NULL) { |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 136 | printf("miiphy_register: cannot allocate memory for '%s'\n", |
Larry Johnson | 81b974b | 2007-10-31 11:21:29 -0500 | [diff] [blame] | 137 | name); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 138 | return; |
| 139 | } |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 140 | |
| 141 | /* initalize mii_dev struct fields */ |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 142 | new_dev->read = legacy_miiphy_read; |
| 143 | new_dev->write = legacy_miiphy_write; |
| 144 | sprintf(new_dev->name, name); |
| 145 | ldev->read = read; |
| 146 | ldev->write = write; |
| 147 | new_dev->priv = ldev; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 148 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 149 | debug("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n", |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 150 | new_dev->name, ldev->read, ldev->write); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 151 | |
| 152 | /* add it to the list */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 153 | list_add_tail(&new_dev->link, &mii_devs); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 154 | |
| 155 | if (!current_mii) |
| 156 | current_mii = new_dev; |
| 157 | } |
| 158 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 159 | struct mii_dev *mdio_alloc(void) |
| 160 | { |
| 161 | struct mii_dev *bus; |
| 162 | |
| 163 | bus = malloc(sizeof(*bus)); |
| 164 | if (!bus) |
| 165 | return bus; |
| 166 | |
| 167 | memset(bus, 0, sizeof(*bus)); |
| 168 | |
| 169 | /* initalize mii_dev struct fields */ |
| 170 | INIT_LIST_HEAD(&bus->link); |
| 171 | |
| 172 | return bus; |
| 173 | } |
| 174 | |
| 175 | int mdio_register(struct mii_dev *bus) |
| 176 | { |
| 177 | if (!bus || !bus->name || !bus->read || !bus->write) |
| 178 | return -1; |
| 179 | |
| 180 | /* check if we have unique name */ |
| 181 | if (miiphy_get_dev_by_name(bus->name)) { |
| 182 | printf("mdio_register: non unique device name '%s'\n", |
| 183 | bus->name); |
| 184 | return -1; |
| 185 | } |
| 186 | |
| 187 | /* add it to the list */ |
| 188 | list_add_tail(&bus->link, &mii_devs); |
| 189 | |
| 190 | if (!current_mii) |
| 191 | current_mii = bus; |
| 192 | |
| 193 | return 0; |
| 194 | } |
| 195 | |
| 196 | void mdio_list_devices(void) |
| 197 | { |
| 198 | struct list_head *entry; |
| 199 | |
| 200 | list_for_each(entry, &mii_devs) { |
| 201 | int i; |
| 202 | struct mii_dev *bus = list_entry(entry, struct mii_dev, link); |
| 203 | |
| 204 | printf("%s:\n", bus->name); |
| 205 | |
| 206 | for (i = 0; i < PHY_MAX_ADDR; i++) { |
| 207 | struct phy_device *phydev = bus->phymap[i]; |
| 208 | |
| 209 | if (phydev) { |
| 210 | printf("%d - %s", i, phydev->drv->name); |
| 211 | |
| 212 | if (phydev->dev) |
| 213 | printf(" <--> %s\n", phydev->dev->name); |
| 214 | else |
| 215 | printf("\n"); |
| 216 | } |
| 217 | } |
| 218 | } |
| 219 | } |
| 220 | |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 221 | int miiphy_set_current_dev(const char *devname) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 222 | { |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 223 | struct mii_dev *dev; |
| 224 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 225 | dev = miiphy_get_dev_by_name(devname); |
Mike Frysinger | 24a9008 | 2010-07-27 18:35:09 -0400 | [diff] [blame] | 226 | if (dev) { |
| 227 | current_mii = dev; |
| 228 | return 0; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 229 | } |
| 230 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 231 | printf("No such device: %s\n", devname); |
| 232 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 233 | return 1; |
| 234 | } |
| 235 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 236 | struct mii_dev *mdio_get_current_dev(void) |
| 237 | { |
| 238 | return current_mii; |
| 239 | } |
| 240 | |
| 241 | struct phy_device *mdio_phydev_for_ethname(const char *ethname) |
| 242 | { |
| 243 | struct list_head *entry; |
| 244 | struct mii_dev *bus; |
| 245 | |
| 246 | list_for_each(entry, &mii_devs) { |
| 247 | int i; |
| 248 | bus = list_entry(entry, struct mii_dev, link); |
| 249 | |
| 250 | for (i = 0; i < PHY_MAX_ADDR; i++) { |
| 251 | if (!bus->phymap[i] || !bus->phymap[i]->dev) |
| 252 | continue; |
| 253 | |
| 254 | if (strcmp(bus->phymap[i]->dev->name, ethname) == 0) |
| 255 | return bus->phymap[i]; |
| 256 | } |
| 257 | } |
| 258 | |
| 259 | printf("%s is not a known ethernet\n", ethname); |
| 260 | return NULL; |
| 261 | } |
| 262 | |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 263 | const char *miiphy_get_current_dev(void) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 264 | { |
| 265 | if (current_mii) |
| 266 | return current_mii->name; |
| 267 | |
| 268 | return NULL; |
| 269 | } |
| 270 | |
Mike Frysinger | bd17e7a | 2010-07-27 18:35:10 -0400 | [diff] [blame] | 271 | static struct mii_dev *miiphy_get_active_dev(const char *devname) |
| 272 | { |
| 273 | /* If the current mii is the one we want, return it */ |
| 274 | if (current_mii) |
| 275 | if (strcmp(current_mii->name, devname) == 0) |
| 276 | return current_mii; |
| 277 | |
| 278 | /* Otherwise, set the active one to the one we want */ |
| 279 | if (miiphy_set_current_dev(devname)) |
| 280 | return NULL; |
| 281 | else |
| 282 | return current_mii; |
| 283 | } |
| 284 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 285 | /***************************************************************************** |
| 286 | * |
| 287 | * Read to variable <value> from the PHY attached to device <devname>, |
| 288 | * use PHY address <addr> and register <reg>. |
| 289 | * |
| 290 | * Returns: |
| 291 | * 0 on success |
| 292 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 293 | int miiphy_read(const char *devname, unsigned char addr, unsigned char reg, |
Larry Johnson | 81b974b | 2007-10-31 11:21:29 -0500 | [diff] [blame] | 294 | unsigned short *value) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 295 | { |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 296 | struct mii_dev *bus; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 297 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 298 | bus = miiphy_get_active_dev(devname); |
| 299 | if (bus) |
| 300 | *value = bus->read(bus, addr, MDIO_DEVAD_NONE, reg); |
| 301 | else |
| 302 | return 1; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 303 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 304 | return (*value < 0) ? 1 : 0; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | /***************************************************************************** |
| 308 | * |
| 309 | * Write <value> to the PHY attached to device <devname>, |
| 310 | * use PHY address <addr> and register <reg>. |
| 311 | * |
| 312 | * Returns: |
| 313 | * 0 on success |
| 314 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 315 | int miiphy_write(const char *devname, unsigned char addr, unsigned char reg, |
Larry Johnson | 81b974b | 2007-10-31 11:21:29 -0500 | [diff] [blame] | 316 | unsigned short value) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 317 | { |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 318 | struct mii_dev *bus; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 319 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 320 | bus = miiphy_get_active_dev(devname); |
| 321 | if (bus) |
| 322 | return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, value); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 323 | |
Mike Frysinger | 24a9008 | 2010-07-27 18:35:09 -0400 | [diff] [blame] | 324 | return 1; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 325 | } |
| 326 | |
| 327 | /***************************************************************************** |
| 328 | * |
| 329 | * Print out list of registered MII capable devices. |
| 330 | */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 331 | void miiphy_listdev(void) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 332 | { |
| 333 | struct list_head *entry; |
| 334 | struct mii_dev *dev; |
| 335 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 336 | puts("MII devices: "); |
| 337 | list_for_each(entry, &mii_devs) { |
| 338 | dev = list_entry(entry, struct mii_dev, link); |
| 339 | printf("'%s' ", dev->name); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 340 | } |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 341 | puts("\n"); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 342 | |
| 343 | if (current_mii) |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 344 | printf("Current device: '%s'\n", current_mii->name); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 345 | } |
| 346 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 347 | /***************************************************************************** |
| 348 | * |
| 349 | * Read the OUI, manufacture's model number, and revision number. |
| 350 | * |
| 351 | * OUI: 22 bits (unsigned int) |
| 352 | * Model: 6 bits (unsigned char) |
| 353 | * Revision: 4 bits (unsigned char) |
| 354 | * |
| 355 | * Returns: |
| 356 | * 0 on success |
| 357 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 358 | int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui, |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 359 | unsigned char *model, unsigned char *rev) |
| 360 | { |
| 361 | unsigned int reg = 0; |
wdenk | f4cec3f | 2003-12-06 23:20:41 +0000 | [diff] [blame] | 362 | unsigned short tmp; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 363 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 364 | if (miiphy_read(devname, addr, MII_PHYSID2, &tmp) != 0) { |
| 365 | debug("PHY ID register 2 read failed\n"); |
| 366 | return -1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 367 | } |
wdenk | f4cec3f | 2003-12-06 23:20:41 +0000 | [diff] [blame] | 368 | reg = tmp; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 369 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 370 | debug("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg); |
Shinya Kuribayashi | 49e42af | 2008-01-19 10:25:59 +0900 | [diff] [blame] | 371 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 372 | if (reg == 0xFFFF) { |
| 373 | /* No physical device present at this address */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 374 | return -1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 375 | } |
| 376 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 377 | if (miiphy_read(devname, addr, MII_PHYSID1, &tmp) != 0) { |
| 378 | debug("PHY ID register 1 read failed\n"); |
| 379 | return -1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 380 | } |
wdenk | f4cec3f | 2003-12-06 23:20:41 +0000 | [diff] [blame] | 381 | reg |= tmp << 16; |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 382 | debug("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg); |
Shinya Kuribayashi | 49e42af | 2008-01-19 10:25:59 +0900 | [diff] [blame] | 383 | |
Larry Johnson | 81b974b | 2007-10-31 11:21:29 -0500 | [diff] [blame] | 384 | *oui = (reg >> 10); |
| 385 | *model = (unsigned char)((reg >> 4) & 0x0000003F); |
| 386 | *rev = (unsigned char)(reg & 0x0000000F); |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 387 | return 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 388 | } |
| 389 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 390 | #ifndef CONFIG_PHYLIB |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 391 | /***************************************************************************** |
| 392 | * |
| 393 | * Reset the PHY. |
| 394 | * Returns: |
| 395 | * 0 on success |
| 396 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 397 | int miiphy_reset(const char *devname, unsigned char addr) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 398 | { |
| 399 | unsigned short reg; |
Stefan Roese | 2e53636 | 2010-02-02 13:43:48 +0100 | [diff] [blame] | 400 | int timeout = 500; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 401 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 402 | if (miiphy_read(devname, addr, MII_BMCR, ®) != 0) { |
| 403 | debug("PHY status read failed\n"); |
| 404 | return -1; |
Wolfgang Denk | 8ff63c2 | 2005-08-12 23:15:53 +0200 | [diff] [blame] | 405 | } |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 406 | if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) { |
| 407 | debug("PHY reset failed\n"); |
| 408 | return -1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 409 | } |
wdenk | 2cefd15 | 2004-02-08 22:55:38 +0000 | [diff] [blame] | 410 | #ifdef CONFIG_PHY_RESET_DELAY |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 411 | udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */ |
wdenk | 2cefd15 | 2004-02-08 22:55:38 +0000 | [diff] [blame] | 412 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 413 | /* |
| 414 | * Poll the control register for the reset bit to go to 0 (it is |
| 415 | * auto-clearing). This should happen within 0.5 seconds per the |
| 416 | * IEEE spec. |
| 417 | */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 418 | reg = 0x8000; |
Stefan Roese | 2e53636 | 2010-02-02 13:43:48 +0100 | [diff] [blame] | 419 | while (((reg & 0x8000) != 0) && timeout--) { |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 420 | if (miiphy_read(devname, addr, MII_BMCR, ®) != 0) { |
Stefan Roese | 2e53636 | 2010-02-02 13:43:48 +0100 | [diff] [blame] | 421 | debug("PHY status read failed\n"); |
| 422 | return -1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 423 | } |
Stefan Roese | 2e53636 | 2010-02-02 13:43:48 +0100 | [diff] [blame] | 424 | udelay(1000); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 425 | } |
| 426 | if ((reg & 0x8000) == 0) { |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 427 | return 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 428 | } else { |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 429 | puts("PHY reset timed out\n"); |
| 430 | return -1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 431 | } |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 432 | return 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 433 | } |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 434 | #endif /* !PHYLIB */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 435 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 436 | /***************************************************************************** |
| 437 | * |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 438 | * Determine the ethernet speed (10/100/1000). Return 10 on error. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 439 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 440 | int miiphy_speed(const char *devname, unsigned char addr) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 441 | { |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 442 | u16 bmcr, anlpar; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 443 | |
wdenk | eec9a3d | 2004-03-23 23:20:24 +0000 | [diff] [blame] | 444 | #if defined(CONFIG_PHY_GIGE) |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 445 | u16 btsr; |
| 446 | |
| 447 | /* |
| 448 | * Check for 1000BASE-X. If it is supported, then assume that the speed |
| 449 | * is 1000. |
| 450 | */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 451 | if (miiphy_is_1000base_x(devname, addr)) |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 452 | return _1000BASET; |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 453 | |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 454 | /* |
| 455 | * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. |
| 456 | */ |
| 457 | /* Check for 1000BASE-T. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 458 | if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) { |
| 459 | printf("PHY 1000BT status"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 460 | goto miiphy_read_failed; |
| 461 | } |
| 462 | if (btsr != 0xFFFF && |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 463 | (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 464 | return _1000BASET; |
wdenk | eec9a3d | 2004-03-23 23:20:24 +0000 | [diff] [blame] | 465 | #endif /* CONFIG_PHY_GIGE */ |
wdenk | ed2ac4b | 2004-03-14 18:23:55 +0000 | [diff] [blame] | 466 | |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 467 | /* Check Basic Management Control Register first. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 468 | if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { |
| 469 | printf("PHY speed"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 470 | goto miiphy_read_failed; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 471 | } |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 472 | /* Check if auto-negotiation is on. */ |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 473 | if (bmcr & BMCR_ANENABLE) { |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 474 | /* Get auto-negotiation results. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 475 | if (miiphy_read(devname, addr, MII_LPA, &anlpar)) { |
| 476 | printf("PHY AN speed"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 477 | goto miiphy_read_failed; |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 478 | } |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 479 | return (anlpar & LPA_100) ? _100BASET : _10BASET; |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 480 | } |
| 481 | /* Get speed from basic control settings. */ |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 482 | return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET; |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 483 | |
Michael Zaidman | 6dbca5f | 2010-02-28 16:28:25 +0200 | [diff] [blame] | 484 | miiphy_read_failed: |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 485 | printf(" read failed, assuming 10BASE-T\n"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 486 | return _10BASET; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 487 | } |
| 488 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 489 | /***************************************************************************** |
| 490 | * |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 491 | * Determine full/half duplex. Return half on error. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 492 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 493 | int miiphy_duplex(const char *devname, unsigned char addr) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 494 | { |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 495 | u16 bmcr, anlpar; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 496 | |
wdenk | eec9a3d | 2004-03-23 23:20:24 +0000 | [diff] [blame] | 497 | #if defined(CONFIG_PHY_GIGE) |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 498 | u16 btsr; |
| 499 | |
| 500 | /* Check for 1000BASE-X. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 501 | if (miiphy_is_1000base_x(devname, addr)) { |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 502 | /* 1000BASE-X */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 503 | if (miiphy_read(devname, addr, MII_LPA, &anlpar)) { |
| 504 | printf("1000BASE-X PHY AN duplex"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 505 | goto miiphy_read_failed; |
wdenk | ed2ac4b | 2004-03-14 18:23:55 +0000 | [diff] [blame] | 506 | } |
| 507 | } |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 508 | /* |
| 509 | * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. |
| 510 | */ |
| 511 | /* Check for 1000BASE-T. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 512 | if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) { |
| 513 | printf("PHY 1000BT status"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 514 | goto miiphy_read_failed; |
| 515 | } |
| 516 | if (btsr != 0xFFFF) { |
| 517 | if (btsr & PHY_1000BTSR_1000FD) { |
| 518 | return FULL; |
| 519 | } else if (btsr & PHY_1000BTSR_1000HD) { |
| 520 | return HALF; |
| 521 | } |
| 522 | } |
wdenk | eec9a3d | 2004-03-23 23:20:24 +0000 | [diff] [blame] | 523 | #endif /* CONFIG_PHY_GIGE */ |
wdenk | ed2ac4b | 2004-03-14 18:23:55 +0000 | [diff] [blame] | 524 | |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 525 | /* Check Basic Management Control Register first. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 526 | if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { |
| 527 | puts("PHY duplex"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 528 | goto miiphy_read_failed; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 529 | } |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 530 | /* Check if auto-negotiation is on. */ |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 531 | if (bmcr & BMCR_ANENABLE) { |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 532 | /* Get auto-negotiation results. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 533 | if (miiphy_read(devname, addr, MII_LPA, &anlpar)) { |
| 534 | puts("PHY AN duplex"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 535 | goto miiphy_read_failed; |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 536 | } |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 537 | return (anlpar & (LPA_10FULL | LPA_100FULL)) ? |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 538 | FULL : HALF; |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 539 | } |
| 540 | /* Get speed from basic control settings. */ |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 541 | return (bmcr & BMCR_FULLDPLX) ? FULL : HALF; |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 542 | |
Michael Zaidman | 6dbca5f | 2010-02-28 16:28:25 +0200 | [diff] [blame] | 543 | miiphy_read_failed: |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 544 | printf(" read failed, assuming half duplex\n"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 545 | return HALF; |
| 546 | } |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 547 | |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 548 | /***************************************************************************** |
| 549 | * |
| 550 | * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/ |
| 551 | * 1000BASE-T, or on error. |
| 552 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 553 | int miiphy_is_1000base_x(const char *devname, unsigned char addr) |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 554 | { |
| 555 | #if defined(CONFIG_PHY_GIGE) |
| 556 | u16 exsr; |
| 557 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 558 | if (miiphy_read(devname, addr, MII_ESTATUS, &exsr)) { |
| 559 | printf("PHY extended status read failed, assuming no " |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 560 | "1000BASE-X\n"); |
| 561 | return 0; |
| 562 | } |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 563 | return 0 != (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 564 | #else |
| 565 | return 0; |
| 566 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 567 | } |
| 568 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 569 | #ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
wdenk | 49c3f67 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 570 | /***************************************************************************** |
| 571 | * |
| 572 | * Determine link status |
| 573 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 574 | int miiphy_link(const char *devname, unsigned char addr) |
wdenk | 49c3f67 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 575 | { |
| 576 | unsigned short reg; |
| 577 | |
wdenk | 145d2c1 | 2004-04-15 21:48:45 +0000 | [diff] [blame] | 578 | /* dummy read; needed to latch some phys */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 579 | (void)miiphy_read(devname, addr, MII_BMSR, ®); |
| 580 | if (miiphy_read(devname, addr, MII_BMSR, ®)) { |
| 581 | puts("MII_BMSR read failed, assuming no link\n"); |
| 582 | return 0; |
wdenk | 49c3f67 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 583 | } |
| 584 | |
| 585 | /* Determine if a link is active */ |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 586 | if ((reg & BMSR_LSTATUS) != 0) { |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 587 | return 1; |
wdenk | 49c3f67 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 588 | } else { |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 589 | return 0; |
wdenk | 49c3f67 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 590 | } |
| 591 | } |
| 592 | #endif |