blob: 006a59d6fa63cd6466babc80e8b1396ef31c5087 [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +09001menu "x86 architecture"
2 depends on X86
3
4config SYS_ARCH
Masahiro Yamadad3ae6782014-07-30 14:08:14 +09005 default "x86"
6
Masahiro Yamadad3ae6782014-07-30 14:08:14 +09007choice
Simon Glass0985e102017-01-16 07:03:43 -07008 prompt "Run U-Boot in 32/64-bit mode"
9 default X86_RUN_32BIT
10 help
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
14
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
18
19 For now, 32-bit mode is recommended, as 64-bit is still
20 experimental and is missing a lot of features.
21
22config X86_RUN_32BIT
23 bool "32-bit"
24 help
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28 to 64-bit just before starting the kernel. Only the bottom 4GB of
29 memory can be accessed through normal means, although
30 arch_phys_memset() can be used for basic access to other memory.
31
32config X86_RUN_64BIT
33 bool "64-bit"
34 select X86_64
Simon Glass890da242023-03-20 08:30:05 +130035 select SPL if !EFI_APP
36 select SPL_SEPARATE_BSS if !EFI_APP
Simon Glass0985e102017-01-16 07:03:43 -070037 help
38 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
39 experimental and many features are missing. U-Boot SPL starts up,
40 runs through the 16-bit and 32-bit init, then switches to 64-bit
41 mode and jumps to U-Boot proper.
42
43endchoice
44
45config X86_64
46 bool
Andrew Goodbody5b5322c2024-12-16 18:07:35 +000047 select 64BIT
Simon Glass0985e102017-01-16 07:03:43 -070048
49config SPL_X86_64
50 bool
51 depends on SPL
52
53choice
Bin Meng03b341b2015-04-27 23:22:24 +080054 prompt "Mainboard vendor"
Bin Mengf9bfac12015-05-07 21:34:09 +080055 default VENDOR_EMULATION
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090056
George McCollisteraedc33d2016-06-21 12:07:33 -050057config VENDOR_ADVANTECH
58 bool "advantech"
59
Stefan Roese2a0b94c2016-03-16 08:48:21 +010060config VENDOR_CONGATEC
61 bool "congatec"
62
Bin Meng03b341b2015-04-27 23:22:24 +080063config VENDOR_COREBOOT
64 bool "coreboot"
Simon Glass4a56f102015-01-27 22:13:47 -070065
Stefan Roese312dc932016-08-15 13:50:49 +020066config VENDOR_DFI
67 bool "dfi"
68
Ben Stoltzab76a472015-08-04 12:33:46 -060069config VENDOR_EFI
70 bool "efi"
71
Bin Meng2229c4c2015-05-07 21:34:08 +080072config VENDOR_EMULATION
73 bool "emulation"
74
Bin Meng03b341b2015-04-27 23:22:24 +080075config VENDOR_GOOGLE
76 bool "Google"
Simon Glass4a56f102015-01-27 22:13:47 -070077
Bin Meng03b341b2015-04-27 23:22:24 +080078config VENDOR_INTEL
79 bool "Intel"
Bin Meng8ba49fe2015-02-02 22:35:29 +080080
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090081endchoice
82
Andy Shevchenko78e473b2017-02-17 16:48:58 +030083# subarchitectures-specific options below
84config INTEL_MID
85 bool "Intel MID platform support"
Felipe Balbiee2e85f2017-04-01 16:21:33 +030086 select REGMAP
87 select SYSCON
Andy Shevchenko78e473b2017-02-17 16:48:58 +030088 help
89 Select to build a U-Boot capable of supporting Intel MID
90 (Mobile Internet Device) platform systems which do not have
91 the PCI legacy interfaces.
92
93 If you are building for a PC class system say N here.
94
95 Intel MID platforms are based on an Intel processor and
96 chipset which consume less power than most of the x86
97 derivatives.
98
Bin Meng03b341b2015-04-27 23:22:24 +080099# board-specific options below
George McCollisteraedc33d2016-06-21 12:07:33 -0500100source "board/advantech/Kconfig"
Stefan Roese2a0b94c2016-03-16 08:48:21 +0100101source "board/congatec/Kconfig"
Bin Meng03b341b2015-04-27 23:22:24 +0800102source "board/coreboot/Kconfig"
Stefan Roese312dc932016-08-15 13:50:49 +0200103source "board/dfi/Kconfig"
Ben Stoltz19c23fd2015-08-04 12:33:47 -0600104source "board/efi/Kconfig"
Bin Meng2229c4c2015-05-07 21:34:08 +0800105source "board/emulation/Kconfig"
Bin Meng03b341b2015-04-27 23:22:24 +0800106source "board/google/Kconfig"
107source "board/intel/Kconfig"
108
Bin Meng6e8ddec2015-04-27 23:22:25 +0800109# platform-specific options below
Simon Glassfcc2ce92019-12-08 17:40:17 -0700110source "arch/x86/cpu/apollolake/Kconfig"
Bin Meng6e8ddec2015-04-27 23:22:25 +0800111source "arch/x86/cpu/baytrail/Kconfig"
Bin Meng68a070b2017-08-15 22:41:58 -0700112source "arch/x86/cpu/braswell/Kconfig"
Simon Glass71606de2016-03-11 22:07:18 -0700113source "arch/x86/cpu/broadwell/Kconfig"
Bin Meng6e8ddec2015-04-27 23:22:25 +0800114source "arch/x86/cpu/coreboot/Kconfig"
115source "arch/x86/cpu/ivybridge/Kconfig"
Bin Meng525c8612018-06-12 08:36:16 -0700116source "arch/x86/cpu/efi/Kconfig"
Bin Meng2229c4c2015-05-07 21:34:08 +0800117source "arch/x86/cpu/qemu/Kconfig"
Bin Meng6e8ddec2015-04-27 23:22:25 +0800118source "arch/x86/cpu/quark/Kconfig"
119source "arch/x86/cpu/queensbay/Kconfig"
Park, Aiden6e3cc362019-08-03 08:30:12 +0000120source "arch/x86/cpu/slimbootloader/Kconfig"
Felipe Balbie564d592017-07-06 14:41:52 +0300121source "arch/x86/cpu/tangier/Kconfig"
Bin Meng6e8ddec2015-04-27 23:22:25 +0800122
123# architecture-specific options below
124
Simon Glass85ee1652016-05-01 11:35:52 -0600125config AHCI
126 default y
127
Simon Glass838723b2015-02-11 16:32:59 -0700128config SYS_MALLOC_F_LEN
129 default 0x800
130
Simon Glass98f139b2014-11-12 22:42:10 -0700131config RAMBASE
132 hex
133 default 0x100000
134
Simon Glass98f139b2014-11-12 22:42:10 -0700135config XIP_ROM_SIZE
136 hex
Bin Meng4cf0b472015-01-06 22:14:16 +0800137 depends on X86_RESET_VECTOR
Simon Glassd9b083e2015-01-01 16:17:54 -0700138 default ROM_SIZE
Simon Glass98f139b2014-11-12 22:42:10 -0700139
140config CPU_ADDR_BITS
141 int
142 default 36
143
Simon Glass268eefd2014-11-12 22:42:28 -0700144config HPET_ADDRESS
145 hex
146 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
147
148config SMM_TSEG
149 bool
Simon Glass268eefd2014-11-12 22:42:28 -0700150
151config SMM_TSEG_SIZE
152 hex
153
Bin Menga11937c2015-01-06 22:14:15 +0800154config X86_RESET_VECTOR
155 bool
Masahiro Yamada87247af2017-10-17 13:42:44 +0900156 select BINMAN
Bin Menga11937c2015-01-06 22:14:15 +0800157
Simon Glass095a8632017-01-16 07:03:44 -0700158# The following options control where the 16-bit and 32-bit init lies
159# If SPL is enabled then it normally holds this init code, and U-Boot proper
160# is normally a 64-bit build.
161#
162# The 16-bit init refers to the reset vector and the small amount of code to
163# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
164# or missing altogether if U-Boot is started from EFI or coreboot.
165#
166# The 32-bit init refers to processor init, running binary blobs including
167# FSP, setting up interrupts and anything else that needs to be done in
168# 32-bit code. It is normally in the same place as 16-bit init if that is
169# enabled (i.e. they are both in SPL, or both in U-Boot proper).
170config X86_16BIT_INIT
171 bool
172 depends on X86_RESET_VECTOR
173 default y if X86_RESET_VECTOR && !SPL
174 help
175 This is enabled when 16-bit init is in U-Boot proper
176
177config SPL_X86_16BIT_INIT
178 bool
179 depends on X86_RESET_VECTOR
Simon Glass71bc4c62019-04-25 21:58:46 -0600180 default y if X86_RESET_VECTOR && SPL && !TPL
Simon Glass095a8632017-01-16 07:03:44 -0700181 help
182 This is enabled when 16-bit init is in SPL
183
Simon Glass71bc4c62019-04-25 21:58:46 -0600184config TPL_X86_16BIT_INIT
185 bool
186 depends on X86_RESET_VECTOR
187 default y if X86_RESET_VECTOR && TPL
188 help
189 This is enabled when 16-bit init is in TPL
190
Simon Glass095a8632017-01-16 07:03:44 -0700191config X86_32BIT_INIT
192 bool
193 depends on X86_RESET_VECTOR
194 default y if X86_RESET_VECTOR && !SPL
195 help
196 This is enabled when 32-bit init is in U-Boot proper
197
198config SPL_X86_32BIT_INIT
199 bool
200 depends on X86_RESET_VECTOR
201 default y if X86_RESET_VECTOR && SPL
202 help
203 This is enabled when 32-bit init is in SPL
204
Andy Shevchenko3e902442020-08-20 13:02:20 +0300205config USE_EARLY_BOARD_INIT
206 bool
207
Bin Meng51b0f622015-06-07 11:33:12 +0800208config RESET_SEG_START
209 hex
210 depends on X86_RESET_VECTOR
211 default 0xffff0000
212
Bin Meng51b0f622015-06-07 11:33:12 +0800213config RESET_VEC_LOC
214 hex
215 depends on X86_RESET_VECTOR
216 default 0xfffffff0
217
Bin Menga11937c2015-01-06 22:14:15 +0800218config SYS_X86_START16
219 hex
220 depends on X86_RESET_VECTOR
221 default 0xfffff800
222
Simon Glass7dbabbb2019-12-06 21:42:24 -0700223config HAVE_X86_FIT
224 bool
225 help
226 Enable inclusion of an Intel Firmware Interface Table (FIT) into the
227 image. This table is supposed to point to microcode and the like. So
228 far it is just a fixed table with the minimum set of headers, so that
229 it is actually present.
230
Andy Shevchenko2ae7da02017-02-05 16:52:00 +0300231config X86_LOAD_FROM_32_BIT
232 bool "Boot from a 32-bit program"
233 help
234 Define this to boot U-Boot from a 32-bit program which sets
235 the GDT differently. This can be used to boot directly from
236 any stage of coreboot, for example, bypassing the normal
237 payload-loading feature.
238
Bin Mengc191ab72014-12-12 21:05:19 +0800239config BOARD_ROMSIZE_KB_512
240 bool
241config BOARD_ROMSIZE_KB_1024
242 bool
243config BOARD_ROMSIZE_KB_2048
244 bool
245config BOARD_ROMSIZE_KB_4096
246 bool
247config BOARD_ROMSIZE_KB_8192
248 bool
249config BOARD_ROMSIZE_KB_16384
250 bool
251
252choice
253 prompt "ROM chip size"
Bin Meng4cf0b472015-01-06 22:14:16 +0800254 depends on X86_RESET_VECTOR
Bin Mengc191ab72014-12-12 21:05:19 +0800255 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
256 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
257 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
258 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
259 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
260 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
261 help
262 Select the size of the ROM chip you intend to flash U-Boot on.
263
264 The build system will take care of creating a u-boot.rom file
265 of the matching size.
266
267config UBOOT_ROMSIZE_KB_512
268 bool "512 KB"
269 help
270 Choose this option if you have a 512 KB ROM chip.
271
272config UBOOT_ROMSIZE_KB_1024
273 bool "1024 KB (1 MB)"
274 help
275 Choose this option if you have a 1024 KB (1 MB) ROM chip.
276
277config UBOOT_ROMSIZE_KB_2048
278 bool "2048 KB (2 MB)"
279 help
280 Choose this option if you have a 2048 KB (2 MB) ROM chip.
281
282config UBOOT_ROMSIZE_KB_4096
283 bool "4096 KB (4 MB)"
284 help
285 Choose this option if you have a 4096 KB (4 MB) ROM chip.
286
287config UBOOT_ROMSIZE_KB_8192
288 bool "8192 KB (8 MB)"
289 help
290 Choose this option if you have a 8192 KB (8 MB) ROM chip.
291
292config UBOOT_ROMSIZE_KB_16384
293 bool "16384 KB (16 MB)"
294 help
295 Choose this option if you have a 16384 KB (16 MB) ROM chip.
296
297endchoice
298
299# Map the config names to an integer (KB).
300config UBOOT_ROMSIZE_KB
301 int
302 default 512 if UBOOT_ROMSIZE_KB_512
303 default 1024 if UBOOT_ROMSIZE_KB_1024
304 default 2048 if UBOOT_ROMSIZE_KB_2048
305 default 4096 if UBOOT_ROMSIZE_KB_4096
306 default 8192 if UBOOT_ROMSIZE_KB_8192
307 default 16384 if UBOOT_ROMSIZE_KB_16384
308
309# Map the config names to a hex value (bytes).
Simon Glass6622b342014-11-12 22:42:08 -0700310config ROM_SIZE
311 hex
Bin Mengc191ab72014-12-12 21:05:19 +0800312 default 0x80000 if UBOOT_ROMSIZE_KB_512
313 default 0x100000 if UBOOT_ROMSIZE_KB_1024
314 default 0x200000 if UBOOT_ROMSIZE_KB_2048
315 default 0x400000 if UBOOT_ROMSIZE_KB_4096
316 default 0x800000 if UBOOT_ROMSIZE_KB_8192
317 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
318 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
Simon Glass6622b342014-11-12 22:42:08 -0700319
320config HAVE_INTEL_ME
321 bool "Platform requires Intel Management Engine"
322 help
323 Newer higher-end devices have an Intel Management Engine (ME)
324 which is a very large binary blob (typically 1.5MB) which is
325 required for the platform to work. This enforces a particular
326 SPI flash format. You will need to supply the me.bin file in
327 your board directory.
328
Simon Glass268eefd2014-11-12 22:42:28 -0700329config X86_RAMTEST
330 bool "Perform a simple RAM test after SDRAM initialisation"
331 help
332 If there is something wrong with SDRAM then the platform will
333 often crash within U-Boot or the kernel. This option enables a
334 very simple RAM test that quickly checks whether the SDRAM seems
335 to work correctly. It is not exhaustive but can save time by
336 detecting obvious failures.
337
Stefan Roesef8cc43a2017-03-30 12:58:10 +0200338config FLASH_DESCRIPTOR_FILE
339 string "Flash descriptor binary filename"
Simon Glass466c7852019-12-06 21:42:18 -0700340 depends on HAVE_INTEL_ME || FSP_VERSION2
Stefan Roesef8cc43a2017-03-30 12:58:10 +0200341 default "descriptor.bin"
342 help
343 The filename of the file to use as flash descriptor in the
344 board directory.
345
346config INTEL_ME_FILE
347 string "Intel Management Engine binary filename"
348 depends on HAVE_INTEL_ME
349 default "me.bin"
350 help
351 The filename of the file to use as Intel Management Engine in the
352 board directory.
353
Park, Aiden6e3cc362019-08-03 08:30:12 +0000354config USE_HOB
355 bool "Use HOB (Hand-Off Block)"
356 help
357 Select this option to access HOB (Hand-Off Block) data structures
358 and parse HOBs. This HOB infra structure can be reused with
359 different solutions across different platforms.
360
Simon Glass45c083b2015-01-27 22:13:41 -0700361config HAVE_FSP
362 bool "Add an Firmware Support Package binary"
Simon Glass2b6d80b2015-08-04 12:34:00 -0600363 depends on !EFI
Park, Aiden6e3cc362019-08-03 08:30:12 +0000364 select USE_HOB
Simon Glassf69c0092020-07-19 13:55:52 -0600365 select HAS_ROM
Simon Glass45c083b2015-01-27 22:13:41 -0700366 help
367 Select this option to add an Firmware Support Package binary to
368 the resulting U-Boot image. It is a binary blob which U-Boot uses
369 to set up SDRAM and other chipset specific initialization.
370
371 Note: Without this binary U-Boot will not be able to set up its
372 SDRAM so will not boot.
373
Simon Glass9e60b432019-09-25 08:11:43 -0600374config USE_CAR
375 bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up"
376 default y if !HAVE_FSP
377 help
378 Select this option if your board uses CAR init code, typically in a
379 car.S file, to get some initial memory for code execution. This is
380 common with Intel CPUs which don't use FSP.
381
Simon Glass6c34fc12019-09-25 08:00:11 -0600382choice
383 prompt "FSP version"
384 depends on HAVE_FSP
385 default FSP_VERSION1
386 help
387 Selects the FSP version to use. Intel has published several versions
388 of the FSP External Architecture Specification and this allows
389 selection of the version number used by a particular SoC.
390
391config FSP_VERSION1
392 bool "FSP version 1.x"
393 help
394 This covers versions 1.0 and 1.1a. See here for details:
395 https://github.com/IntelFsp/fsp/wiki
396
397config FSP_VERSION2
398 bool "FSP version 2.x"
Tom Rini7d3684a2023-01-16 15:46:49 -0500399 select DM_EVENT
Simon Glass6c34fc12019-09-25 08:00:11 -0600400 help
401 This covers versions 2.0 and 2.1. See here for details:
402 https://github.com/IntelFsp/fsp/wiki
403
404endchoice
405
Simon Glass45c083b2015-01-27 22:13:41 -0700406config FSP_FILE
407 string "Firmware Support Package binary filename"
Simon Glass1efffd62019-09-25 08:57:14 -0600408 depends on FSP_VERSION1
Simon Glass45c083b2015-01-27 22:13:41 -0700409 default "fsp.bin"
410 help
411 The filename of the file to use as Firmware Support Package binary
412 in the board directory.
413
414config FSP_ADDR
415 hex "Firmware Support Package binary location"
Simon Glass1efffd62019-09-25 08:57:14 -0600416 depends on FSP_VERSION1
Simon Glass45c083b2015-01-27 22:13:41 -0700417 default 0xfffc0000
418 help
419 FSP is not Position Independent Code (PIC) and the whole FSP has to
420 be rebased if it is placed at a location which is different from the
421 perferred base address specified during the FSP build. Use Intel's
422 Binary Configuration Tool (BCT) to do the rebase.
423
424 The default base address of 0xfffc0000 indicates that the binary must
425 be located at offset 0xc0000 from the beginning of a 1MB flash device.
426
Simon Glass466c7852019-12-06 21:42:18 -0700427if FSP_VERSION2
428
429config FSP_FILE_T
430 string "Firmware Support Package binary filename (Temp RAM)"
431 default "fsp_t.bin"
432 help
433 The filename of the file to use for the temporary-RAM init phase from
434 the Firmware Support Package binary. Put this in the board directory.
435 It is used to set up an initial area of RAM which can be used for the
436 stack and other purposes, while bringing up the main system DRAM.
437
438config FSP_ADDR_T
439 hex "Firmware Support Package binary location (Temp RAM)"
440 default 0xffff8000
441 help
442 FSP is not Position-Independent Code (PIC) and FSP components have to
443 be rebased if placed at a location which is different from the
444 perferred base address specified during the FSP build. Use Intel's
445 Binary Configuration Tool (BCT) to do the rebase.
446
447config FSP_FILE_M
448 string "Firmware Support Package binary filename (Memory Init)"
449 default "fsp_m.bin"
450 help
451 The filename of the file to use for the RAM init phase from the
452 Firmware Support Package binary. Put this in the board directory.
453 It is used to set up the main system DRAM and runs in SPL, once
454 temporary RAM (CAR) is working.
455
456config FSP_FILE_S
457 string "Firmware Support Package binary filename (Silicon Init)"
458 default "fsp_s.bin"
459 help
460 The filename of the file to use for the Silicon init phase from the
461 Firmware Support Package binary. Put this in the board directory.
462 It is used to set up the silicon to work correctly and must be
463 executed after DRAM is running.
464
465config IFWI_INPUT_FILE
466 string "Filename containing FIT (Firmware Interface Table) with IFWI"
467 default "fitimage.bin"
468 help
469 The IFWI is obtained by running a tool on this file to extract the
470 IFWI. Put this in the board directory. The IFWI contains U-Boot TPL,
471 microcode and other internal items.
472
473endif
474
Simon Glass45c083b2015-01-27 22:13:41 -0700475config FSP_TEMP_RAM_ADDR
476 hex
Simon Glass1efffd62019-09-25 08:57:14 -0600477 depends on FSP_VERSION1
Simon Glass45c083b2015-01-27 22:13:41 -0700478 default 0x2000000
479 help
Bin Meng73574dc2015-08-20 06:40:20 -0700480 Stack top address which is used in fsp_init() after DRAM is ready and
Simon Glass45c083b2015-01-27 22:13:41 -0700481 CAR is disabled.
482
Bin Meng12440cd2015-08-20 06:40:19 -0700483config FSP_SYS_MALLOC_F_LEN
484 hex
Simon Glass1efffd62019-09-25 08:57:14 -0600485 depends on FSP_VERSION1
Bin Meng12440cd2015-08-20 06:40:19 -0700486 default 0x100000
487 help
488 Additional size of malloc() pool before relocation.
489
Bin Mengf9a61892015-12-10 22:03:01 -0800490config FSP_USE_UPD
491 bool
Simon Glass1efffd62019-09-25 08:57:14 -0600492 depends on FSP_VERSION1
Michal Simek4b198e32021-08-27 08:48:10 +0200493 default y if !NORTHBRIDGE_INTEL_IVYBRIDGE
Bin Mengf9a61892015-12-10 22:03:01 -0800494 help
495 Most FSPs use UPD data region for some FSP customization. But there
496 are still some FSPs that might not even have UPD. For such FSPs,
497 override this to n in their platform Kconfig files.
498
Bin Meng4c836c92016-02-17 00:16:23 -0800499config FSP_BROKEN_HOB
500 bool
Simon Glass1efffd62019-09-25 08:57:14 -0600501 depends on FSP_VERSION1
Bin Meng4c836c92016-02-17 00:16:23 -0800502 help
503 Indicate some buggy FSPs that does not report memory used by FSP
504 itself as reserved in the resource descriptor HOB. Select this to
505 tell U-Boot to do some additional work to ensure U-Boot relocation
506 do not overwrite the important boot service data which is used by
507 FSP, otherwise the subsequent call to fsp_notify() will fail.
508
Bin Meng0ffd7e52015-10-11 21:37:35 -0700509config ENABLE_MRC_CACHE
510 bool "Enable MRC cache"
511 depends on !EFI && !SYS_COREBOOT
512 help
513 Enable this feature to cause MRC data to be cached in NV storage
514 to be used for speeding up boot time on future reboots and/or
515 power cycles.
516
Bin Meng5e842af2016-05-22 01:45:27 -0700517 For platforms that use Intel FSP for the memory initialization,
518 please check FSP output HOB via U-Boot command 'fsp hob' to see
Simon Glass6c34fc12019-09-25 08:00:11 -0600519 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
Vagrant Cascadian973c0992019-05-03 14:28:37 -0800520 If such GUID does not exist, MRC cache is not available on such
Bin Meng5e842af2016-05-22 01:45:27 -0700521 platform (eg: Intel Queensbay), which means selecting this option
522 here does not make any difference.
523
Simon Glassd4e90742016-03-11 22:07:08 -0700524config HAVE_MRC
525 bool "Add a System Agent binary"
Simon Glassf69c0092020-07-19 13:55:52 -0600526 select HAS_ROM
Simon Glassd4e90742016-03-11 22:07:08 -0700527 depends on !HAVE_FSP
528 help
529 Select this option to add a System Agent binary to
530 the resulting U-Boot image. MRC stands for Memory Reference Code.
531 It is a binary blob which U-Boot uses to set up SDRAM.
532
533 Note: Without this binary U-Boot will not be able to set up its
534 SDRAM so will not boot.
535
536config CACHE_MRC_BIN
537 bool
538 depends on HAVE_MRC
Simon Glassd4e90742016-03-11 22:07:08 -0700539 help
540 Enable caching for the memory reference code binary. This uses an
541 MTRR (memory type range register) to turn on caching for the section
542 of SPI flash that contains the memory reference code. This makes
543 SDRAM init run faster.
544
545config CACHE_MRC_SIZE_KB
546 int
547 depends on HAVE_MRC
548 default 512
549 help
550 Sets the size of the cached area for the memory reference code.
551 This ends at the end of SPI flash (address 0xffffffff) and is
552 measured in KB. Typically this is set to 512, providing for 0.5MB
553 of cached space.
554
555config DCACHE_RAM_BASE
556 hex
557 depends on HAVE_MRC
558 help
559 Sets the base of the data cache area in memory space. This is the
560 start address of the cache-as-RAM (CAR) area and the address varies
561 depending on the CPU. Once CAR is set up, read/write memory becomes
562 available at this address and can be used temporarily until SDRAM
563 is working.
564
565config DCACHE_RAM_SIZE
566 hex
567 depends on HAVE_MRC
568 default 0x40000
569 help
570 Sets the total size of the data cache area in memory space. This
571 sets the size of the cache-as-RAM (CAR) area. Note that much of the
572 CAR space is required by the MRC. The CAR space available to U-Boot
573 is normally at the start and typically extends to 1/4 or 1/2 of the
574 available size.
575
576config DCACHE_RAM_MRC_VAR_SIZE
577 hex
578 depends on HAVE_MRC
579 help
580 This is the amount of CAR (Cache as RAM) reserved for use by the
581 memory reference code. This depends on the implementation of the
582 memory reference code and must be set correctly or the board will
583 not boot.
584
Simon Glassecae7fd2016-03-11 22:07:16 -0700585config HAVE_REFCODE
586 bool "Add a Reference Code binary"
587 help
588 Select this option to add a Reference Code binary to the resulting
589 U-Boot image. This is an Intel binary blob that handles system
590 initialisation, in this case the PCH and System Agent.
591
592 Note: Without this binary (on platforms that need it such as
593 broadwell) U-Boot will be missing some critical setup steps.
594 Various peripherals may fail to work.
595
Simon Glass3c4b98f2019-12-06 21:42:26 -0700596config HAVE_MICROCODE
Simon Glass0bd972a2020-07-19 13:56:17 -0600597 bool "Board requires a microcode binary"
Simon Glass3c4b98f2019-12-06 21:42:26 -0700598 default y if !FSP_VERSION2
Simon Glass0bd972a2020-07-19 13:56:17 -0600599 help
600 Enable this if the board requires microcode to be loaded on boot.
601 Typically this is handed by the FSP for modern boards, but for
602 some older boards, it must be programmed by U-Boot, and that form
603 part of the image.
Simon Glass3c4b98f2019-12-06 21:42:26 -0700604
Simon Glassa9a44262015-04-29 22:25:59 -0600605config SMP
606 bool "Enable Symmetric Multiprocessing"
Simon Glassa9a44262015-04-29 22:25:59 -0600607 help
608 Enable use of more than one CPU in U-Boot and the Operating System
609 when loaded. Each CPU will be started up and information can be
610 obtained using the 'cpu' command. If this option is disabled, then
611 only one CPU will be enabled regardless of the number of CPUs
612 available.
613
Simon Glass4a30bbb2020-07-17 08:48:16 -0600614config SMP_AP_WORK
615 bool
616 depends on SMP
617 help
618 Allow APs to do other work after initialisation instead of going
619 to sleep.
620
Bin Meng6bd24462015-06-12 14:52:23 +0800621config MAX_CPUS
622 int "Maximum number of CPUs permitted"
623 depends on SMP
624 default 4
625 help
626 When using multi-CPU chips it is possible for U-Boot to start up
627 more than one CPU. The stack memory used by all of these CPUs is
628 pre-allocated so at present U-Boot wants to know the maximum
629 number of CPUs that may be present. Set this to at least as high
630 as the number of CPUs in your system (it uses about 4KB of RAM for
631 each CPU).
632
Simon Glassa9a44262015-04-29 22:25:59 -0600633config AP_STACK_SIZE
634 hex
Bin Meng5ec10582015-06-12 14:52:22 +0800635 depends on SMP
Simon Glassa9a44262015-04-29 22:25:59 -0600636 default 0x1000
637 help
638 Each additional CPU started by U-Boot requires its own stack. This
639 option sets the stack size used by each CPU and directly affects
640 the memory used by this initialisation process. Typically 4KB is
641 enough space.
642
Bin Meng842c31e2017-08-17 01:10:42 -0700643config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
644 bool
645 help
646 This option indicates that the turbo mode setting is not package
647 scoped. i.e. turbo_enable() needs to be called on not just the
648 bootstrap processor (BSP).
649
Bin Meng4de38862015-07-06 16:31:33 +0800650config HAVE_VGA_BIOS
651 bool "Add a VGA BIOS image"
652 help
653 Select this option if you have a VGA BIOS image that you would
654 like to add to your ROM.
655
656config VGA_BIOS_FILE
657 string "VGA BIOS image filename"
658 depends on HAVE_VGA_BIOS
659 default "vga.bin"
660 help
661 The filename of the VGA BIOS image in the board directory.
662
663config VGA_BIOS_ADDR
664 hex "VGA BIOS image location"
665 depends on HAVE_VGA_BIOS
666 default 0xfff90000
667 help
668 The location of VGA BIOS image in the SPI flash. For example, base
669 address of 0xfff90000 indicates that the image will be put at offset
670 0x90000 from the beginning of a 1MB flash device.
671
Bin Meng61dc3e22017-08-15 22:41:53 -0700672config HAVE_VBT
673 bool "Add a Video BIOS Table (VBT) image"
Simon Glass466c7852019-12-06 21:42:18 -0700674 depends on HAVE_FSP
Bin Meng61dc3e22017-08-15 22:41:53 -0700675 help
676 Select this option if you have a Video BIOS Table (VBT) image that
677 you would like to add to your ROM. This is normally required if you
678 are using an Intel FSP firmware that is complaint with spec 1.1 or
679 later to initialize the integrated graphics device (IGD).
680
681 Video BIOS Table, or VBT, provides platform and board specific
682 configuration information to the driver that is not discoverable
683 or available through other means. By other means the most used
684 method here is to read EDID table from the attached monitor, over
685 Display Data Channel (DDC) using two pin I2C serial interface. VBT
686 configuration is related to display hardware and is available via
687 the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
688
689config VBT_FILE
690 string "Video BIOS Table (VBT) image filename"
691 depends on HAVE_VBT
692 default "vbt.bin"
693 help
694 The filename of the file to use as Video BIOS Table (VBT) image
695 in the board directory.
696
697config VBT_ADDR
698 hex "Video BIOS Table (VBT) image location"
699 depends on HAVE_VBT
700 default 0xfff90000
701 help
702 The location of Video BIOS Table (VBT) image in the SPI flash. For
703 example, base address of 0xfff90000 indicates that the image will
704 be put at offset 0x90000 from the beginning of a 1MB flash device.
705
Bin Meng1b35bc52017-08-15 22:41:56 -0700706config VIDEO_FSP
707 bool "Enable FSP framebuffer driver support"
Simon Glass52cb5042022-10-18 07:46:31 -0600708 depends on HAVE_VBT && VIDEO
Bin Meng1b35bc52017-08-15 22:41:56 -0700709 help
710 Turn on this option to enable a framebuffer driver when U-Boot is
711 using Video BIOS Table (VBT) image for FSP firmware to initialize
712 the integrated graphics device.
713
Andy Shevchenkoa364e622017-07-28 20:02:15 +0300714config ROM_TABLE_ADDR
715 hex
716 default 0xf0000
717 help
718 All x86 tables happen to like the address range from 0x0f0000
719 to 0x100000. We use 0xf0000 as the starting address to store
720 those tables, including PIRQ routing table, Multi-Processor
721 table and ACPI table.
722
723config ROM_TABLE_SIZE
724 hex
725 default 0x10000
726
Simon Glass0b226042024-01-04 08:10:39 -0700727config X86_HARDFP
728 bool "Support hardware floating point"
729 help
730 U-Boot generally does not make use of floating point. Where this is
731 needed, it can be enabled using this option. This adjusts the
732 start-up code for 64-bit mode and changes the compiler options for
733 64-bit to enable SSE.
734
Wolfgang Wallnerb5460dd2020-02-03 14:06:45 +0100735config HAVE_ITSS
736 bool "Enable ITSS"
737 help
738 Select this to include the driver for the Interrupt Timer
739 Subsystem (ITSS) which is found on several Intel devices.
740
Wolfgang Wallner21fae582020-02-04 09:04:56 +0100741config HAVE_P2SB
742 bool "Enable P2SB"
Wolfgang Wallnera7851852020-07-01 13:37:24 +0200743 depends on P2SB
Wolfgang Wallner21fae582020-02-04 09:04:56 +0100744 help
745 Select this to include the driver for the Primary to
746 Sideband Bridge (P2SB) which is found on several Intel
747 devices.
748
Bin Meng45236ad2015-04-24 18:10:05 +0800749menu "System tables"
Bin Mengfd53d3c2015-08-13 00:29:13 -0700750 depends on !EFI && !SYS_COREBOOT
Bin Meng45236ad2015-04-24 18:10:05 +0800751
752config GENERATE_PIRQ_TABLE
753 bool "Generate a PIRQ table"
Bin Meng45236ad2015-04-24 18:10:05 +0800754 help
755 Generate a PIRQ routing table for this board. The PIRQ routing table
756 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
757 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
758 It specifies the interrupt router information as well how all the PCI
759 devices' interrupt pins are wired to PIRQs.
760
Simon Glass07e922a2015-04-28 20:25:10 -0600761config GENERATE_SFI_TABLE
762 bool "Generate a SFI (Simple Firmware Interface) table"
763 help
764 The Simple Firmware Interface (SFI) provides a lightweight method
765 for platform firmware to pass information to the operating system
766 via static tables in memory. Kernel SFI support is required to
767 boot on SFI-only platforms. If you have ACPI tables then these are
768 used instead.
769
770 U-Boot writes this table in write_sfi_table() just before booting
771 the OS.
772
773 For more information, see http://simplefirmware.org
774
Bin Mengc4f407e2015-06-23 12:18:52 +0800775config GENERATE_MP_TABLE
776 bool "Generate an MP (Multi-Processor) table"
Bin Mengc4f407e2015-06-23 12:18:52 +0800777 help
778 Generate an MP (Multi-Processor) table for this board. The MP table
779 provides a way for the operating system to support for symmetric
780 multiprocessing as well as symmetric I/O interrupt handling with
781 the local APIC and I/O APIC.
782
Simon Glass6fe570a2020-09-22 12:44:53 -0600783config ACPI_GNVS_EXTERNAL
784 bool
785 help
786 Put the GNVS (Global Non-Volatile Sleeping) table separate from the
787 DSDT and add a pointer to the table from the DSDT. This allows
788 U-Boot to better control the address of the GNVS.
789
Bin Meng45236ad2015-04-24 18:10:05 +0800790endmenu
791
Bin Mengab702be2017-04-21 07:24:28 -0700792config HAVE_ACPI_RESUME
793 bool "Enable ACPI S3 resume"
Bin Meng21340ed2017-10-18 18:20:55 -0700794 select ENABLE_MRC_CACHE
Bin Mengab702be2017-04-21 07:24:28 -0700795 help
796 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
797 state where all system context is lost except system memory. U-Boot
798 is responsible for restoring the machine state as it was before sleep.
799 It needs restore the memory controller, without overwriting memory
800 which is not marked as reserved. For the peripherals which lose their
801 registers, U-Boot needs to write the original value. When everything
802 is done, U-Boot needs to find out the wakeup vector provided by OSes
803 and jump there.
804
Bin Meng62a8f7d2017-04-21 07:24:46 -0700805config S3_VGA_ROM_RUN
806 bool "Re-run VGA option ROMs on S3 resume"
807 depends on HAVE_ACPI_RESUME
Bin Meng62a8f7d2017-04-21 07:24:46 -0700808 help
809 Execute VGA option ROMs in U-Boot when resuming from S3. Normally
810 this is needed when graphics console is being used in the kernel.
811
812 Turning it off can reduce some resume time, but be aware that your
813 graphics console won't work without VGA options ROMs. Set it to N
814 if your kernel is only on a serial console.
815
Heinrich Schuchardt99186b32020-07-29 12:31:17 +0200816config STACK_SIZE_RESUME
Bin Meng212c7b22017-04-21 07:24:34 -0700817 hex
818 depends on HAVE_ACPI_RESUME
819 default 0x1000
820 help
821 Estimated U-Boot's runtime stack size that needs to be reserved
822 during an ACPI S3 resume.
823
Bin Meng45236ad2015-04-24 18:10:05 +0800824config MAX_PIRQ_LINKS
825 int
826 default 8
827 help
828 This variable specifies the number of PIRQ interrupt links which are
829 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
830 Some newer chipsets offer more than four links, commonly up to PIRQH.
831
832config IRQ_SLOT_COUNT
833 int
834 default 128
835 help
836 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
837 which in turns forms a table of exact 4KiB. The default value 128
838 should be enough for most boards. If this does not fit your board,
839 change it according to your needs.
840
Simon Glass461cebf2015-01-27 22:13:33 -0700841config PCIE_ECAM_BASE
842 hex
Bin Mengd11c1b22015-02-02 21:25:09 +0800843 default 0xe0000000
Simon Glass461cebf2015-01-27 22:13:33 -0700844 help
845 This is the memory-mapped address of PCI configuration space, which
846 is only available through the Enhanced Configuration Access
847 Mechanism (ECAM) with PCI Express. It can be set up almost
848 anywhere. Before it is set up, it is possible to access PCI
849 configuration space through I/O access, but memory access is more
850 convenient. Using this, PCI can be scanned and configured. This
851 should be set to a region that does not conflict with memory
852 assigned to PCI devices - i.e. the memory and prefetch regions, as
853 passed to pci_set_region().
854
Bin Mengcf40bd42015-07-22 01:21:15 -0700855config PCIE_ECAM_SIZE
856 hex
857 default 0x10000000
858 help
859 This is the size of memory-mapped address of PCI configuration space,
860 which is only available through the Enhanced Configuration Access
861 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
862 so a default 0x10000000 size covers all of the 256 buses which is the
863 maximum number of PCI buses as defined by the PCI specification.
864
Bin Meng70e41942015-10-22 19:13:31 -0700865config I8259_PIC
Bin Mengcda8aab2018-11-29 19:57:22 -0800866 bool "Enable Intel 8259 compatible interrupt controller"
Bin Meng70e41942015-10-22 19:13:31 -0700867 default y
868 help
869 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
870 slave) interrupt controllers. Include this to have U-Boot set up
871 the interrupt correctly.
872
Hannes Schmelzerd18df3c2018-11-18 23:19:43 +0100873config APIC
Bin Mengcda8aab2018-11-29 19:57:22 -0800874 bool "Enable Intel Advanced Programmable Interrupt Controller"
Hannes Schmelzerd18df3c2018-11-18 23:19:43 +0100875 default y
876 help
877 The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
878 for catching interrupts and distributing them to one or more CPU
879 cores. In most cases there are some LAPICs (local) for each core and
880 one I/O APIC. This conjunction is found on most modern x86 systems.
881
Bin Mengc253c3f2018-06-10 06:25:01 -0700882config PINCTRL_ICH6
883 bool
884 help
885 Intel ICH6 compatible chipset pinctrl driver. It needs to work
886 together with the ICH6 compatible gpio driver.
887
Bin Meng70e41942015-10-22 19:13:31 -0700888config I8254_TIMER
889 bool
890 default y
891 help
892 Intel 8254 timer contains three counters which have fixed uses.
893 Include this to have U-Boot set up the timer correctly.
894
Bin Meng96030fa2016-02-28 23:54:50 -0800895config SEABIOS
896 bool "Support booting SeaBIOS"
897 help
898 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
899 It can run in an emulator or natively on X86 hardware with the use
900 of coreboot/U-Boot. By turning on this option, U-Boot prepares
901 all the configuration tables that are necessary to boot SeaBIOS.
902
903 Check http://www.seabios.org/SeaBIOS for details.
904
Bin Meng322ec3e2016-05-11 07:44:59 -0700905config HIGH_TABLE_SIZE
906 hex "Size of configuration tables which reside in high memory"
907 default 0x10000
908 depends on SEABIOS
909 help
910 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
911 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
912 puts a copy of configuration tables in high memory region which
913 is reserved on the stack before relocation. The region size is
914 determined by this option.
915
916 Increse it if the default size does not fit the board's needs.
917 This is most likely due to a large ACPI DSDT table is used.
918
Simon Glass8f963e12019-12-06 21:42:25 -0700919config INTEL_CAR_CQOS
920 bool "Support Intel Cache Quality of Service"
921 help
922 Cache Quality of Service allows more fine-grained control of cache
923 usage. As result, it is possible to set up a portion of L2 cache for
924 CAR and use the remainder for actual caching.
925
926#
927# Each bit in QOS mask controls this many bytes. This is calculated as:
928# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
929#
930config CACHE_QOS_SIZE_PER_BIT
931 hex
932 depends on INTEL_CAR_CQOS
933 default 0x20000 # 128 KB
934
Simon Glass20af0ff2019-12-06 21:42:29 -0700935config X86_OFFSET_U_BOOT
936 hex "Offset of U-Boot in ROM image"
Simon Glass72cc5382022-10-20 18:22:39 -0600937 depends on HAVE_TEXT_BASE
938 default TEXT_BASE
Simon Glass20af0ff2019-12-06 21:42:29 -0700939
Simon Glass4d7a9232019-12-06 21:42:30 -0700940config X86_OFFSET_SPL
941 hex "Offset of SPL in ROM image"
942 depends on SPL && X86
943 default SPL_TEXT_BASE
944
Simon Glass98a4cb62020-02-06 09:55:01 -0700945config ACPI_GPE
946 bool "Support ACPI general-purpose events"
947 help
948 Enable a driver for ACPI GPEs to allow peripherals to send interrupts
949 via ACPI to the OS. In U-Boot this is only used when U-Boot itself
950 needs access to these interrupts. This can happen when it uses a
951 peripheral that is set up to use GPEs and so cannot use the normal
952 GPIO mechanism for polling an input.
953
954 See https://queue.acm.org/blogposting.cfm?id=18977 for more info
955
956config SPL_ACPI_GPE
957 bool "Support ACPI general-purpose events in SPL"
Tom Rini0a83cc22022-06-10 23:03:09 -0400958 depends on SPL
Simon Glass98a4cb62020-02-06 09:55:01 -0700959 help
960 Enable a driver for ACPI GPEs to allow peripherals to send interrupts
961 via ACPI to the OS. In U-Boot this is only used when U-Boot itself
962 needs access to these interrupts. This can happen when it uses a
963 peripheral that is set up to use GPEs and so cannot use the normal
964 GPIO mechanism for polling an input.
965
966 See https://queue.acm.org/blogposting.cfm?id=18977 for more info
967
968config TPL_ACPI_GPE
969 bool "Support ACPI general-purpose events in TPL"
Tom Rini36a4ca02022-06-08 08:24:39 -0400970 depends on TPL
Simon Glass98a4cb62020-02-06 09:55:01 -0700971 help
972 Enable a driver for ACPI GPEs to allow peripherals to send interrupts
973 via ACPI to the OS. In U-Boot this is only used when U-Boot itself
974 needs access to these interrupts. This can happen when it uses a
975 peripheral that is set up to use GPEs and so cannot use the normal
976 GPIO mechanism for polling an input.
977
978 See https://queue.acm.org/blogposting.cfm?id=18977 for more info
979
Simon Glass741ce462020-09-22 12:44:51 -0600980config SA_PCIEX_LENGTH
981 hex
982 default 0x10000000 if (PCIEX_LENGTH_256MB)
983 default 0x8000000 if (PCIEX_LENGTH_128MB)
984 default 0x4000000 if (PCIEX_LENGTH_64MB)
985 default 0x10000000
986 help
987 This option allows you to select length of PCIEX region.
988
989config PCIEX_LENGTH_256MB
990 bool
991
992config PCIEX_LENGTH_128MB
993 bool
994
995config PCIEX_LENGTH_64MB
996 bool
997
Simon Glassc6eeff92021-02-23 05:35:42 -0500998config INTEL_SOC
999 bool
1000 help
1001 This is enabled on Intel SoCs that can support various advanced
1002 features such as power management (requiring asm/arch/pm.h), system
1003 agent (asm/arch/systemagent.h) and an I/O map for ACPI
1004 (asm/arch/iomap.h).
1005
1006 This cannot be selected in a defconfig file. It must be enabled by a
1007 'select' in the SoC's Kconfig.
1008
1009if INTEL_SOC
1010
Simon Glassbabc9f12021-02-23 05:35:41 -05001011config INTEL_ACPIGEN
1012 bool "Support ACPI table generation for Intel SoCs"
1013 depends on ACPIGEN
1014 help
1015 This option adds some functions used for programmatic generation of
1016 ACPI tables on Intel SoCs. This provides features for writing CPU
1017 information such as P states and T stages. Also included is a way
1018 to create a GNVS table and set it up.
1019
Simon Glass057427c2020-09-22 12:45:03 -06001020config INTEL_GMA_ACPI
1021 bool "Generate ACPI table for Intel GMA graphics"
1022 help
1023 The Intel GMA graphics driver in Linux expects an ACPI table
1024 which describes the layout of the registers and the display
1025 connected to the device. Enable this option to create this
1026 table so that graphics works correctly.
1027
Simon Glass4c69a5f2020-09-22 12:45:04 -06001028config INTEL_GENERIC_WIFI
1029 bool "Enable generation of ACPI tables for Intel WiFi"
1030 help
1031 Select this option to provide code to a build generic WiFi ACPI table
1032 for Intel WiFi devices. This is not a WiFi driver and offers no
1033 network functionality. It is only here to generate the ACPI tables
1034 required by Linux.
1035
Simon Glassc32fbb62020-09-22 12:45:15 -06001036config INTEL_GMA_SWSMISCI
1037 bool
1038 help
1039 Select this option for Atom-based platforms which use the SWSMISCI
1040 register (0xe0) rather than the SWSCI register (0xe8).
1041
Simon Glassc6eeff92021-02-23 05:35:42 -05001042endif # INTEL_SOC
1043
Simon Glassb7f8bad2021-03-15 18:00:21 +13001044config COREBOOT_SYSINFO
1045 bool "Support reading coreboot sysinfo"
1046 default y if SYS_COREBOOT
1047 help
1048 Select this option to read the coreboot sysinfo table on start-up,
1049 if present. This is written by coreboot before it exits and provides
1050 various pieces of information about the running system, including
1051 display, memory and build information. It is stored in
1052 struct sysinfo_t after parsing by get_coreboot_info().
1053
1054config SPL_COREBOOT_SYSINFO
1055 bool "Support reading coreboot sysinfo"
1056 depends on SPL
1057 default y if COREBOOT_SYSINFO
1058 help
1059 Select this option to read the coreboot sysinfo table in SPL,
1060 if present. This is written by coreboot before it exits and provides
1061 various pieces of information about the running system, including
1062 display, memory and build information. It is stored in
1063 struct sysinfo_t after parsing by get_coreboot_info().
1064
Simon Glassc90a4062023-12-03 17:29:28 -07001065config ZBOOT
1066 bool "Support the zImage format"
1067 default y
1068 help
1069 Enable this to support booting the x86-specific zImage format. This
1070 uses a special, binary format containing information about the Linux
1071 format to boot.
1072
Masahiro Yamadad3ae6782014-07-30 14:08:14 +09001073endmenu