x86: Add support for newer CAR schemes
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.
To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index bcce111..44f7f0a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -879,4 +879,20 @@
Increse it if the default size does not fit the board's needs.
This is most likely due to a large ACPI DSDT table is used.
+config INTEL_CAR_CQOS
+ bool "Support Intel Cache Quality of Service"
+ help
+ Cache Quality of Service allows more fine-grained control of cache
+ usage. As result, it is possible to set up a portion of L2 cache for
+ CAR and use the remainder for actual caching.
+
+#
+# Each bit in QOS mask controls this many bytes. This is calculated as:
+# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
+#
+config CACHE_QOS_SIZE_PER_BIT
+ hex
+ depends on INTEL_CAR_CQOS
+ default 0x20000 # 128 KB
+
endmenu