blob: 060b02accc5ccad5a7d516c060bca62503266a04 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wolfgang Grandegger1859b702012-02-08 22:33:25 +00002/*
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
Wolfgang Grandegger1859b702012-02-08 22:33:25 +00005 */
6
7#include <common.h>
Marek Vasutf22fde72021-03-31 12:28:03 +02008#include <clk.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000010#include <usb.h>
11#include <errno.h>
Mateusz Kulikowski4073b832016-01-23 11:54:32 +010012#include <wait_bit.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000014#include <linux/compiler.h>
Simon Glassdbd79542020-05-10 11:40:11 -060015#include <linux/delay.h>
Mateusz Kulikowski3add69e2016-03-31 23:12:23 +020016#include <usb/ehci-ci.h>
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000017#include <asm/io.h>
18#include <asm/arch/imx-regs.h>
19#include <asm/arch/clock.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020020#include <asm/mach-imx/iomux-v3.h>
21#include <asm/mach-imx/sys_proto.h>
Peng Fan5c363c12016-06-17 14:19:27 +080022#include <dm.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -060023#include <asm/mach-types.h>
Peng Fan13351332016-12-22 17:06:43 +080024#include <power/regulator.h>
Adam Ford15287f02019-04-03 08:41:56 -050025#include <linux/usb/otg.h>
Matthias Schiffer6eff2422021-09-20 15:37:25 +020026#include <linux/usb/phy.h>
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000027
28#include "ehci.h"
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000029
Peng Fan9e3eab32016-12-22 17:06:42 +080030DECLARE_GLOBAL_DATA_PTR;
31
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000032#define USB_OTGREGS_OFFSET 0x000
33#define USB_H1REGS_OFFSET 0x200
34#define USB_H2REGS_OFFSET 0x400
35#define USB_H3REGS_OFFSET 0x600
36#define USB_OTHERREGS_OFFSET 0x800
37
38#define USB_H1_CTRL_OFFSET 0x04
39
40#define USBPHY_CTRL 0x00000030
41#define USBPHY_CTRL_SET 0x00000034
42#define USBPHY_CTRL_CLR 0x00000038
43#define USBPHY_CTRL_TOG 0x0000003c
44
45#define USBPHY_PWD 0x00000000
46#define USBPHY_CTRL_SFTRST 0x80000000
47#define USBPHY_CTRL_CLKGATE 0x40000000
48#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
49#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
Troy Kiskyed72a9e2013-10-10 15:27:59 -070050#define USBPHY_CTRL_OTG_ID 0x08000000
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000051
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000052#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
53#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
54
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000055#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
56#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
57#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
58#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
59
Adrian Alonsof31599f2015-08-06 15:43:17 -050060#define USBNC_OFFSET 0x200
Peng Fan9e3eab32016-12-22 17:06:42 +080061#define USBNC_PHY_STATUS_OFFSET 0x23C
Adrian Alonsof31599f2015-08-06 15:43:17 -050062#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
63#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
Stefan Agner475cf912016-07-13 00:25:37 -070064#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000065#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
66#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
67
68/* USBCMD */
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000069#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
70#define UCMD_RESET (1 << 1) /* controller reset */
71
Marek Vasut5fc0d352021-04-10 16:03:04 +020072/* If this is not defined, assume MX6/MX7/MX8M SoC default */
73#ifndef CONFIG_MXC_USB_PORTSC
74#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
75#endif
76
Marek Vasut793e5752021-03-31 22:19:00 +020077/* Base address for this IP block is 0x02184800 */
78struct usbnc_regs {
79 u32 ctrl[4]; /* otg/host1-3 */
80 u32 uh2_hsic_ctrl;
81 u32 uh3_hsic_ctrl;
82 u32 otg_phy_ctrl_0;
83 u32 uh1_phy_ctrl_0;
84 u32 reserve1[4];
85 u32 phy_cfg1;
86 u32 phy_cfg2;
87 u32 reserve2;
88 u32 phy_status;
89 u32 reserve3[4];
90 u32 adp_cfg1;
91 u32 adp_cfg2;
92 u32 adp_status;
93};
94
Marek Vasut41e81392021-03-31 23:00:23 +020095#if defined(CONFIG_MX6) && !defined(CONFIG_PHY)
96static void usb_power_config_mx6(struct anatop_regs __iomem *anatop,
97 int anatop_bits_index)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000098{
Troy Kiskyed72a9e2013-10-10 15:27:59 -070099 void __iomem *chrg_detect;
100 void __iomem *pll_480_ctrl_clr;
101 void __iomem *pll_480_ctrl_set;
102
Marek Vasut41e81392021-03-31 23:00:23 +0200103 if (!is_mx6())
104 return;
105
106 switch (anatop_bits_index) {
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700107 case 0:
108 chrg_detect = &anatop->usb1_chrg_detect;
109 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
110 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
111 break;
112 case 1:
113 chrg_detect = &anatop->usb2_chrg_detect;
114 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
115 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
116 break;
117 default:
118 return;
119 }
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000120 /*
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700121 * Some phy and power's special controls
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000122 * 1. The external charger detector needs to be disabled
123 * or the signal at DP will be poor
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700124 * 2. The PLL's power and output to usb
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000125 * is totally controlled by IC, so the Software only needs
126 * to enable them at initializtion.
127 */
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500128 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000129 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700130 chrg_detect);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000131
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500132 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700133 pll_480_ctrl_clr);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000134
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500135 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000136 ANADIG_USB2_PLL_480_CTRL_POWER |
137 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700138 pll_480_ctrl_set);
Marek Vasut41e81392021-03-31 23:00:23 +0200139}
140#else
141static void __maybe_unused
142usb_power_config_mx6(void *anatop, int anatop_bits_index) { }
143#endif
Ye Li9da57ea2019-10-24 10:29:32 -0300144
Marek Vasut41e81392021-03-31 23:00:23 +0200145#if defined(CONFIG_MX7) && !defined(CONFIG_PHY)
146static void usb_power_config_mx7(struct usbnc_regs *usbnc)
147{
148 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
149
150 if (!is_mx7())
151 return;
152
153 /*
154 * Clear the ACAENB to enable usb_otg_id detection,
155 * otherwise it is the ACA detection enabled.
156 */
157 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
158}
159#else
160static void __maybe_unused
161usb_power_config_mx7(void *usbnc) { }
Ye Li9da57ea2019-10-24 10:29:32 -0300162#endif
Marek Vasut41e81392021-03-31 23:00:23 +0200163
164#if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
165static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
166{
167 if (!is_mx7ulp())
168 return;
169
170 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
171 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
172 &usbphy->usb1_chrg_detect);
173
174 scg_enable_usb_pll(true);
175}
176#else
177static void __maybe_unused
178usb_power_config_mx7ulp(void *usbphy) { }
179#endif
180
Giulio Benetti13ded2c2021-05-20 16:10:15 +0200181#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
Marek Vasut41e81392021-03-31 23:00:23 +0200182static const unsigned phy_bases[] = {
183 USB_PHY0_BASE_ADDR,
184#if defined(USB_PHY1_BASE_ADDR)
185 USB_PHY1_BASE_ADDR,
186#endif
187};
188
189#if !defined(CONFIG_PHY)
190static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
191{
192 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
193 writel(USBPHY_CTRL_CLKGATE, phy_reg);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000194}
195
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700196/* Return 0 : host node, <>0 : device mode */
Marek Vasut6b6df642021-03-31 22:10:35 +0200197static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000198{
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700199 void __iomem *phy_ctrl;
200 void __iomem *usb_cmd;
Adrian Alonsoc52eb1c2015-08-06 15:46:03 -0500201 int ret;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000202
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700203 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
204 usb_cmd = (void __iomem *)&ehci->usbcmd;
205
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000206 /* Stop then Reset */
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500207 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100208 ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
Adrian Alonsoc52eb1c2015-08-06 15:46:03 -0500209 if (ret)
210 return ret;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000211
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500212 setbits_le32(usb_cmd, UCMD_RESET);
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100213 ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
Adrian Alonsoc52eb1c2015-08-06 15:46:03 -0500214 if (ret)
215 return ret;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000216
217 /* Reset USBPHY module */
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500218 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000219 udelay(10);
220
221 /* Remove CLKGATE and SFTRST */
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500222 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000223 udelay(10);
224
225 /* Power up the PHY */
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500226 writel(0, phy_reg + USBPHY_PWD);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000227 /* enable FS/LS device */
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500228 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
229 USBPHY_CTRL_ENUTMILEVEL3);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000230
Peng Fan220402e2014-11-10 08:50:39 +0800231 return 0;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000232}
Marek Vasut41e81392021-03-31 23:00:23 +0200233#endif
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000234
Adrian Alonsof31599f2015-08-06 15:43:17 -0500235int usb_phy_mode(int port)
236{
237 void __iomem *phy_reg;
238 void __iomem *phy_ctrl;
239 u32 val;
240
241 phy_reg = (void __iomem *)phy_bases[port];
242 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
243
244 val = readl(phy_ctrl);
245
246 if (val & USBPHY_CTRL_OTG_ID)
247 return USB_INIT_DEVICE;
248 else
249 return USB_INIT_HOST;
250}
251
Adrian Alonsof31599f2015-08-06 15:43:17 -0500252#elif defined(CONFIG_MX7)
Adrian Alonsof31599f2015-08-06 15:43:17 -0500253int usb_phy_mode(int port)
254{
255 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
256 (0x10000 * port) + USBNC_OFFSET);
257 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
258 u32 val;
259
260 val = readl(status);
261
262 if (val & USBNC_PHYSTATUS_ID_DIG)
263 return USB_INIT_DEVICE;
264 else
265 return USB_INIT_HOST;
266}
267#endif
268
Marek Vasut09603b92021-04-22 21:06:40 +0200269#if !defined(CONFIG_PHY)
270/* Should be done in the MXS PHY driver */
Marek Vasut1fa42432021-03-31 23:24:41 +0200271static void usb_oc_config(struct usbnc_regs *usbnc, int index)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000272{
Marek Vasut793e5752021-03-31 22:19:00 +0200273 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000274
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000275#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
276 /* mx6qarm2 seems to required a different setting*/
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500277 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000278#else
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500279 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000280#endif
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000281
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500282 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
Ye Li9da57ea2019-10-24 10:29:32 -0300283
284 /* Set power polarity to high active */
285#ifdef CONFIG_MXC_USB_OTG_HACTIVE
286 setbits_le32(ctrl, UCTRL_PWR_POL);
287#else
288 clrbits_le32(ctrl, UCTRL_PWR_POL);
289#endif
Peng Fan220402e2014-11-10 08:50:39 +0800290}
Marek Vasut09603b92021-04-22 21:06:40 +0200291#endif
Peng Fan220402e2014-11-10 08:50:39 +0800292
Marek Vasut09dc0702021-03-31 21:40:24 +0200293#if !CONFIG_IS_ENABLED(DM_USB)
Adrian Alonso14dfbbb2015-08-06 15:43:16 -0500294/**
Stefan Agner3dfd3a02016-05-05 16:59:12 -0700295 * board_usb_phy_mode - override usb phy mode
Adrian Alonso14dfbbb2015-08-06 15:43:16 -0500296 * @port: usb host/otg port
297 *
298 * Target board specific, override usb_phy_mode.
299 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
300 * left disconnected in this case usb_phy_mode will not be able to identify
301 * the phy mode that usb port is used.
302 * Machine file overrides board_usb_phy_mode.
303 *
304 * Return: USB_INIT_DEVICE or USB_INIT_HOST
305 */
Peng Fan220402e2014-11-10 08:50:39 +0800306int __weak board_usb_phy_mode(int port)
307{
308 return usb_phy_mode(port);
309}
310
Adrian Alonso14dfbbb2015-08-06 15:43:16 -0500311/**
312 * board_ehci_hcd_init - set usb vbus voltage
313 * @port: usb otg port
314 *
315 * Target board specific, setup iomux pad to setup supply vbus voltage
316 * for usb otg port. Machine board file overrides board_ehci_hcd_init
317 *
318 * Return: 0 Success
319 */
Benoît Thébaudeau98023c12012-11-13 09:58:35 +0000320int __weak board_ehci_hcd_init(int port)
321{
322 return 0;
323}
324
Adrian Alonso14dfbbb2015-08-06 15:43:16 -0500325/**
326 * board_ehci_power - enables/disables usb vbus voltage
327 * @port: usb otg port
328 * @on: on/off vbus voltage
329 *
330 * Enables/disables supply vbus voltage for usb otg port.
331 * Machine board file overrides board_ehci_power
332 *
333 * Return: 0 Success
334 */
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700335int __weak board_ehci_power(int port, int on)
336{
Peng Fan5c363c12016-06-17 14:19:27 +0800337 return 0;
338}
339
Troy Kisky7d6bbb92013-10-10 15:27:57 -0700340int ehci_hcd_init(int index, enum usb_init_type init,
341 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000342{
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700343 enum usb_init_type type;
Giulio Benetti13ded2c2021-05-20 16:10:15 +0200344#if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
Adrian Alonsof31599f2015-08-06 15:43:17 -0500345 u32 controller_spacing = 0x200;
Marek Vasut41e81392021-03-31 23:00:23 +0200346 struct anatop_regs __iomem *anatop =
347 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
Marek Vasut1fa42432021-03-31 23:24:41 +0200348 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
349 USB_OTHERREGS_OFFSET);
Marek Vasut41e81392021-03-31 23:00:23 +0200350#elif defined(CONFIG_MX7)
351 u32 controller_spacing = 0x10000;
352 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
353 (0x10000 * index) + USBNC_OFFSET);
354#elif defined(CONFIG_MX7ULP)
Adrian Alonsof31599f2015-08-06 15:43:17 -0500355 u32 controller_spacing = 0x10000;
Marek Vasut41e81392021-03-31 23:00:23 +0200356 struct usbphy_regs __iomem *usbphy =
357 (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
Marek Vasut1fa42432021-03-31 23:24:41 +0200358 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
359 (0x10000 * index) + USBNC_OFFSET);
Adrian Alonsof31599f2015-08-06 15:43:17 -0500360#endif
Ye.Lif93453a2014-09-15 17:23:14 +0800361 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
Adrian Alonsof31599f2015-08-06 15:43:17 -0500362 (controller_spacing * index));
Stefan Agner3dfd3a02016-05-05 16:59:12 -0700363 int ret;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000364
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700365 if (index > 3)
366 return -EINVAL;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000367
Peng Fanf8b27192020-05-01 22:08:36 +0800368 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
369 if (usb_fused((ulong)ehci)) {
370 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
371 (ulong)ehci);
372 return -ENODEV;
373 }
374 }
375
Marek Vasutf22fde72021-03-31 12:28:03 +0200376 enable_usboh3_clk(1);
377 mdelay(1);
378
Marek Vasut09dc0702021-03-31 21:40:24 +0200379 /* Do board specific initialization */
380 ret = board_ehci_hcd_init(index);
381 if (ret) {
382 enable_usboh3_clk(0);
Stefan Agner3dfd3a02016-05-05 16:59:12 -0700383 return ret;
Marek Vasut09dc0702021-03-31 21:40:24 +0200384 }
385
Giulio Benetti13ded2c2021-05-20 16:10:15 +0200386#if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
Marek Vasut41e81392021-03-31 23:00:23 +0200387 usb_power_config_mx6(anatop, index);
388#elif defined (CONFIG_MX7)
389 usb_power_config_mx7(usbnc);
390#elif defined (CONFIG_MX7ULP)
391 usb_power_config_mx7ulp(usbphy);
392#endif
393
Marek Vasut1fa42432021-03-31 23:24:41 +0200394 usb_oc_config(usbnc, index);
Marek Vasut09dc0702021-03-31 21:40:24 +0200395
Giulio Benetti13ded2c2021-05-20 16:10:15 +0200396#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
Marek Vasut6b6df642021-03-31 22:10:35 +0200397 if (index < ARRAY_SIZE(phy_bases)) {
398 usb_internal_phy_clock_gate((void __iomem *)phy_bases[index], 1);
399 usb_phy_enable(ehci, (void __iomem *)phy_bases[index]);
400 }
Marek Vasut09dc0702021-03-31 21:40:24 +0200401#endif
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000402
Peng Fan220402e2014-11-10 08:50:39 +0800403 type = board_usb_phy_mode(index);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000404
Peng Fan5c363c12016-06-17 14:19:27 +0800405 if (hccr && hcor) {
Marek Vasuta60258f2021-04-06 20:37:16 +0200406 *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
407 *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
Peng Fan5c363c12016-06-17 14:19:27 +0800408 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
409 }
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000410
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700411 if ((type == init) || (type == USB_INIT_DEVICE))
412 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
413 if (type != init)
414 return -ENODEV;
415 if (type == USB_INIT_DEVICE)
416 return 0;
Adrian Alonsof31599f2015-08-06 15:43:17 -0500417
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700418 setbits_le32(&ehci->usbmode, CM_HOST);
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500419 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000420 setbits_le32(&ehci->portsc, USB_EN);
421
422 mdelay(10);
423
424 return 0;
425}
426
Lucas Stach3494a4c2012-09-26 00:14:35 +0200427int ehci_hcd_stop(int index)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000428{
Peng Fan5c363c12016-06-17 14:19:27 +0800429 return 0;
430}
431#else
432struct ehci_mx6_priv_data {
433 struct ehci_ctrl ctrl;
434 struct usb_ehci *ehci;
Peng Fan13351332016-12-22 17:06:43 +0800435 struct udevice *vbus_supply;
Marek Vasutf22fde72021-03-31 12:28:03 +0200436 struct clk clk;
Marek Vasut4e216512021-04-02 13:07:49 +0200437 struct phy phy;
Peng Fan5c363c12016-06-17 14:19:27 +0800438 enum usb_init_type init_type;
Matthias Schiffer6eff2422021-09-20 15:37:25 +0200439 enum usb_phy_interface phy_type;
Marek Vasut09603b92021-04-22 21:06:40 +0200440#if !defined(CONFIG_PHY)
Peng Fan5c363c12016-06-17 14:19:27 +0800441 int portnr;
Marek Vasutebaf3ae2021-03-31 23:06:07 +0200442 void __iomem *phy_addr;
443 void __iomem *misc_addr;
444 void __iomem *anatop_addr;
Marek Vasut09603b92021-04-22 21:06:40 +0200445#endif
Peng Fan5c363c12016-06-17 14:19:27 +0800446};
447
Matthias Schiffer6eff2422021-09-20 15:37:25 +0200448static u32 mx6_portsc(enum usb_phy_interface phy_type)
449{
450 switch (phy_type) {
451 case USBPHY_INTERFACE_MODE_UTMI:
452 return PORT_PTS_UTMI;
453 case USBPHY_INTERFACE_MODE_UTMIW:
454 return PORT_PTS_UTMI | PORT_PTS_PTW;
455 case USBPHY_INTERFACE_MODE_ULPI:
456 return PORT_PTS_ULPI;
457 case USBPHY_INTERFACE_MODE_SERIAL:
458 return PORT_PTS_SERIAL;
459 case USBPHY_INTERFACE_MODE_HSIC:
460 return PORT_PTS_HSIC;
461 default:
462 return CONFIG_MXC_USB_PORTSC;
463 }
464}
465
Peng Fan5c363c12016-06-17 14:19:27 +0800466static int mx6_init_after_reset(struct ehci_ctrl *dev)
467{
468 struct ehci_mx6_priv_data *priv = dev->priv;
469 enum usb_init_type type = priv->init_type;
470 struct usb_ehci *ehci = priv->ehci;
Peng Fan5c363c12016-06-17 14:19:27 +0800471
Marek Vasut41e81392021-03-31 23:00:23 +0200472#if !defined(CONFIG_PHY)
473 usb_power_config_mx6(priv->anatop_addr, priv->portnr);
474 usb_power_config_mx7(priv->misc_addr);
475 usb_power_config_mx7ulp(priv->phy_addr);
Marek Vasut41e81392021-03-31 23:00:23 +0200476
Marek Vasut1fa42432021-03-31 23:24:41 +0200477 usb_oc_config(priv->misc_addr, priv->portnr);
Marek Vasut09dc0702021-03-31 21:40:24 +0200478
Marek Vasut09603b92021-04-22 21:06:40 +0200479#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
Marek Vasut6b6df642021-03-31 22:10:35 +0200480 usb_internal_phy_clock_gate(priv->phy_addr, 1);
481 usb_phy_enable(ehci, priv->phy_addr);
Marek Vasut09dc0702021-03-31 21:40:24 +0200482#endif
Marek Vasut09603b92021-04-22 21:06:40 +0200483#endif
Peng Fan5c363c12016-06-17 14:19:27 +0800484
Abel Vesa888a9462019-02-01 16:40:08 +0000485#if CONFIG_IS_ENABLED(DM_REGULATOR)
Peng Fan13351332016-12-22 17:06:43 +0800486 if (priv->vbus_supply) {
Marek Vasut09dc0702021-03-31 21:40:24 +0200487 int ret;
Peng Fan13351332016-12-22 17:06:43 +0800488 ret = regulator_set_enable(priv->vbus_supply,
489 (type == USB_INIT_DEVICE) ?
490 false : true);
Marek Vasut27370452020-05-21 23:32:23 +0200491 if (ret && ret != -ENOSYS) {
Marek Vasuta86d51a2020-05-21 23:34:06 +0200492 printf("Error enabling VBUS supply (ret=%i)\n", ret);
Peng Fan13351332016-12-22 17:06:43 +0800493 return ret;
494 }
495 }
Abel Vesa888a9462019-02-01 16:40:08 +0000496#endif
Peng Fan5c363c12016-06-17 14:19:27 +0800497
498 if (type == USB_INIT_DEVICE)
499 return 0;
500
501 setbits_le32(&ehci->usbmode, CM_HOST);
Matthias Schiffer6eff2422021-09-20 15:37:25 +0200502 writel(mx6_portsc(priv->phy_type), &ehci->portsc);
Peng Fan5c363c12016-06-17 14:19:27 +0800503 setbits_le32(&ehci->portsc, USB_EN);
504
505 mdelay(10);
506
507 return 0;
508}
509
510static const struct ehci_ops mx6_ehci_ops = {
511 .init_after_reset = mx6_init_after_reset
512};
513
Peng Fan9e3eab32016-12-22 17:06:42 +0800514static int ehci_usb_phy_mode(struct udevice *dev)
515{
Simon Glassb75b15b2020-12-03 16:55:23 -0700516 struct usb_plat *plat = dev_get_plat(dev);
Masahiro Yamada1096ae12020-07-17 14:36:46 +0900517 void *__iomem addr = dev_read_addr_ptr(dev);
Peng Fan9e3eab32016-12-22 17:06:42 +0800518 void *__iomem phy_ctrl, *__iomem phy_status;
519 const void *blob = gd->fdt_blob;
Simon Glassdd79d6e2017-01-17 16:52:55 -0700520 int offset = dev_of_offset(dev), phy_off;
Peng Fan9e3eab32016-12-22 17:06:42 +0800521 u32 val;
522
523 /*
524 * About fsl,usbphy, Refer to
525 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
526 */
Giulio Benetti13ded2c2021-05-20 16:10:15 +0200527 if (is_mx6() || is_mx7ulp() || is_imxrt()) {
Peng Fan9e3eab32016-12-22 17:06:42 +0800528 phy_off = fdtdec_lookup_phandle(blob,
529 offset,
530 "fsl,usbphy");
531 if (phy_off < 0)
532 return -EINVAL;
533
534 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
535 "reg");
536 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
537 return -EINVAL;
538
539 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
540 val = readl(phy_ctrl);
541
542 if (val & USBPHY_CTRL_OTG_ID)
543 plat->init_type = USB_INIT_DEVICE;
544 else
545 plat->init_type = USB_INIT_HOST;
Adam Ford33da95a2022-02-03 15:20:11 -0600546 } else if (is_mx7() || is_imx8mm() || is_imx8mn()) {
Peng Fan9e3eab32016-12-22 17:06:42 +0800547 phy_status = (void __iomem *)(addr +
548 USBNC_PHY_STATUS_OFFSET);
549 val = readl(phy_status);
550
551 if (val & USBNC_PHYSTATUS_ID_DIG)
552 plat->init_type = USB_INIT_DEVICE;
553 else
554 plat->init_type = USB_INIT_HOST;
555 } else {
556 return -EINVAL;
557 }
558
559 return 0;
560}
561
Simon Glassaad29ae2020-12-03 16:55:21 -0700562static int ehci_usb_of_to_plat(struct udevice *dev)
Peng Fan9e3eab32016-12-22 17:06:42 +0800563{
Simon Glassb75b15b2020-12-03 16:55:23 -0700564 struct usb_plat *plat = dev_get_plat(dev);
Adam Ford15287f02019-04-03 08:41:56 -0500565 enum usb_dr_mode dr_mode;
Peng Fan9e3eab32016-12-22 17:06:42 +0800566
Simon Glassa7ece582020-12-19 10:40:14 -0700567 dr_mode = usb_get_dr_mode(dev_ofnode(dev));
Peng Fan9e3eab32016-12-22 17:06:42 +0800568
Adam Ford15287f02019-04-03 08:41:56 -0500569 switch (dr_mode) {
570 case USB_DR_MODE_HOST:
571 plat->init_type = USB_INIT_HOST;
572 break;
573 case USB_DR_MODE_PERIPHERAL:
574 plat->init_type = USB_INIT_DEVICE;
575 break;
Adam Ford33da95a2022-02-03 15:20:11 -0600576 default:
577 plat->init_type = USB_INIT_UNKNOWN;
Adam Ford15287f02019-04-03 08:41:56 -0500578 };
Peng Fan9e3eab32016-12-22 17:06:42 +0800579
Adam Ford15287f02019-04-03 08:41:56 -0500580 return 0;
Peng Fan9e3eab32016-12-22 17:06:42 +0800581}
582
Marek Vasutebaf3ae2021-03-31 23:06:07 +0200583static int mx6_parse_dt_addrs(struct udevice *dev)
584{
Marek Vasut09603b92021-04-22 21:06:40 +0200585#if !defined(CONFIG_PHY)
Marek Vasutebaf3ae2021-03-31 23:06:07 +0200586 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
587 int phy_off, misc_off;
588 const void *blob = gd->fdt_blob;
589 int offset = dev_of_offset(dev);
590 void *__iomem addr;
591
592 phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy");
593 if (phy_off < 0) {
594 phy_off = fdtdec_lookup_phandle(blob, offset, "phys");
595 if (phy_off < 0)
596 return -EINVAL;
597 }
598
599 misc_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbmisc");
600 if (misc_off < 0)
601 return -EINVAL;
602
603 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
604 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
Fabio Estevamf88939c2021-06-20 12:00:52 -0300605 addr = NULL;
Marek Vasutebaf3ae2021-03-31 23:06:07 +0200606
607 priv->phy_addr = addr;
608
609 addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
610 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
611 return -EINVAL;
612
613 priv->misc_addr = addr;
614
Marek Vasut09603b92021-04-22 21:06:40 +0200615#if defined(CONFIG_MX6)
Fabio Estevam759126c2021-06-20 12:00:51 -0300616 int anatop_off, ret, devnump;
617
618 ret = fdtdec_get_alias_seq(blob, dev->uclass->uc_drv->name,
619 phy_off, &devnump);
620 if (ret < 0)
621 return ret;
622 priv->portnr = devnump;
Marek Vasutebaf3ae2021-03-31 23:06:07 +0200623
624 /* Resolve ANATOP offset through USB PHY node */
625 anatop_off = fdtdec_lookup_phandle(blob, phy_off, "fsl,anatop");
626 if (anatop_off < 0)
627 return -EINVAL;
628
629 addr = (void __iomem *)fdtdec_get_addr(blob, anatop_off, "reg");
630 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
631 return -EINVAL;
632
633 priv->anatop_addr = addr;
634#endif
Marek Vasut09603b92021-04-22 21:06:40 +0200635#endif
Marek Vasutebaf3ae2021-03-31 23:06:07 +0200636 return 0;
637}
638
Peng Fan5c363c12016-06-17 14:19:27 +0800639static int ehci_usb_probe(struct udevice *dev)
640{
Simon Glassb75b15b2020-12-03 16:55:23 -0700641 struct usb_plat *plat = dev_get_plat(dev);
Masahiro Yamada1096ae12020-07-17 14:36:46 +0900642 struct usb_ehci *ehci = dev_read_addr_ptr(dev);
Peng Fan5c363c12016-06-17 14:19:27 +0800643 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
Peng Fan13351332016-12-22 17:06:43 +0800644 enum usb_init_type type = plat->init_type;
Peng Fan5c363c12016-06-17 14:19:27 +0800645 struct ehci_hccr *hccr;
646 struct ehci_hcor *hcor;
647 int ret;
648
Peng Fanf8b27192020-05-01 22:08:36 +0800649 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
650 if (usb_fused((ulong)ehci)) {
651 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
652 (ulong)ehci);
653 return -ENODEV;
654 }
655 }
656
Marek Vasutebaf3ae2021-03-31 23:06:07 +0200657 ret = mx6_parse_dt_addrs(dev);
658 if (ret)
659 return ret;
660
Peng Fan5c363c12016-06-17 14:19:27 +0800661 priv->ehci = ehci;
Peng Fan13351332016-12-22 17:06:43 +0800662 priv->init_type = type;
Matthias Schiffer6eff2422021-09-20 15:37:25 +0200663 priv->phy_type = usb_get_phy_mode(dev_ofnode(dev));
Peng Fan13351332016-12-22 17:06:43 +0800664
Marek Vasutf22fde72021-03-31 12:28:03 +0200665#if CONFIG_IS_ENABLED(CLK)
666 ret = clk_get_by_index(dev, 0, &priv->clk);
667 if (ret < 0)
668 return ret;
669
670 ret = clk_enable(&priv->clk);
671 if (ret)
672 return ret;
673#else
674 /* Compatibility with DM_USB and !CLK */
675 enable_usboh3_clk(1);
676 mdelay(1);
677#endif
678
Adam Ford33da95a2022-02-03 15:20:11 -0600679 /*
680 * If the device tree didn't specify host or device,
681 * the default is USB_INIT_UNKNOWN, so we need to check
682 * the register. For imx8mm and imx8mn, the clocks need to be
683 * running first, so we defer the check until they are.
684 */
685 if (priv->init_type == USB_INIT_UNKNOWN) {
686 ret = ehci_usb_phy_mode(dev);
687 if (ret)
688 goto err_clk;
689 else
690 priv->init_type = plat->init_type;
691 }
692
Abel Vesa888a9462019-02-01 16:40:08 +0000693#if CONFIG_IS_ENABLED(DM_REGULATOR)
Peng Fan13351332016-12-22 17:06:43 +0800694 ret = device_get_supply_regulator(dev, "vbus-supply",
695 &priv->vbus_supply);
696 if (ret)
697 debug("%s: No vbus supply\n", dev->name);
Abel Vesa888a9462019-02-01 16:40:08 +0000698#endif
Marek Vasut09dc0702021-03-31 21:40:24 +0200699
Marek Vasut41e81392021-03-31 23:00:23 +0200700#if !defined(CONFIG_PHY)
701 usb_power_config_mx6(priv->anatop_addr, priv->portnr);
702 usb_power_config_mx7(priv->misc_addr);
703 usb_power_config_mx7ulp(priv->phy_addr);
Marek Vasut41e81392021-03-31 23:00:23 +0200704
Marek Vasut1fa42432021-03-31 23:24:41 +0200705 usb_oc_config(priv->misc_addr, priv->portnr);
Marek Vasut09dc0702021-03-31 21:40:24 +0200706
Giulio Benetti13ded2c2021-05-20 16:10:15 +0200707#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
Marek Vasut6b6df642021-03-31 22:10:35 +0200708 usb_internal_phy_clock_gate(priv->phy_addr, 1);
709 usb_phy_enable(ehci, priv->phy_addr);
Marek Vasut09dc0702021-03-31 21:40:24 +0200710#endif
Marek Vasut09603b92021-04-22 21:06:40 +0200711#endif
Peng Fan5c363c12016-06-17 14:19:27 +0800712
Abel Vesa888a9462019-02-01 16:40:08 +0000713#if CONFIG_IS_ENABLED(DM_REGULATOR)
Peng Fan13351332016-12-22 17:06:43 +0800714 if (priv->vbus_supply) {
715 ret = regulator_set_enable(priv->vbus_supply,
716 (type == USB_INIT_DEVICE) ?
717 false : true);
Marek Vasut27370452020-05-21 23:32:23 +0200718 if (ret && ret != -ENOSYS) {
Marek Vasuta86d51a2020-05-21 23:34:06 +0200719 printf("Error enabling VBUS supply (ret=%i)\n", ret);
Marek Vasutf22fde72021-03-31 12:28:03 +0200720 goto err_clk;
Peng Fan13351332016-12-22 17:06:43 +0800721 }
722 }
Abel Vesa888a9462019-02-01 16:40:08 +0000723#endif
Peng Fan5c363c12016-06-17 14:19:27 +0800724
725 if (priv->init_type == USB_INIT_HOST) {
726 setbits_le32(&ehci->usbmode, CM_HOST);
Matthias Schiffer6eff2422021-09-20 15:37:25 +0200727 writel(mx6_portsc(priv->phy_type), &ehci->portsc);
Peng Fan5c363c12016-06-17 14:19:27 +0800728 setbits_le32(&ehci->portsc, USB_EN);
729 }
730
731 mdelay(10);
732
Marek Vasut4e216512021-04-02 13:07:49 +0200733#if defined(CONFIG_PHY)
734 ret = ehci_setup_phy(dev, &priv->phy, 0);
735 if (ret)
736 goto err_regulator;
737#endif
738
Marek Vasuta60258f2021-04-06 20:37:16 +0200739 hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
740 hcor = (struct ehci_hcor *)((uintptr_t)hccr +
Peng Fan5c363c12016-06-17 14:19:27 +0800741 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
742
Marek Vasutf36841e2021-03-31 12:19:27 +0200743 ret = ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
744 if (ret)
Marek Vasut4e216512021-04-02 13:07:49 +0200745 goto err_phy;
Marek Vasutf36841e2021-03-31 12:19:27 +0200746
747 return ret;
748
Marek Vasut4e216512021-04-02 13:07:49 +0200749err_phy:
750#if defined(CONFIG_PHY)
751 ehci_shutdown_phy(dev, &priv->phy);
Marek Vasutf36841e2021-03-31 12:19:27 +0200752err_regulator:
Marek Vasut4e216512021-04-02 13:07:49 +0200753#endif
Marek Vasutf36841e2021-03-31 12:19:27 +0200754#if CONFIG_IS_ENABLED(DM_REGULATOR)
755 if (priv->vbus_supply)
756 regulator_set_enable(priv->vbus_supply, false);
Marek Vasut4e216512021-04-02 13:07:49 +0200757#endif
Adam Ford33da95a2022-02-03 15:20:11 -0600758err_clk:
Marek Vasutf22fde72021-03-31 12:28:03 +0200759#if CONFIG_IS_ENABLED(CLK)
760 clk_disable(&priv->clk);
761#else
762 /* Compatibility with DM_USB and !CLK */
763 enable_usboh3_clk(0);
764#endif
Marek Vasutf36841e2021-03-31 12:19:27 +0200765 return ret;
766}
767
768int ehci_usb_remove(struct udevice *dev)
769{
770 struct ehci_mx6_priv_data *priv __maybe_unused = dev_get_priv(dev);
771
772 ehci_deregister(dev);
773
Marek Vasut4e216512021-04-02 13:07:49 +0200774#if defined(CONFIG_PHY)
775 ehci_shutdown_phy(dev, &priv->phy);
776#endif
777
Marek Vasutf36841e2021-03-31 12:19:27 +0200778#if CONFIG_IS_ENABLED(DM_REGULATOR)
779 if (priv->vbus_supply)
780 regulator_set_enable(priv->vbus_supply, false);
781#endif
782
Marek Vasutf22fde72021-03-31 12:28:03 +0200783#if CONFIG_IS_ENABLED(CLK)
784 clk_disable(&priv->clk);
785#endif
786
Marek Vasutf36841e2021-03-31 12:19:27 +0200787 return 0;
Peng Fan5c363c12016-06-17 14:19:27 +0800788}
789
Peng Fan5c363c12016-06-17 14:19:27 +0800790static const struct udevice_id mx6_usb_ids[] = {
791 { .compatible = "fsl,imx27-usb" },
Marek Vasutd650c552021-04-02 13:07:59 +0200792 { .compatible = "fsl,imx7d-usb" },
Giulio Benetti13ded2c2021-05-20 16:10:15 +0200793 { .compatible = "fsl,imxrt-usb" },
Peng Fan5c363c12016-06-17 14:19:27 +0800794 { }
795};
796
797U_BOOT_DRIVER(usb_mx6) = {
798 .name = "ehci_mx6",
799 .id = UCLASS_USB,
800 .of_match = mx6_usb_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700801 .of_to_plat = ehci_usb_of_to_plat,
Peng Fan5c363c12016-06-17 14:19:27 +0800802 .probe = ehci_usb_probe,
Marek Vasutf36841e2021-03-31 12:19:27 +0200803 .remove = ehci_usb_remove,
Peng Fan5c363c12016-06-17 14:19:27 +0800804 .ops = &ehci_usb_ops,
Simon Glassb75b15b2020-12-03 16:55:23 -0700805 .plat_auto = sizeof(struct usb_plat),
Simon Glass8a2b47f2020-12-03 16:55:17 -0700806 .priv_auto = sizeof(struct ehci_mx6_priv_data),
Peng Fan5c363c12016-06-17 14:19:27 +0800807 .flags = DM_FLAG_ALLOC_PRIV_DMA,
808};
809#endif