blob: 37b59758bb38c8901d104cdacaf7ecb2be44507a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wolfgang Grandegger1859b702012-02-08 22:33:25 +00002/*
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
Wolfgang Grandegger1859b702012-02-08 22:33:25 +00005 */
6
7#include <common.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
Wolfgang Grandegger1859b702012-02-08 22:33:25 +00009#include <usb.h>
10#include <errno.h>
Mateusz Kulikowski4073b832016-01-23 11:54:32 +010011#include <wait_bit.h>
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000012#include <linux/compiler.h>
Simon Glassdbd79542020-05-10 11:40:11 -060013#include <linux/delay.h>
Mateusz Kulikowski3add69e2016-03-31 23:12:23 +020014#include <usb/ehci-ci.h>
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000015#include <asm/io.h>
16#include <asm/arch/imx-regs.h>
17#include <asm/arch/clock.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020018#include <asm/mach-imx/iomux-v3.h>
19#include <asm/mach-imx/sys_proto.h>
Peng Fan5c363c12016-06-17 14:19:27 +080020#include <dm.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -060021#include <asm/mach-types.h>
Peng Fan13351332016-12-22 17:06:43 +080022#include <power/regulator.h>
Adam Ford15287f02019-04-03 08:41:56 -050023#include <linux/usb/otg.h>
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000024
25#include "ehci.h"
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000026
Peng Fan9e3eab32016-12-22 17:06:42 +080027DECLARE_GLOBAL_DATA_PTR;
28
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000029#define USB_OTGREGS_OFFSET 0x000
30#define USB_H1REGS_OFFSET 0x200
31#define USB_H2REGS_OFFSET 0x400
32#define USB_H3REGS_OFFSET 0x600
33#define USB_OTHERREGS_OFFSET 0x800
34
35#define USB_H1_CTRL_OFFSET 0x04
36
37#define USBPHY_CTRL 0x00000030
38#define USBPHY_CTRL_SET 0x00000034
39#define USBPHY_CTRL_CLR 0x00000038
40#define USBPHY_CTRL_TOG 0x0000003c
41
42#define USBPHY_PWD 0x00000000
43#define USBPHY_CTRL_SFTRST 0x80000000
44#define USBPHY_CTRL_CLKGATE 0x40000000
45#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
46#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
Troy Kiskyed72a9e2013-10-10 15:27:59 -070047#define USBPHY_CTRL_OTG_ID 0x08000000
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000048
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000049#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
50#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
51
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000052#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
53#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
54#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
55#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
56
Adrian Alonsof31599f2015-08-06 15:43:17 -050057#define USBNC_OFFSET 0x200
Peng Fan9e3eab32016-12-22 17:06:42 +080058#define USBNC_PHY_STATUS_OFFSET 0x23C
Adrian Alonsof31599f2015-08-06 15:43:17 -050059#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
60#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
Stefan Agner475cf912016-07-13 00:25:37 -070061#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000062#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
63#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
64
65/* USBCMD */
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000066#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
67#define UCMD_RESET (1 << 1) /* controller reset */
68
Ye Li9da57ea2019-10-24 10:29:32 -030069#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
Troy Kiskyed72a9e2013-10-10 15:27:59 -070070static const unsigned phy_bases[] = {
71 USB_PHY0_BASE_ADDR,
Ye Li9da57ea2019-10-24 10:29:32 -030072#if defined(USB_PHY1_BASE_ADDR)
Troy Kiskyed72a9e2013-10-10 15:27:59 -070073 USB_PHY1_BASE_ADDR,
Ye Li9da57ea2019-10-24 10:29:32 -030074#endif
Troy Kiskyed72a9e2013-10-10 15:27:59 -070075};
76
77static void usb_internal_phy_clock_gate(int index, int on)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000078{
Troy Kiskyed72a9e2013-10-10 15:27:59 -070079 void __iomem *phy_reg;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000080
Troy Kiskyed72a9e2013-10-10 15:27:59 -070081 if (index >= ARRAY_SIZE(phy_bases))
82 return;
83
84 phy_reg = (void __iomem *)phy_bases[index];
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000085 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
Adrian Alonsoaee79b42015-08-06 15:43:15 -050086 writel(USBPHY_CTRL_CLKGATE, phy_reg);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000087}
88
Troy Kiskyed72a9e2013-10-10 15:27:59 -070089static void usb_power_config(int index)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000090{
Ye Li9da57ea2019-10-24 10:29:32 -030091#if defined(CONFIG_MX7ULP)
92 struct usbphy_regs __iomem *usbphy =
93 (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
94
95 if (index > 0)
96 return;
97
98 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
99 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
100 &usbphy->usb1_chrg_detect);
101
102 scg_enable_usb_pll(true);
103
104#else
Wolfgang Grandegger5d113ca2012-05-02 04:36:39 +0000105 struct anatop_regs __iomem *anatop =
106 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700107 void __iomem *chrg_detect;
108 void __iomem *pll_480_ctrl_clr;
109 void __iomem *pll_480_ctrl_set;
110
111 switch (index) {
112 case 0:
113 chrg_detect = &anatop->usb1_chrg_detect;
114 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
115 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
116 break;
117 case 1:
118 chrg_detect = &anatop->usb2_chrg_detect;
119 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
120 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
121 break;
122 default:
123 return;
124 }
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000125 /*
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700126 * Some phy and power's special controls
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000127 * 1. The external charger detector needs to be disabled
128 * or the signal at DP will be poor
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700129 * 2. The PLL's power and output to usb
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000130 * is totally controlled by IC, so the Software only needs
131 * to enable them at initializtion.
132 */
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500133 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000134 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700135 chrg_detect);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000136
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500137 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700138 pll_480_ctrl_clr);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000139
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500140 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000141 ANADIG_USB2_PLL_480_CTRL_POWER |
142 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700143 pll_480_ctrl_set);
Ye Li9da57ea2019-10-24 10:29:32 -0300144
145#endif
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000146}
147
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700148/* Return 0 : host node, <>0 : device mode */
149static int usb_phy_enable(int index, struct usb_ehci *ehci)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000150{
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700151 void __iomem *phy_reg;
152 void __iomem *phy_ctrl;
153 void __iomem *usb_cmd;
Adrian Alonsoc52eb1c2015-08-06 15:46:03 -0500154 int ret;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000155
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700156 if (index >= ARRAY_SIZE(phy_bases))
157 return 0;
158
159 phy_reg = (void __iomem *)phy_bases[index];
160 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
161 usb_cmd = (void __iomem *)&ehci->usbcmd;
162
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000163 /* Stop then Reset */
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500164 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100165 ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
Adrian Alonsoc52eb1c2015-08-06 15:46:03 -0500166 if (ret)
167 return ret;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000168
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500169 setbits_le32(usb_cmd, UCMD_RESET);
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100170 ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
Adrian Alonsoc52eb1c2015-08-06 15:46:03 -0500171 if (ret)
172 return ret;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000173
174 /* Reset USBPHY module */
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500175 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000176 udelay(10);
177
178 /* Remove CLKGATE and SFTRST */
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500179 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000180 udelay(10);
181
182 /* Power up the PHY */
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500183 writel(0, phy_reg + USBPHY_PWD);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000184 /* enable FS/LS device */
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500185 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
186 USBPHY_CTRL_ENUTMILEVEL3);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000187
Peng Fan220402e2014-11-10 08:50:39 +0800188 return 0;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000189}
190
Adrian Alonsof31599f2015-08-06 15:43:17 -0500191int usb_phy_mode(int port)
192{
193 void __iomem *phy_reg;
194 void __iomem *phy_ctrl;
195 u32 val;
196
197 phy_reg = (void __iomem *)phy_bases[port];
198 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
199
200 val = readl(phy_ctrl);
201
202 if (val & USBPHY_CTRL_OTG_ID)
203 return USB_INIT_DEVICE;
204 else
205 return USB_INIT_HOST;
206}
207
Ye Li9da57ea2019-10-24 10:29:32 -0300208#if defined(CONFIG_MX7ULP)
209struct usbnc_regs {
210 u32 ctrl1;
211 u32 ctrl2;
212 u32 reserve0[2];
213 u32 hsic_ctrl;
214};
215#else
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700216/* Base address for this IP block is 0x02184800 */
217struct usbnc_regs {
218 u32 ctrl[4]; /* otg/host1-3 */
219 u32 uh2_hsic_ctrl;
220 u32 uh3_hsic_ctrl;
221 u32 otg_phy_ctrl_0;
222 u32 uh1_phy_ctrl_0;
223};
Ye Li9da57ea2019-10-24 10:29:32 -0300224#endif
225
Adrian Alonsof31599f2015-08-06 15:43:17 -0500226#elif defined(CONFIG_MX7)
227struct usbnc_regs {
228 u32 ctrl1;
229 u32 ctrl2;
230 u32 reserve1[10];
231 u32 phy_cfg1;
232 u32 phy_cfg2;
Peng Fan13186cf2016-06-20 09:43:08 +0800233 u32 reserve2;
Adrian Alonsof31599f2015-08-06 15:43:17 -0500234 u32 phy_status;
Peng Fan13186cf2016-06-20 09:43:08 +0800235 u32 reserve3[4];
Adrian Alonsof31599f2015-08-06 15:43:17 -0500236 u32 adp_cfg1;
237 u32 adp_cfg2;
238 u32 adp_status;
239};
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700240
Adrian Alonsof31599f2015-08-06 15:43:17 -0500241static void usb_power_config(int index)
242{
243 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
244 (0x10000 * index) + USBNC_OFFSET);
245 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
246
Peng Fan928d3d02016-06-20 09:43:09 +0800247 /*
248 * Clear the ACAENB to enable usb_otg_id detection,
249 * otherwise it is the ACA detection enabled.
250 */
251 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
Adrian Alonsof31599f2015-08-06 15:43:17 -0500252}
253
254int usb_phy_mode(int port)
255{
256 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
257 (0x10000 * port) + USBNC_OFFSET);
258 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
259 u32 val;
260
261 val = readl(status);
262
263 if (val & USBNC_PHYSTATUS_ID_DIG)
264 return USB_INIT_DEVICE;
265 else
266 return USB_INIT_HOST;
267}
268#endif
269
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700270static void usb_oc_config(int index)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000271{
Adrian Alonsof31599f2015-08-06 15:43:17 -0500272#if defined(CONFIG_MX6)
Ye.Lif93453a2014-09-15 17:23:14 +0800273 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700274 USB_OTHERREGS_OFFSET);
275 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
Ye Li9da57ea2019-10-24 10:29:32 -0300276#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
Adrian Alonsof31599f2015-08-06 15:43:17 -0500277 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
278 (0x10000 * index) + USBNC_OFFSET);
279 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
280#endif
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000281
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000282#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
283 /* mx6qarm2 seems to required a different setting*/
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500284 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000285#else
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500286 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000287#endif
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000288
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500289 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
Ye Li9da57ea2019-10-24 10:29:32 -0300290
291 /* Set power polarity to high active */
292#ifdef CONFIG_MXC_USB_OTG_HACTIVE
293 setbits_le32(ctrl, UCTRL_PWR_POL);
294#else
295 clrbits_le32(ctrl, UCTRL_PWR_POL);
296#endif
Peng Fan220402e2014-11-10 08:50:39 +0800297}
298
Adrian Alonso14dfbbb2015-08-06 15:43:16 -0500299/**
Stefan Agner3dfd3a02016-05-05 16:59:12 -0700300 * board_usb_phy_mode - override usb phy mode
Adrian Alonso14dfbbb2015-08-06 15:43:16 -0500301 * @port: usb host/otg port
302 *
303 * Target board specific, override usb_phy_mode.
304 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
305 * left disconnected in this case usb_phy_mode will not be able to identify
306 * the phy mode that usb port is used.
307 * Machine file overrides board_usb_phy_mode.
308 *
309 * Return: USB_INIT_DEVICE or USB_INIT_HOST
310 */
Peng Fan220402e2014-11-10 08:50:39 +0800311int __weak board_usb_phy_mode(int port)
312{
313 return usb_phy_mode(port);
314}
315
Adrian Alonso14dfbbb2015-08-06 15:43:16 -0500316/**
317 * board_ehci_hcd_init - set usb vbus voltage
318 * @port: usb otg port
319 *
320 * Target board specific, setup iomux pad to setup supply vbus voltage
321 * for usb otg port. Machine board file overrides board_ehci_hcd_init
322 *
323 * Return: 0 Success
324 */
Benoît Thébaudeau98023c12012-11-13 09:58:35 +0000325int __weak board_ehci_hcd_init(int port)
326{
327 return 0;
328}
329
Adrian Alonso14dfbbb2015-08-06 15:43:16 -0500330/**
331 * board_ehci_power - enables/disables usb vbus voltage
332 * @port: usb otg port
333 * @on: on/off vbus voltage
334 *
335 * Enables/disables supply vbus voltage for usb otg port.
336 * Machine board file overrides board_ehci_power
337 *
338 * Return: 0 Success
339 */
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700340int __weak board_ehci_power(int port, int on)
341{
342 return 0;
343}
344
Peng Fan5c363c12016-06-17 14:19:27 +0800345int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
346{
347 int ret;
348
349 enable_usboh3_clk(1);
350 mdelay(1);
351
352 /* Do board specific initialization */
353 ret = board_ehci_hcd_init(index);
354 if (ret)
355 return ret;
356
357 usb_power_config(index);
358 usb_oc_config(index);
359
Ye Li9da57ea2019-10-24 10:29:32 -0300360#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
Peng Fan5c363c12016-06-17 14:19:27 +0800361 usb_internal_phy_clock_gate(index, 1);
362 usb_phy_enable(index, ehci);
363#endif
364
365 return 0;
366}
367
Sven Schwermer8a3cb9f12018-11-21 08:43:56 +0100368#if !CONFIG_IS_ENABLED(DM_USB)
Troy Kisky7d6bbb92013-10-10 15:27:57 -0700369int ehci_hcd_init(int index, enum usb_init_type init,
370 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000371{
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700372 enum usb_init_type type;
Adrian Alonsof31599f2015-08-06 15:43:17 -0500373#if defined(CONFIG_MX6)
374 u32 controller_spacing = 0x200;
Ye Li9da57ea2019-10-24 10:29:32 -0300375#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
Adrian Alonsof31599f2015-08-06 15:43:17 -0500376 u32 controller_spacing = 0x10000;
377#endif
Ye.Lif93453a2014-09-15 17:23:14 +0800378 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
Adrian Alonsof31599f2015-08-06 15:43:17 -0500379 (controller_spacing * index));
Stefan Agner3dfd3a02016-05-05 16:59:12 -0700380 int ret;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000381
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700382 if (index > 3)
383 return -EINVAL;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000384
Peng Fanf8b27192020-05-01 22:08:36 +0800385 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
386 if (usb_fused((ulong)ehci)) {
387 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
388 (ulong)ehci);
389 return -ENODEV;
390 }
391 }
392
Peng Fan5c363c12016-06-17 14:19:27 +0800393 ret = ehci_mx6_common_init(ehci, index);
Stefan Agner3dfd3a02016-05-05 16:59:12 -0700394 if (ret)
395 return ret;
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000396
Peng Fan220402e2014-11-10 08:50:39 +0800397 type = board_usb_phy_mode(index);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000398
Peng Fan5c363c12016-06-17 14:19:27 +0800399 if (hccr && hcor) {
400 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
401 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
402 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
403 }
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000404
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700405 if ((type == init) || (type == USB_INIT_DEVICE))
406 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
407 if (type != init)
408 return -ENODEV;
409 if (type == USB_INIT_DEVICE)
410 return 0;
Adrian Alonsof31599f2015-08-06 15:43:17 -0500411
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700412 setbits_le32(&ehci->usbmode, CM_HOST);
Adrian Alonsoaee79b42015-08-06 15:43:15 -0500413 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000414 setbits_le32(&ehci->portsc, USB_EN);
415
416 mdelay(10);
417
418 return 0;
419}
420
Lucas Stach3494a4c2012-09-26 00:14:35 +0200421int ehci_hcd_stop(int index)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000422{
Peng Fan5c363c12016-06-17 14:19:27 +0800423 return 0;
424}
425#else
426struct ehci_mx6_priv_data {
427 struct ehci_ctrl ctrl;
428 struct usb_ehci *ehci;
Peng Fan13351332016-12-22 17:06:43 +0800429 struct udevice *vbus_supply;
Peng Fan5c363c12016-06-17 14:19:27 +0800430 enum usb_init_type init_type;
431 int portnr;
432};
433
434static int mx6_init_after_reset(struct ehci_ctrl *dev)
435{
436 struct ehci_mx6_priv_data *priv = dev->priv;
437 enum usb_init_type type = priv->init_type;
438 struct usb_ehci *ehci = priv->ehci;
439 int ret;
440
441 ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
442 if (ret)
443 return ret;
444
Abel Vesa888a9462019-02-01 16:40:08 +0000445#if CONFIG_IS_ENABLED(DM_REGULATOR)
Peng Fan13351332016-12-22 17:06:43 +0800446 if (priv->vbus_supply) {
447 ret = regulator_set_enable(priv->vbus_supply,
448 (type == USB_INIT_DEVICE) ?
449 false : true);
Marek Vasut27370452020-05-21 23:32:23 +0200450 if (ret && ret != -ENOSYS) {
Marek Vasuta86d51a2020-05-21 23:34:06 +0200451 printf("Error enabling VBUS supply (ret=%i)\n", ret);
Peng Fan13351332016-12-22 17:06:43 +0800452 return ret;
453 }
454 }
Abel Vesa888a9462019-02-01 16:40:08 +0000455#endif
Peng Fan5c363c12016-06-17 14:19:27 +0800456
457 if (type == USB_INIT_DEVICE)
458 return 0;
459
460 setbits_le32(&ehci->usbmode, CM_HOST);
461 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
462 setbits_le32(&ehci->portsc, USB_EN);
463
464 mdelay(10);
465
466 return 0;
467}
468
469static const struct ehci_ops mx6_ehci_ops = {
470 .init_after_reset = mx6_init_after_reset
471};
472
Peng Fan9e3eab32016-12-22 17:06:42 +0800473static int ehci_usb_phy_mode(struct udevice *dev)
474{
475 struct usb_platdata *plat = dev_get_platdata(dev);
Masahiro Yamada1096ae12020-07-17 14:36:46 +0900476 void *__iomem addr = dev_read_addr_ptr(dev);
Peng Fan9e3eab32016-12-22 17:06:42 +0800477 void *__iomem phy_ctrl, *__iomem phy_status;
478 const void *blob = gd->fdt_blob;
Simon Glassdd79d6e2017-01-17 16:52:55 -0700479 int offset = dev_of_offset(dev), phy_off;
Peng Fan9e3eab32016-12-22 17:06:42 +0800480 u32 val;
481
482 /*
483 * About fsl,usbphy, Refer to
484 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
485 */
Ye Li9da57ea2019-10-24 10:29:32 -0300486 if (is_mx6() || is_mx7ulp()) {
Peng Fan9e3eab32016-12-22 17:06:42 +0800487 phy_off = fdtdec_lookup_phandle(blob,
488 offset,
489 "fsl,usbphy");
490 if (phy_off < 0)
491 return -EINVAL;
492
493 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
494 "reg");
495 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
496 return -EINVAL;
497
498 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
499 val = readl(phy_ctrl);
500
501 if (val & USBPHY_CTRL_OTG_ID)
502 plat->init_type = USB_INIT_DEVICE;
503 else
504 plat->init_type = USB_INIT_HOST;
505 } else if (is_mx7()) {
506 phy_status = (void __iomem *)(addr +
507 USBNC_PHY_STATUS_OFFSET);
508 val = readl(phy_status);
509
510 if (val & USBNC_PHYSTATUS_ID_DIG)
511 plat->init_type = USB_INIT_DEVICE;
512 else
513 plat->init_type = USB_INIT_HOST;
514 } else {
515 return -EINVAL;
516 }
517
518 return 0;
519}
520
521static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
522{
523 struct usb_platdata *plat = dev_get_platdata(dev);
Adam Ford15287f02019-04-03 08:41:56 -0500524 enum usb_dr_mode dr_mode;
Peng Fan9e3eab32016-12-22 17:06:42 +0800525
Kever Yang1b807052020-03-04 08:59:50 +0800526 dr_mode = usb_get_dr_mode(dev->node);
Peng Fan9e3eab32016-12-22 17:06:42 +0800527
Adam Ford15287f02019-04-03 08:41:56 -0500528 switch (dr_mode) {
529 case USB_DR_MODE_HOST:
530 plat->init_type = USB_INIT_HOST;
531 break;
532 case USB_DR_MODE_PERIPHERAL:
533 plat->init_type = USB_INIT_DEVICE;
534 break;
535 case USB_DR_MODE_OTG:
536 case USB_DR_MODE_UNKNOWN:
537 return ehci_usb_phy_mode(dev);
538 };
Peng Fan9e3eab32016-12-22 17:06:42 +0800539
Adam Ford15287f02019-04-03 08:41:56 -0500540 return 0;
Peng Fan9e3eab32016-12-22 17:06:42 +0800541}
542
Marek Vasutd93dda72019-06-24 19:05:47 +0200543static int ehci_usb_bind(struct udevice *dev)
544{
545 /*
546 * TODO:
547 * This driver is only partly converted to DT probing and still uses
548 * a tremendous amount of hard-coded addresses. To make things worse,
549 * the driver depends on specific sequential indexing of controllers,
550 * from which it derives offsets in the PHY and ANATOP register sets.
551 *
552 * Here we attempt to calculate these indexes from DT information as
Igor Opaniuk9c24d012019-10-10 16:09:35 +0300553 * well as we can. The USB controllers on all existing iMX6 SoCs
554 * are placed next to each other, at addresses incremented by 0x200,
555 * and iMX7 their addresses are shifted by 0x10000.
556 * Thus, the index is derived from the multiple of 0x200 (0x10000 for
557 * iMX7) offset from the first controller address.
Marek Vasutd93dda72019-06-24 19:05:47 +0200558 *
559 * However, to complete conversion of this driver to DT probing, the
560 * following has to be done:
561 * - DM clock framework support for iMX must be implemented
562 * - usb_power_config() has to be converted to clock framework
563 * -> Thus, the ad-hoc "index" variable goes away.
564 * - USB PHY handling has to be factored out into separate driver
565 * -> Thus, the ad-hoc "index" variable goes away from the PHY
566 * code, the PHY driver must parse it's address from DT. This
567 * USB driver must find the PHY driver via DT phandle.
568 * -> usb_power_config() shall be moved to PHY driver
569 * With these changes in place, the ad-hoc indexing goes away and
570 * the driver is fully converted to DT probing.
571 */
Igor Opaniuk9c24d012019-10-10 16:09:35 +0300572 u32 controller_spacing = is_mx7() ? 0x10000 : 0x200;
573 fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
Marek Vasutd93dda72019-06-24 19:05:47 +0200574
Igor Opaniuk9c24d012019-10-10 16:09:35 +0300575 dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;
Marek Vasutd93dda72019-06-24 19:05:47 +0200576
577 return 0;
578}
579
Peng Fan5c363c12016-06-17 14:19:27 +0800580static int ehci_usb_probe(struct udevice *dev)
581{
582 struct usb_platdata *plat = dev_get_platdata(dev);
Masahiro Yamada1096ae12020-07-17 14:36:46 +0900583 struct usb_ehci *ehci = dev_read_addr_ptr(dev);
Peng Fan5c363c12016-06-17 14:19:27 +0800584 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
Peng Fan13351332016-12-22 17:06:43 +0800585 enum usb_init_type type = plat->init_type;
Peng Fan5c363c12016-06-17 14:19:27 +0800586 struct ehci_hccr *hccr;
587 struct ehci_hcor *hcor;
588 int ret;
589
Peng Fanf8b27192020-05-01 22:08:36 +0800590 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
591 if (usb_fused((ulong)ehci)) {
592 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
593 (ulong)ehci);
594 return -ENODEV;
595 }
596 }
597
Peng Fan5c363c12016-06-17 14:19:27 +0800598 priv->ehci = ehci;
599 priv->portnr = dev->seq;
Peng Fan13351332016-12-22 17:06:43 +0800600 priv->init_type = type;
601
Abel Vesa888a9462019-02-01 16:40:08 +0000602#if CONFIG_IS_ENABLED(DM_REGULATOR)
Peng Fan13351332016-12-22 17:06:43 +0800603 ret = device_get_supply_regulator(dev, "vbus-supply",
604 &priv->vbus_supply);
605 if (ret)
606 debug("%s: No vbus supply\n", dev->name);
Abel Vesa888a9462019-02-01 16:40:08 +0000607#endif
Peng Fan5c363c12016-06-17 14:19:27 +0800608 ret = ehci_mx6_common_init(ehci, priv->portnr);
609 if (ret)
610 return ret;
611
Abel Vesa888a9462019-02-01 16:40:08 +0000612#if CONFIG_IS_ENABLED(DM_REGULATOR)
Peng Fan13351332016-12-22 17:06:43 +0800613 if (priv->vbus_supply) {
614 ret = regulator_set_enable(priv->vbus_supply,
615 (type == USB_INIT_DEVICE) ?
616 false : true);
Marek Vasut27370452020-05-21 23:32:23 +0200617 if (ret && ret != -ENOSYS) {
Marek Vasuta86d51a2020-05-21 23:34:06 +0200618 printf("Error enabling VBUS supply (ret=%i)\n", ret);
Peng Fan13351332016-12-22 17:06:43 +0800619 return ret;
620 }
621 }
Abel Vesa888a9462019-02-01 16:40:08 +0000622#endif
Peng Fan5c363c12016-06-17 14:19:27 +0800623
624 if (priv->init_type == USB_INIT_HOST) {
625 setbits_le32(&ehci->usbmode, CM_HOST);
626 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
627 setbits_le32(&ehci->portsc, USB_EN);
628 }
629
630 mdelay(10);
631
632 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
633 hcor = (struct ehci_hcor *)((uint32_t)hccr +
634 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
635
636 return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
637}
638
Peng Fan5c363c12016-06-17 14:19:27 +0800639static const struct udevice_id mx6_usb_ids[] = {
640 { .compatible = "fsl,imx27-usb" },
641 { }
642};
643
644U_BOOT_DRIVER(usb_mx6) = {
645 .name = "ehci_mx6",
646 .id = UCLASS_USB,
647 .of_match = mx6_usb_ids,
Peng Fan9e3eab32016-12-22 17:06:42 +0800648 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
Marek Vasutd93dda72019-06-24 19:05:47 +0200649 .bind = ehci_usb_bind,
Peng Fan5c363c12016-06-17 14:19:27 +0800650 .probe = ehci_usb_probe,
Masahiro Yamadad41919b2016-09-06 22:17:34 +0900651 .remove = ehci_deregister,
Peng Fan5c363c12016-06-17 14:19:27 +0800652 .ops = &ehci_usb_ops,
653 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
654 .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
655 .flags = DM_FLAG_ALLOC_PRIV_DMA,
656};
657#endif